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    Searched defs:Registers (Results 1 - 13 of 13) sorted by relevancy

  /src/external/gpl3/gcc/dist/libsanitizer/hwasan/
hwasan_registers.h 23 struct Registers {
27 __attribute__((always_inline, unused)) static Registers GetRegisters() {
28 Registers regs;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUPALMetadata.h 27 msgpack::DocNode Registers;
120 // Reference (create if necessary) the node for the registers map.
123 // Get (create if necessary) the registers map.
AMDGPUPALMetadata.cpp 54 // store as Registers[key]=value in the map.
272 // Table of registers.
277 // Registers that code generation sets/modifies metadata for.
298 // Registers not known to code generation.
661 // but first change the registers map to use names.
683 // Restore original registers map.
699 auto Registers = getRegisters();
700 if (Registers.getMap().empty())
704 for (auto I : Registers.getMap()) {
721 // In the registers map, some keys may be of the form "0xa19
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  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
RegisterAliasing.h 27 // Returns the registers that are aliased by the ones set in SourceBits.
32 // aliased registers.
53 // Retrieves all the touched registers as a BitVector.
72 PackedVector<size_t, 10> Origins; // Max 1024 physical registers.
84 // Convenient function to retrieve the registers the function body can't use.
101 Registers;
113 // Returns a debug string for the list of registers.
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MicroMipsSizeReduction.cpp 377 // Returns true if the registers Reg1 and Reg2 are consecutive
379 constexpr std::array<unsigned, 31> Registers = {
386 for (uint8_t i = 0; i < Registers.size() - 1; i++) {
387 if (Registers[i] == Reg1) {
388 if (Registers[i + 1] == Reg2)
397 // Returns true if registers and offsets are consecutive
594 // Returns true if the registers can be a pair of destination
595 // registers in MOVEP instruction
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
AsmMatcherEmitter.cpp 202 /// For register classes: the records for all the registers in this class.
203 RegisterSet Registers;
236 // Registers classes are only related to registers classes, and only if
244 std::set_intersection(Registers.begin(), Registers.end(),
245 RHS.Registers.begin(), RHS.Registers.end(),
315 // Tokens sort before registers, which sort before user classes.
349 // For register sets, sort by number of registers. This guarantees tha
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AsmWriterEmitter.cpp 551 const std::deque<CodeGenRegister> &Registers) {
553 SmallVector<std::string, 4> AsmNames(Registers.size());
555 for (const auto &Reg : Registers) {
594 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
606 const auto &Registers = Target.getRegBank().getRegisters();
609 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
620 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
626 emitRegisterNameString(O, R->getName(), Registers);
628 emitRegisterNameString(O, "", Registers);
CodeGenRegisters.h 79 // Are all super-registers containing this SubRegIndex covered by their
80 // sub-registers?
172 // Lazily compute a map of all sub-registers.
173 // This includes unique entries for all sub-sub-registers.
176 // Compute extra sub-registers by combining the existing sub-registers.
179 // Add this as a super-register to all sub-registers after the sub-register
184 assert(SubRegsComplete && "Must precompute sub-registers");
188 // Add sub-registers to OSet following a pre-order defined by the .td file.
200 // Get the list of super-registers in topological order, small to large
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RegisterInfoEmitter.cpp 66 // runEnums - Print out enum values for all of the registers.
101 // runEnums - Print out enum values for all of the registers.
104 const auto &Registers = Bank.getRegisters();
107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
109 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
126 for (const auto &Reg : Registers)
128 assert(Registers.size() == Registers.back().EnumValue &&
130 OS << " NUM_TARGET_REGS // " << Registers.size()+1 << "\n";
283 << "// This limit must be adjusted dynamically for reserved registers.\n
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CodeGenRegisters.cpp 178 // Also compute leading super-registers. Each register has a list of
179 // covered-by-subregs super-registers where it appears as the first explicit
187 // registers, so build a symmetric graph by adding links in both ends.
203 // Iterate over all register units in a set of registers.
281 // Map explicit sub-registers first, so the names take precedence.
282 // The inherited sub-registers are mapped below.
382 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
408 // sub-registers, the other registers won't contribute any more units.
429 // registers
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  /src/external/apache2/llvm/dist/clang/utils/TableGen/
MveEmitter.cpp 314 unsigned Registers;
317 MultiVectorType(unsigned Registers, const VectorType *Element)
319 Registers(Registers) {}
321 return Registers * Element->sizeInBits();
323 unsigned registers() const { return Registers; } function in class:__anon3610::MultiVectorType
327 return Element->cNameBase() + "x" + utostr(Registers);
1005 const MultiVectorType *getMultiVectorType(unsigned Registers,
1007 std::pair<std::string, unsigned> key(VT->cNameBase(), Registers);
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 517 // arm64_32 has 32-bit pointers held in 64-bit registers. Because of that,
2935 static const MCPhysReg Registers[6][8] = {
2957 SrcReg = Registers[0][GPRIdx++];
2961 SrcReg = Registers[1][GPRIdx++];
2964 SrcReg = Registers[2][FPRIdx++];
2967 SrcReg = Registers[3][FPRIdx++];
2970 SrcReg = Registers[4][FPRIdx++];
2973 SrcReg = Registers[5][FPRIdx++];
3100 // Copy all of the result registers out of their specified physreg.
3247 // Add a register mask with the call-preserved registers
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 253 // Map of register aliases registers via the .req directive.
774 SmallVector<unsigned, 8> Registers;
829 // A vector register list is a sequential list of 1 to 4 registers.
975 return Registers;
1716 // Thumb reg+reg addressing is simple. Just two registers, a base and
3339 // of q-registers by its base register and length, and it will
3715 assert(Regs.size() > 0 && "RegList contains no registers?");
3739 Op->Registers.push_back(P.second);
4119 // Some FPUs only have 16 D registers, so D16-D31 are invalid
4253 // Also check for an index operand. This is only legal for vector registers,
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