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    Searched defs:Rt2 (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/arch/aarch64/aarch64/
db_trace.c 390 uint64_t Rt2 = (insn >> 10) & 0x1f;
397 } else if (Rt2 == 30) {
411 if (func_entry_autodetect && Rt1 == 29 && Rt2 == 30)
420 uint64_t Rt2 = (insn >> 10) & 0x1f;
426 Rt2, imm7);
429 } else if (Rt2 == 30) {
  /src/external/gpl3/gdb/dist/sim/arm/
thumbemu.c 322 ARMword Rt2 = ntBITS (8, 11);
328 tASSERT (Rt2 == Rt + 1);
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
350 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
  /src/external/gpl3/gdb.old/dist/sim/arm/
thumbemu.c 322 ARMword Rt2 = ntBITS (8, 11);
328 tASSERT (Rt2 == Rt + 1);
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
350 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 1336 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1390 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1399 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1408 Rt == Rt2)
1419 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1483 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1496 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1507 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1518 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1529 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 2006 unsigned Rt2 = Rt + 1;
2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2034 if (Rt2 == 15)
2053 if (Rt2 == 15)
2059 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2063 if (writeback && (Rn == Rt || Rn == Rt2))
5475 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5480 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 4200 // the Rt == Rt2. All of those are undefined behaviour.
4208 unsigned Rt2 = Inst.getOperand(2).getReg();
4213 if (RI->isSubRegisterEq(Rn, Rt2))
4225 unsigned Rt2 = Inst.getOperand(1).getReg();
4226 if (Rt == Rt2)
4227 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4238 unsigned Rt2 = Inst.getOperand(2).getReg();
4239 if (Rt == Rt2)
4240 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4254 unsigned Rt2 = Inst.getOperand(2).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 5813 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5817 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
6932 // We have to be careful to not emit an invalid Rt2 here, because the rest of
7416 unsigned Rt2 = MRI->getEncodingValue(Reg2);
7418 // Rt2 must be Rt + 1 and Rt must be even.
7419 if (Rt + 1 != Rt2 || (Rt & 1)) {
7537 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
7550 // Rt2 must be Rt + 1.
7551 if (Rt2 != Rt + 1) {
7565 if (Rt2 == Rt
    [all...]
  /src/external/gpl3/binutils/dist/gas/config/
tc-arm.c 6679 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6902 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
7957 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
19817 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19823 Rt2 = 3;
19829 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
19832 || inst.operands[Rt2].reg == REG_SP,
19835 || inst.operands[Rt2].reg == REG_PC,
19841 inst.instruction |= inst.operands[Rt2].reg << 16;
19899 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-arm.c 6682 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6905 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
7960 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
19820 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19826 Rt2 = 3;
19832 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
19835 || inst.operands[Rt2].reg == REG_SP,
19838 || inst.operands[Rt2].reg == REG_PC,
19844 inst.instruction |= inst.operands[Rt2].reg << 16;
19902 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]
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