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    Searched defs:Shifted (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 2334 unsigned Shifted = 0;
2341 Shifted += 2;
2350 if (Shifted > 24)
2351 Value = Value >> (Shifted - 24);
2353 Value = Value << (24 - Shifted);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstCombineIntrinsic.cpp 1002 // describes a subset of the input bits shifted to the appropriate
1007 Value *Shifted = IC.Builder.CreateLShr(Masked,
1010 return IC.replaceInstUsesWith(II, Shifted);
1047 // describes a subset of the input bits shifted to the appropriate
1051 Value *Shifted = IC.Builder.CreateShl(Input,
1054 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1));
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
SimplifyCFG.cpp 6056 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted");
6058 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit");
6190 // Now we have signed numbers that have been shifted so that, given enough
6221 // shift and puts the shifted-off bits in the uppermost bits. If any of these
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 2977 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt);
2978 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
6698 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
6702 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
6796 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt});
6797 MIRBuilder.buildTrunc(Result, Shifted);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 4523 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT,
4525 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
4553 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT,
4555 RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
5150 // The expected mask is shifted left when the AND is found around SHL
5162 // The expected mask is now in fact shifted left for SRL, so reverse the
5168 // Use a default shifted mask of all-ones if there's no AND, truncated
5201 // patterns. They may be shifted left in certain circumstances.
5307 // patterns. They may be shifted left in certain circumstances.
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 7251 // Every load here needs to be shifted, otherwise a full register load
9229 // Figure out what shift amount will be used by altivec if shifted by i in
11314 // For unsigned comparisons, we can directly compare the shifted values.
12935 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode,
12937 auto Final = Shifted;
12941 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted,
14763 // it need to be shifted to the right side before STBRX.
15765 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
16189 // 2. If the multiplier after shifted fits 16 bits, an extra shift
17298 // zero or load-immediate-shifted and the displacement will b
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