| /src/external/apache2/llvm/dist/llvm/tools/llvm-pdbutil/ |
| PrettyCompilandDumper.cpp | 194 uint64_t VA = Symbol.getVirtualAddress();
197 WithColor(Printer, PDB_ColorItem::Address).get() << format_hex(VA, 10);
202 << "[" << format_hex(VA, 10) << " - "
203 << format_hex(VA + Symbol.getLength(), 10) << "]";
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-xray/ |
| xray-graph.cpp | 420 const auto &VA = V.second;
424 << escapeString(VA.SymbolName.size() > 40
425 ? VA.SymbolName.substr(0, 40) + "..."
426 : VA.SymbolName);
428 OS << "|" << VA.S.getString(VT) << "}\"";
434 std::sqrt(VA.S.getDouble(VC) / G.GraphVertexMax.getDouble(VC)))
|
| /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| RuntimeDyldCOFFAArch64.h | 295 // The 32-bit VA of the target.
296 uint32_t VA = Value + RE.Addend;
297 write32le(Target, VA);
342 // The 64-bit VA of the relocation target.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMCallLowering.cpp | 112 CCValAssign &VA) override {
113 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
114 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
116 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
117 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
119 Register ExtReg = extendRegister(ValVReg, VA);
125 MachinePointerInfo &MPO, CCValAssign &VA) override {
129 Register ExtReg = extendRegister(ValVReg, VA);
131 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
140 CCValAssign VA = VAs[0]
[all...] |
| ARMFastISel.cpp | 1887 CCValAssign &VA = ArgLocs[i];
1888 MVT ArgVT = ArgVTs[VA.getValNo()];
1895 if (VA.isRegLoc() && !VA.needsCustom()) {
1897 } else if (VA.needsCustom()) {
1899 if (VA.getLocVT() != MVT::f64 ||
1901 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1937 CCValAssign &VA = ArgLocs[i];
1938 const Value *ArgVal = Args[VA.getValNo()];
1939 Register Arg = ArgRegs[VA.getValNo()]
[all...] |
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.cp/ |
| virtfunc.cc | 24 // V : VA VB
32 class VA
35 int va; member in class:VA
46 class V : public VA, public VB
112 VA va; variable
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.cp/ |
| virtfunc.cc | 24 // V : VA VB
32 class VA
35 int va; member in class:VA
46 class V : public VA, public VB
112 VA va; variable
|
| /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/PDB/Native/ |
| NativeSession.cpp | 212 bool NativeSession::addressForVA(uint64_t VA, uint32_t &Section,
214 uint32_t RVA = VA - getLoadAddress();
285 uint64_t VA = getVAFromSectOffset(Section, Offset);
286 return Cache.findLineNumbersByVA(VA, Length);
394 bool NativeSession::moduleIndexForVA(uint64_t VA, uint16_t &ModuleIndex) const {
396 auto Iter = AddrToModuleIndex.find(VA);
429 uint64_t VA = Session.getVAFromSectOffset(C.ISect, C.Off);
430 uint64_t End = VA + C.Size;
434 if (!AddrMap.overlaps(VA, End))
435 AddrMap.insert(VA, End, C.Imod)
[all...] |
| SymbolCache.cpp | 494 uint64_t VA =
503 Entries.push_back({VA, Line, ColNum, Group.NameIndex, false});
528 SymbolCache::findLineNumbersByVA(uint64_t VA, uint32_t Length) const {
530 if (!Session.moduleIndexForVA(VA, Modi))
540 return (E.Addr < VA || (E.Addr == VA && E.IsTerminalEntry));
544 if (LineIter == Lines.end() || LineIter->Addr > VA) {
574 if (LineIter->Addr > VA + Length)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 262 CCValAssign &VA = ArgLocs[i];
266 switch (VA.getLocInfo()) {
272 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
275 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
278 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
284 if (VA.isRegLoc()) {
285 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
287 assert(VA.isMemLoc() && "Must be register or memory argument.");
292 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
376 const CCValAssign &VA = RVLocs[i]
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 319 for (auto &VA : ArgLocs) {
320 if (VA.isRegLoc()) {
322 EVT RegVT = VA.getLocVT();
334 RegInfo.addLiveIn(VA.getLocReg(), VReg);
339 if (VA.getLocInfo() == CCValAssign::SExt)
341 DAG.getValueType(VA.getValVT()));
342 else if (VA.getLocInfo() == CCValAssign::ZExt)
344 DAG.getValueType(VA.getValVT()));
346 if (VA.getLocInfo() != CCValAssign::Full)
347 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsCallLowering.cpp | 27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
29 if (VA.isRegLoc()) {
30 assignValueToReg(VReg, VA, VT);
31 } else if (VA.isMemLoc()) {
32 assignValueToAddress(VReg, VA);
97 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
100 Register getStackAddress(const CCValAssign &VA,
103 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
114 MachineInstrBuilder buildLoad(const DstOp &Res, const CCValAssign &VA) {
116 Register Addr = getStackAddress(VA, MMO)
[all...] |
| MipsFastISel.cpp | 1153 CCValAssign &VA = ArgLocs[i];
1154 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1155 MVT ArgVT = OutVTs[VA.getValNo()];
1160 VA.convertToReg(Mips::F12);
1163 VA.convertToReg(Mips::D6_64);
1165 VA.convertToReg(Mips::D6);
1170 VA.convertToReg(Mips::F14);
1173 VA.convertToReg(Mips::D7_64);
1175 VA.convertToReg(Mips::D7);
1181 VA.isMemLoc())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 457 CCValAssign &VA = ArgLocs[i];
458 if (VA.isRegLoc()) {
460 EVT RegVT = VA.getLocVT();
464 RegInfo.addLiveIn(VA.getLocReg(), VReg);
470 if (VA.getLocInfo() == CCValAssign::SExt)
472 DAG.getValueType(VA.getValVT()));
473 else if (VA.getLocInfo() == CCValAssign::ZExt)
475 DAG.getValueType(VA.getValVT()));
477 if (VA.getLocInfo() != CCValAssign::Full)
478 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 639 CCValAssign &VA = ArgLocs[i];
640 if (VA.isRegLoc()) {
642 EVT RegVT = VA.getLocVT();
654 RegInfo.addLiveIn(VA.getLocReg(), VReg);
660 if (VA.getLocInfo() == CCValAssign::SExt)
662 DAG.getValueType(VA.getValVT()));
663 else if (VA.getLocInfo() == CCValAssign::ZExt)
665 DAG.getValueType(VA.getValVT()));
667 if (VA.getLocInfo() != CCValAssign::Full)
668 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 2654 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
2659 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2673 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
2702 CCValAssign &VA = RVLocs[I];
2703 assert(VA.isRegLoc() && "Can only return in registers!");
2707 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
2713 if (VA.getLocInfo() == CCValAssign::SExt)
2714 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2715 else if (VA.getLocInfo() == CCValAssign::ZExt)
2716 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombinePHI.cpp | 1379 Value *VA = PN.getIncomingValue(i);
1380 if (isKnownNonZero(VA, DL, 0, &AC, CtxI, &DT)) {
1384 if (NonZeroConst != VA) {
1440 Value *VA = PN.getIncomingValue(i);
1446 PN.setIncomingValue(j, VA);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 1506 CCValAssign &VA = ArgLocs[i];
1509 EVT MemVT = VA.getLocVT();
1516 Register Reg = MF.addLiveIn(VA.getLocReg(), &R600::R600_Reg128RegClass);
1542 unsigned PartOffset = VA.getLocMemOffset();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 1145 for (CCValAssign &VA : ArgLocs) {
1148 if (VA.isRegLoc()) {
1149 EVT RegVT = VA.getLocVT();
1159 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1168 switch (VA.getLocInfo()) {
1174 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1178 DAG.getValueType(VA.getValVT()));
1179 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1183 DAG.getValueType(VA.getValVT()));
1184 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 1391 CCValAssign &VA = ArgLocs[I];
1392 MVT ArgVT = ArgVTs[VA.getValNo()];
1397 !VA.isRegLoc() || VA.needsCustom())
1401 if (VA.getLocInfo() == CCValAssign::BCvt)
1429 CCValAssign &VA = ArgLocs[I];
1430 unsigned Arg = ArgRegs[VA.getValNo()];
1431 MVT ArgVT = ArgVTs[VA.getValNo()];
1434 switch (VA.getLocInfo()) {
1440 MVT DestVT = VA.getLocVT()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1067 const CCValAssign &VA = RVLocs[i];
1068 if (VA.isRegLoc()) {
1069 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
1074 assert(VA.isMemLoc());
1075 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
1142 CCValAssign &VA = ArgLocs[i];
1146 switch (VA.getLocInfo()) {
1150 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1153 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 810 SDNode *VA = CurDAG->getMachineNode(Hexagon::S2_valignrb, dl, ResTy,
813 ReplaceNode(N, VA);
|
| HexagonISelLowering.cpp | 221 CCValAssign &VA = RVLocs[i];
224 switch (VA.getLocInfo()) {
231 Val = DAG.getBitcast(VA.getLocVT(), Val);
234 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val);
237 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val);
240 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val);
244 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag);
248 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
443 CCValAssign &VA = ArgLocs[i]
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 247 const CCValAssign &VA) {
316 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) {
380 const CCValAssign &VA,
389 if (VA.getLocInfo() == CCValAssign::Indirect)
390 ValVT = VA.getLocVT();
392 ValVT = VA.getValVT();
396 int Offset = VA.getLocMemOffset();
397 if (VA.getValVT() == MVT::i8) {
399 } else if (VA.getValVT() == MVT::i16) {
428 if (VA.getLocInfo() == CCValAssign::ZExt)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 232 CCValAssign &VA = RVLocs[i];
233 assert(VA.isRegLoc() && "Can only return in registers!");
237 if (VA.needsCustom()) {
238 assert(VA.getLocVT() == MVT::v2i32);
249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag);
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
252 VA = RVLocs[++i]; // skip ahead to next loc
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag)
[all...] |
