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    Searched defs:VR2 (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 3029 // li $vr2, 0
3034 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
3067 Register VR2 = RegInfo.createVirtualRegister(RC);
3068 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3080 .addReg(VR2)
  /src/external/gpl3/binutils/dist/opcodes/
v850-opc.c 1271 #define VR2 (VR1 + 1)
1274 #define CACHEOP (VR2 + 1)
1607 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },
  /src/external/gpl3/binutils.old/dist/opcodes/
v850-opc.c 1271 #define VR2 (VR1 + 1)
1274 #define CACHEOP (VR2 + 1)
1607 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },
  /src/external/gpl3/gdb/dist/opcodes/
v850-opc.c 1271 #define VR2 (VR1 + 1)
1274 #define CACHEOP (VR2 + 1)
1607 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },
  /src/external/gpl3/gdb.old/dist/opcodes/
v850-opc.c 1271 #define VR2 (VR1 + 1)
1274 #define CACHEOP (VR2 + 1)
1607 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },

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