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Searched defs:WR_CC (Results 1 - 8 of 8) sorted by relevancy

/src/external/gpl3/binutils/dist/opcodes/
micromips-opc.c	238 #define WR_CC INSN_WRITE_COND_CODE 461 {"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 462 {"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 463 {"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 }, 464 {"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I1, 0, 0 }, 465 {"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 466 {"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 467 {"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 468 {"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 469 {"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 } [all...]
mips-opc.c	244 #define WR_CC INSN_WRITE_COND_CODE 801 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 802 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 }, 803 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, I37 }, 804 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I4_32, 0, I37 }, 805 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I5_33\|IL2F, 0, I37 }, 806 {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, IL2E, 0, 0 }, 807 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I5_33, 0, I37 }, 808 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 809 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 } [all...]
/src/external/gpl3/binutils.old/dist/opcodes/
micromips-opc.c	238 #define WR_CC INSN_WRITE_COND_CODE 461 {"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 462 {"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 463 {"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 }, 464 {"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I1, 0, 0 }, 465 {"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 466 {"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 467 {"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 468 {"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 469 {"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 } [all...]
mips-opc.c	244 #define WR_CC INSN_WRITE_COND_CODE 801 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 802 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 }, 803 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, I37 }, 804 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I4_32, 0, I37 }, 805 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I5_33\|IL2F, 0, I37 }, 806 {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, IL2E, 0, 0 }, 807 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I5_33, 0, I37 }, 808 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 809 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 } [all...]
/src/external/gpl3/gdb/dist/opcodes/
micromips-opc.c	238 #define WR_CC INSN_WRITE_COND_CODE 461 {"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 462 {"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 463 {"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 }, 464 {"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I1, 0, 0 }, 465 {"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 466 {"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 467 {"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 468 {"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 469 {"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 } [all...]
mips-opc.c	244 #define WR_CC INSN_WRITE_COND_CODE 801 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 802 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 }, 803 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, I37 }, 804 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I4_32, 0, I37 }, 805 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I5_33\|IL2F, 0, I37 }, 806 {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, IL2E, 0, 0 }, 807 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I5_33, 0, I37 }, 808 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 809 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 } [all...]
/src/external/gpl3/gdb.old/dist/opcodes/
micromips-opc.c	230 #define WR_CC INSN_WRITE_COND_CODE 450 {"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 451 {"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 452 {"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 }, 453 {"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I1, 0, 0 }, 454 {"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 455 {"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 456 {"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, 0 }, 457 {"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I1, 0, 0 }, 458 {"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, 0 } [all...]
mips-opc.c	243 #define WR_CC INSN_WRITE_COND_CODE 800 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 801 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 }, 802 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_S, 0, I1, 0, I37 }, 803 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_S, 0, I4_32, 0, I37 }, 804 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I5_33\|IL2F, 0, I37 }, 805 {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, IL2E, 0, 0 }, 806 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I5_33, 0, I37 }, 807 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, I1, 0, SF\|I37 }, 808 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2\|RD_3\|WR_CC\|FP_D, 0, I4_32, 0, I37 } [all...]

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