| sunxi_hdmiphy.c | 54 #define ANA_CFG1 0x020
193 device_printf(sc->sc_dev, "ANA_CFG1: %#x\tANA_CFG2: %#x\tANA_CFG3: %#x\n",
194 PHY_READ(sc, ANA_CFG1), PHY_READ(sc, ANA_CFG2), PHY_READ(sc, ANA_CFG3));
208 PHY_WRITE(sc, ANA_CFG1, 0);
210 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENBI);
214 PHY_SET(sc, ANA_CFG1, ANA_CFG1_TMDSCLK_EN);
217 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENVBS);
221 PHY_SET(sc, ANA_CFG1, ANA_CFG1_LDOEN);
225 PHY_SET(sc, ANA_CFG1, ANA_CFG1_CKEN);
229 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENRCAL)
274 uint32_t ana_cfg1; member in struct:sun8i_h3_hdmiphy_init
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