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/src/sys/arch/arm/amlogic/
mesong12_clkc.c	1422 uint32_t cntl0, cntl4, cntl3, cntl5; local in function:mesong12_clk_pcie_pll_set_rate 1435 cntl5 = __SHIFTIN(6, HHI_PCIE_PLL_CNTL5_PCIE_HCSL_ADJ_LDO) | 1453 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL5, cntl5); 1455 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL5, cntl5 |

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