radeon_sumo_dpm.c | 504 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6); local in function:sumo_set_ds_dividers 506 dpm_ctrl &= ~(0x7 << (index * 3)); 507 dpm_ctrl |= (divider << (index * 3)); 508 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl); 518 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11); local in function:sumo_set_ss_dividers 520 dpm_ctrl &= ~(0x7 << (index * 3)); 521 dpm_ctrl |= (divider << (index * 3)); 522 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
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