| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_dpp.c | 56 void dpp20_read_state(struct dpp *dpp_base, argument
80 dpp2_power_on_obuf(struct dpp * dpp_base,bool power_on) argument
95 dpp2_dummy_program_input_lut(struct dpp * dpp_base,const struct dc_gamma * gamma) argument
100 dpp2_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut) argument
254 dpp2_cnv_set_bias_scale(struct dpp * dpp_base,struct dc_bias_and_scale * bias_and_scale) argument
325 dpp2_cnv_set_alpha_keyer(struct dpp * dpp_base,struct cnv_color_keyer_params * color_keyer) argument
348 dpp2_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes) argument
[all...] |
| H A D | amdgpu_dcn20_dpp_cm.c | 55 dpp2_enable_cm_block(struct dpp * dpp_base) argument
69 dpp2_degamma_ram_inuse(struct dpp * dpp_base,bool * ram_a_inuse) argument
90 dpp2_program_degamma_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num,bool is_ram_a) argument
121 dpp2_set_degamma_pwl(struct dpp * dpp_base,const struct pwl_params * params) argument
139 dpp2_set_degamma(struct dpp * dpp_base,enum ipp_degamma_mode mode) argument
218 dpp2_cm_set_gamut_remap(struct dpp * dpp_base,const struct dpp_grph_csc_adjustment * adjust) argument
242 dpp2_program_input_csc(struct dpp * dpp_base,enum dc_color_space color_space,enum dcn20_input_csc_select input_select,const struct out_csc_color_matrix * tbl_entry) argument
315 dpp20_power_on_blnd_lut(struct dpp * dpp_base,bool power_on) argument
326 dpp20_configure_blnd_lut(struct dpp * dpp_base,bool is_ram_a) argument
339 dpp20_program_blnd_pwl(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num) argument
391 dpp20_program_blnd_luta_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
419 dpp20_program_blnd_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
446 dpp20_get_blndgam_current(struct dpp * dpp_base) argument
472 dpp20_program_blnd_lut(struct dpp * dpp_base,const struct pwl_params * params) argument
507 dpp20_program_shaper_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num) argument
539 dpp20_get_shaper_current(struct dpp * dpp_base) argument
565 dpp20_configure_shaper_lut(struct dpp * dpp_base,bool is_ram_a) argument
580 dpp20_program_shaper_luta_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
730 dpp20_program_shaper_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
881 dpp20_program_shaper(struct dpp * dpp_base,const struct pwl_params * params) argument
917 get3dlut_config(struct dpp * dpp_base,bool * is_17x17x17,bool * is_12bits_color_channel) argument
963 dpp20_set_3dlut_mode(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17) argument
984 dpp20_select_3dlut_ram(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits) argument
999 dpp20_set3dlut_ram12(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries) argument
1033 dpp20_set3dlut_ram10(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries) argument
1054 dpp20_select_3dlut_ram_mask(struct dpp * dpp_base,uint32_t ram_selection_mask) argument
1065 dpp20_program_3dlut(struct dpp * dpp_base,struct tetrahedral_params * params) argument
1145 dpp2_set_hdr_multiplier(struct dpp * dpp_base,uint32_t multiplier) argument
[all...] |
| H A D | amdgpu_dcn20_hwseq.c | 782 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn20_set_blend_lut
804 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn20_set_shaper_3dlut
835 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn20_set_input_transfer_func
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_dpp.c | 99 void dpp_read_state(struct dpp *dpp_base, argument
208 void dpp_reset(struct dpp *dpp_base) argument
223 dpp1_cm_set_regamma_pwl(struct dpp * dpp_base,const struct pwl_params * params,enum opp_regamma mode) argument
278 dpp1_set_degamma_format_float(struct dpp * dpp_base,bool is_float) argument
293 dpp1_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut) argument
428 dpp1_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes) argument
449 dpp1_set_cursor_position(struct dpp * dpp_base,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param,uint32_t width,uint32_t height) argument
491 dpp1_cnv_set_optional_cursor_attributes(struct dpp * dpp_base,struct dpp_cursor_attributes * attr) argument
503 dpp1_dppclk_control(struct dpp * dpp_base,bool dppclk_div,bool enable) argument
[all...] |
| H A D | amdgpu_dcn10_dpp_cm.c | 323 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, argument
333 void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, argument
165 dpp1_cm_set_gamut_remap(struct dpp * dpp_base,const struct dpp_grph_csc_adjustment * adjust) argument
244 dpp1_cm_set_output_csc_default(struct dpp * dpp_base,enum dc_color_space colorspace) argument
314 dpp1_cm_set_output_csc_adjustment(struct dpp * dpp_base,const uint16_t * regval) argument
355 dpp1_cm_configure_regamma_lut(struct dpp * dpp_base,bool is_ram_a) argument
369 dpp1_cm_program_regamma_luta_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
398 dpp1_cm_program_regamma_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
425 dpp1_program_input_csc(struct dpp * dpp_base,enum dc_color_space color_space,enum dcn10_input_csc_select input_select,const struct out_csc_color_matrix * tbl_entry) argument
501 dpp1_program_bias_and_scale(struct dpp * dpp_base,struct dc_bias_and_scale * params) argument
522 dpp1_program_degamma_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
551 dpp1_program_degamma_luta_settings(struct dpp * dpp_base,const struct pwl_params * params) argument
578 dpp1_power_on_degamma_lut(struct dpp * dpp_base,bool power_on) argument
589 dpp1_enable_cm_block(struct dpp * dpp_base) argument
598 dpp1_set_degamma(struct dpp * dpp_base,enum ipp_degamma_mode mode) argument
628 dpp1_degamma_ram_select(struct dpp * dpp_base,bool use_ram_a) argument
641 dpp1_degamma_ram_inuse(struct dpp * dpp_base,bool * ram_a_inuse) argument
662 dpp1_program_degamma_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num,bool is_ram_a) argument
692 dpp1_set_degamma_pwl(struct dpp * dpp_base,const struct pwl_params * params) argument
710 dpp1_full_bypass(struct dpp * dpp_base) argument
734 dpp1_ingamma_ram_inuse(struct dpp * dpp_base,bool * ram_a_inuse) argument
765 dpp1_program_input_lut(struct dpp * dpp_base,const struct dc_gamma * gamma) argument
814 dpp1_set_hdr_multiplier(struct dpp * dpp_base,uint32_t multiplier) argument
[all...] |
| H A D | amdgpu_dcn10_dpp_dscl.c | 172 dpp1_dscl_get_dscl_mode(struct dpp * dpp_base,const struct scaler_data * data,bool dbg_always_scale) argument
529 dpp1_dscl_set_scaler_auto_scale(struct dpp * dpp_base,const struct scaler_data * scl_data) argument
668 dpp1_dscl_set_scaler_manual_scale(struct dpp * dpp_base,const struct scaler_data * scl_data) argument
[all...] |
| H A D | amdgpu_dcn10_hw_sequencer.c | 1457 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn10_set_input_transfer_func
[all...] |