1 /* $NetBSD: wdc.c,v 1.317 2026/09/06 05:32:19 mlelstv Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.317 2026/09/06 05:32:19 mlelstv Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/kmem.h> 74 #include <sys/syslog.h> 75 #include <sys/proc.h> 76 77 #include <sys/intr.h> 78 #include <sys/bus.h> 79 80 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 81 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 82 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 83 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 84 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 85 #define bus_space_read_stream_2 bus_space_read_2 86 #define bus_space_read_stream_4 bus_space_read_4 87 #define bus_space_write_stream_2 bus_space_write_2 88 #define bus_space_write_stream_4 bus_space_write_4 89 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 90 91 #include <dev/ata/atavar.h> 92 #include <dev/ata/atareg.h> 93 #include <dev/ata/satareg.h> 94 #include <dev/ata/satavar.h> 95 #include <dev/ic/wdcreg.h> 96 #include <dev/ic/wdcvar.h> 97 98 #include "locators.h" 99 100 #include "atapibus.h" 101 #include "wd.h" 102 #include "sata.h" 103 104 #define WDCDELAY 100 /* 100 microseconds */ 105 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 106 #if 0 107 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 108 #define WDCNDELAY_DEBUG 50 109 #endif 110 111 /* When polling wait that much and then kpause for 1/hz seconds */ 112 #define WDCDELAY_POLL 1 /* ms */ 113 114 /* timeout for the control commands */ 115 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 116 117 /* 118 * timeout when waiting for BSY to deassert when probing. 119 * set to 5s. From the standards this could be up to 31, but we can't 120 * wait that much at boot time, and 5s seems to be enough. 121 */ 122 #define WDC_PROBE_WAIT 5 123 124 125 #if NWD > 0 126 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 127 #else 128 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 129 const struct ata_bustype wdc_ata_bustype = { 130 .bustype_type = SCSIPI_BUSTYPE_ATA, 131 .ata_bio = NULL, 132 .ata_reset_drive = NULL, 133 .ata_reset_channel = wdc_reset_channel, 134 .ata_exec_command = wdc_exec_command, 135 .ata_get_params = NULL, 136 .ata_addref = NULL, 137 .ata_delref = NULL, 138 .ata_killpending = NULL, 139 .ata_recovery = NULL, 140 }; 141 #endif 142 143 /* Flags to wdcreset(). */ 144 #define RESET_POLL 1 145 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 146 147 static int wdcprobe1(struct ata_channel *, int); 148 static int wdcreset(struct ata_channel *, int); 149 static void __wdcerror(struct ata_channel *, const char *); 150 static int __wdcwait_reset(struct ata_channel *, int, int); 151 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 152 static int __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 154 static void __wdccommand_kill_xfer(struct ata_channel *, 155 struct ata_xfer *, int); 156 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 157 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 158 static int __wdcwait(struct ata_channel *, int, int, int, int *); 159 160 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 161 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 162 #define DEBUG_INTR 0x01 163 #define DEBUG_XFERS 0x02 164 #define DEBUG_STATUS 0x04 165 #define DEBUG_FUNCS 0x08 166 #define DEBUG_PROBE 0x10 167 #define DEBUG_DETACH 0x20 168 #define DEBUG_DELAY 0x40 169 #ifdef ATADEBUG 170 extern int atadebug_mask; /* init'ed in ata.c */ 171 int wdc_nxfer = 0; 172 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 173 #else 174 #define ATADEBUG_PRINT(args, level) 175 #endif 176 177 /* 178 * Initialize the "shadow register" handles for a standard wdc controller. 179 */ 180 void 181 wdc_init_shadow_regs(struct wdc_regs *wdr) 182 { 183 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 184 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 185 } 186 187 /* 188 * Allocate a wdc_regs array, based on the number of channels. 189 */ 190 void 191 wdc_allocate_regs(struct wdc_softc *wdc) 192 { 193 194 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 195 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 196 } 197 198 #if NSATA > 0 199 /* 200 * probe drives on SATA controllers with standard SATA registers: 201 * bring the PHYs online, read the drive signature and set drive flags 202 * appropriately. 203 */ 204 void 205 wdc_sataprobe(struct ata_channel *chp) 206 { 207 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 208 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 209 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 210 int i; 211 212 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 213 214 /* do this before we take lock */ 215 216 ata_channel_lock(chp); 217 218 /* reset the PHY and bring online */ 219 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 220 wdr->sata_status, AT_WAIT)) { 221 case SStatus_DET_DEV: 222 /* wait 5s for BSY to clear */ 223 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 224 bus_space_write_1(wdr->cmd_iot, 225 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 226 delay(10); /* 400ns delay */ 227 st = bus_space_read_1(wdr->cmd_iot, 228 wdr->cmd_iohs[wd_status], 0); 229 if ((st & WDCS_BSY) == 0) 230 break; 231 ata_delay(chp, 1, "sataprb", AT_WAIT); 232 } 233 if (i == WDC_PROBE_WAIT * hz) 234 aprint_error_dev(chp->ch_atac->atac_dev, 235 "BSY never cleared, status 0x%02x\n", st); 236 sc = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_seccnt], 0); 238 sn = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_sector], 0); 240 cl = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_lo], 0); 242 ch = bus_space_read_1(wdr->cmd_iot, 243 wdr->cmd_iohs[wd_cyl_hi], 0); 244 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 245 "cl=0x%x ch=0x%x\n", 246 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 247 sc, sn, cl, ch), DEBUG_PROBE); 248 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 249 ata_channel_unlock(chp); 250 return; 251 } 252 /* 253 * sc and sn are supposed to be 0x1 for ATAPI, but in some 254 * cases we get wrong values here, so ignore it. 255 */ 256 if (cl == 0x14 && ch == 0xeb) 257 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 258 else 259 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 260 261 /* 262 * issue a reset in case only the interface part of the drive 263 * is up 264 */ 265 if (wdcreset(chp, RESET_SLEEP) != 0) 266 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 267 break; 268 269 default: 270 break; 271 } 272 273 ata_channel_unlock(chp); 274 } 275 #endif /* NSATA > 0 */ 276 277 278 /* Test to see controller with at last one attached drive is there. 279 * Returns a bit for each possible drive found (0x01 for drive 0, 280 * 0x02 for drive 1). 281 * Logic: 282 * - If a status register is at 0xff, assume there is no drive here 283 * (ISA has pull-up resistors). Similarly if the status register has 284 * the value we last wrote to the bus (for IDE interfaces without pullups). 285 * If no drive at all -> return. 286 * - reset the controller, wait for it to complete (may take up to 31s !). 287 * If timeout -> return. 288 * - test ATA/ATAPI signatures. If at last one drive found -> return. 289 * - try an ATA command on the master. 290 */ 291 292 void 293 wdc_drvprobe(struct ata_channel *chp) 294 { 295 struct ataparams params; /* XXX: large struct */ 296 struct atac_softc *atac = chp->ch_atac; 297 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 298 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 299 u_int8_t st0 = 0, st1 = 0; 300 int i, error, tfd; 301 302 ata_channel_lock(chp); 303 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 304 ata_channel_unlock(chp); 305 return; 306 } 307 if (wdcprobe1(chp, 0) == 0) { 308 /* No drives, abort the attach here. */ 309 atabus_free_drives(chp); 310 ata_channel_unlock(chp); 311 return; 312 } 313 314 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 315 for (i = 0; i < mstohz(3000); i++) { 316 /* 317 * select drive 1 first, so that master is selected on 318 * exit from the loop 319 */ 320 if (chp->ch_ndrives > 1 && 321 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 322 if (wdc->select) 323 wdc->select(chp,1); 324 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 325 0, WDSD_IBM | 0x10); 326 delay(10); /* 400ns delay */ 327 st1 = bus_space_read_1(wdr->cmd_iot, 328 wdr->cmd_iohs[wd_status], 0); 329 } 330 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 331 if (wdc->select) 332 wdc->select(chp,0); 333 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 334 0, WDSD_IBM); 335 delay(10); /* 400ns delay */ 336 st0 = bus_space_read_1(wdr->cmd_iot, 337 wdr->cmd_iohs[wd_status], 0); 338 } 339 340 341 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 342 (st0 & WDCS_DRDY)) && 343 (chp->ch_ndrives < 2 || 344 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 345 (st1 & WDCS_DRDY))) 346 break; 347 #ifdef WDC_NO_IDS 348 /* cannot kpause here (can't enable IPL_BIO interrupts), 349 * delay instead 350 */ 351 delay(1000000 / hz); 352 #else 353 ata_delay(chp, 1, "atadrdy", AT_WAIT); 354 #endif 355 } 356 if ((st0 & WDCS_DRDY) == 0 && 357 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 358 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 359 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 360 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 361 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 362 ata_channel_unlock(chp); 363 364 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 365 device_xname(atac->atac_dev), 366 chp->ch_channel, st0, st1), DEBUG_PROBE); 367 368 /* Wait a bit, some devices are weird just after a reset. */ 369 delay(5000); 370 371 for (i = 0; i < chp->ch_ndrives; i++) { 372 #if NATA_DMA 373 /* 374 * Init error counter so that an error within the first xfers 375 * will trigger a downgrade 376 */ 377 chp->ch_drive[i].n_dmaerrs = NERRS_MAX - 1; 378 #endif 379 380 switch (atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) { 381 case 0: 382 /* 383 * Controller can only do 8-bit PIO; we will have 384 * to issue a SET_FEATURES to put the drive into 385 * that mode. If it fails, we will ignore the 386 * drive. 387 */ 388 aprint_verbose("%s:%d:%d: setting PIO8_EN\n", 389 device_xname(atac->atac_dev), 390 chp->ch_channel, i); 391 error = ata_set_pio8(&chp->ch_drive[i], 392 AT_WAIT | AT_POLL); 393 if (error != CMD_OK) { 394 aprint_error("%s:%d:%d: failed to set " 395 "8-bit PIO (%d)\n", 396 device_xname(atac->atac_dev), 397 chp->ch_channel, i, error); 398 ata_channel_lock(chp); 399 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 400 ata_channel_unlock(chp); 401 } 402 break; 403 404 case ATAC_CAP_DATA32: 405 /* 406 * If the controller can't do 16-bit, then flag 407 * the drives as 32-bit. 408 */ 409 ata_channel_lock(chp); 410 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 411 ata_channel_unlock(chp); 412 break; 413 414 default: 415 break; 416 } 417 418 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 419 continue; 420 421 /* Shortcut in case we've been shutdown */ 422 if (chp->ch_flags & ATACH_SHUTDOWN) 423 return; 424 425 /* 426 * Issue an identify, to try to detect ghosts. 427 * Note that we can't use interrupts here, because if there 428 * is no devices, we will get a command aborted without 429 * interrupts. 430 */ 431 error = ata_get_params(&chp->ch_drive[i], 432 AT_WAIT | AT_POLL, ¶ms); 433 if (error != CMD_OK) { 434 ata_channel_lock(chp); 435 ata_delay(chp, 1000, "atacnf", AT_WAIT); 436 ata_channel_unlock(chp); 437 438 /* Shortcut in case we've been shutdown */ 439 if (chp->ch_flags & ATACH_SHUTDOWN) 440 return; 441 442 error = ata_get_params(&chp->ch_drive[i], 443 AT_WAIT | AT_POLL, ¶ms); 444 } 445 if (error != CMD_OK) { 446 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 447 device_xname(atac->atac_dev), 448 chp->ch_channel, i, error), DEBUG_PROBE); 449 ata_channel_lock(chp); 450 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 451 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 452 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 453 ata_channel_unlock(chp); 454 continue; 455 } 456 /* 457 * Pre-ATA drive ? 458 * Test registers writability (Error register not 459 * writable, but cyllo is), then try an ATA command. 460 */ 461 if (wdc->select) 462 wdc->select(chp,i); 463 bus_space_write_1(wdr->cmd_iot, 464 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 465 delay(10); /* 400ns delay */ 466 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 467 0, 0x58); 468 bus_space_write_1(wdr->cmd_iot, 469 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 470 if (bus_space_read_1(wdr->cmd_iot, 471 wdr->cmd_iohs[wd_error], 0) == 0x58 || 472 bus_space_read_1(wdr->cmd_iot, 473 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 474 ATADEBUG_PRINT(("%s:%d:%d: register " 475 "writability failed\n", 476 device_xname(atac->atac_dev), 477 chp->ch_channel, i), DEBUG_PROBE); 478 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 479 ata_channel_unlock(chp); 480 continue; 481 } 482 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 483 WDCWAIT_TOUT) { 484 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 485 device_xname(atac->atac_dev), 486 chp->ch_channel, i), DEBUG_PROBE); 487 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 488 ata_channel_unlock(chp); 489 continue; 490 } 491 bus_space_write_1(wdr->cmd_iot, 492 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 493 delay(10); /* 400ns delay */ 494 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 495 WDCWAIT_TOUT) { 496 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 497 device_xname(atac->atac_dev), 498 chp->ch_channel, i), DEBUG_PROBE); 499 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 500 ata_channel_unlock(chp); 501 continue; 502 } 503 chp->ch_drive[i].drive_type = ATA_DRIVET_OLD; 504 ata_channel_unlock(chp); 505 } 506 } 507 } 508 509 int 510 wdcprobe(struct wdc_regs *wdr) 511 { 512 513 return wdcprobe_with_reset(wdr, NULL); 514 } 515 516 int 517 wdcprobe_with_reset(struct wdc_regs *wdr, 518 void (*do_reset)(struct ata_channel *, int)) 519 { 520 struct wdc_softc *wdc; 521 struct ata_channel *ch; 522 int rv; 523 524 wdc = kmem_zalloc(sizeof(*wdc), KM_SLEEP); 525 ch = kmem_zalloc(sizeof(*ch), KM_SLEEP); 526 527 ata_channel_init(ch); 528 ch->ch_atac = &wdc->sc_atac; 529 wdc->regs = wdr; 530 531 /* check the MD reset method */ 532 wdc->reset = (do_reset != NULL) ? do_reset : wdc_do_reset; 533 534 ata_channel_lock(ch); 535 rv = wdcprobe1(ch, 1); 536 ata_channel_unlock(ch); 537 538 ata_channel_destroy(ch); 539 540 kmem_free(ch, sizeof(*ch)); 541 kmem_free(wdc, sizeof(*wdc)); 542 543 return rv; 544 } 545 546 static int 547 wdcprobe1(struct ata_channel *chp, int poll) 548 { 549 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 550 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 551 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 552 u_int8_t ret_value = 0x03; 553 u_int8_t drive; 554 /* XXX if poll, wdc_probe_count is 0. */ 555 int wdc_probe_count = 556 poll ? (WDC_PROBE_WAIT / WDCDELAY) 557 : (WDC_PROBE_WAIT * hz); 558 559 /* 560 * Sanity check to see if the wdc channel responds at all. 561 */ 562 563 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 564 while (wdc_probe_count-- > 0) { 565 if (wdc->select) 566 wdc->select(chp,0); 567 568 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 569 0, WDSD_IBM); 570 delay(10); /* 400ns delay */ 571 st0 = bus_space_read_1(wdr->cmd_iot, 572 wdr->cmd_iohs[wd_status], 0); 573 574 if (wdc->select) 575 wdc->select(chp,1); 576 577 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 578 0, WDSD_IBM | 0x10); 579 delay(10); /* 400ns delay */ 580 st1 = bus_space_read_1(wdr->cmd_iot, 581 wdr->cmd_iohs[wd_status], 0); 582 if ((st0 & WDCS_BSY) == 0) 583 break; 584 } 585 586 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 587 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 588 589 /* 590 * Is a drive present? Originally this code tested either 591 * for 0xff (ISA controller with no drive present; pull-ups 592 * take reg values high) or "echo", which meant writing to 593 * the notionally read-only geometry regs and seeing if we 594 * could read back what we wrote (if a drive is there, we 595 * will not). But some PCI controllers don't have the 596 * 0xff behavior and also share regs internally in a way 597 * that tricks the echo test, resulting in a 3 second delay 598 * later before we find no drive. We conditionally check for 599 * 0x00 which should catch this case because a drive that's 600 * actually present should have at least BSY or DRDY set. 601 */ 602 if (st0 == 0xff || st0 == WDSD_IBM) 603 ret_value &= ~0x01; 604 else if (st0 == 0x00 && 605 (wdc->cap & WDC_CAPABILITY_ZERO_ABSENT)) 606 ret_value &= ~0x01; 607 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 608 ret_value &= ~0x02; 609 else if (st0 == 0x00 && 610 (wdc->cap & WDC_CAPABILITY_ZERO_ABSENT)) 611 ret_value &= ~0x02; 612 /* Register writability test, drive 0. */ 613 if (ret_value & 0x01) { 614 if (wdc->select) 615 wdc->select(chp,0); 616 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 617 0, WDSD_IBM); 618 bus_space_write_1(wdr->cmd_iot, 619 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 620 cl = bus_space_read_1(wdr->cmd_iot, 621 wdr->cmd_iohs[wd_cyl_lo], 0); 622 if (cl != 0x02) { 623 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 624 "got 0x%x != 0x02\n", 625 __func__, chp->ch_channel, cl), 626 DEBUG_PROBE); 627 ret_value &= ~0x01; 628 } 629 bus_space_write_1(wdr->cmd_iot, 630 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 631 cl = bus_space_read_1(wdr->cmd_iot, 632 wdr->cmd_iohs[wd_cyl_lo], 0); 633 if (cl != 0x01) { 634 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 635 "got 0x%x != 0x01\n", 636 __func__, chp->ch_channel, cl), 637 DEBUG_PROBE); 638 ret_value &= ~0x01; 639 } 640 bus_space_write_1(wdr->cmd_iot, 641 wdr->cmd_iohs[wd_sector], 0, 0x01); 642 cl = bus_space_read_1(wdr->cmd_iot, 643 wdr->cmd_iohs[wd_sector], 0); 644 if (cl != 0x01) { 645 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 646 "got 0x%x != 0x01\n", 647 __func__, chp->ch_channel, cl), 648 DEBUG_PROBE); 649 ret_value &= ~0x01; 650 } 651 bus_space_write_1(wdr->cmd_iot, 652 wdr->cmd_iohs[wd_sector], 0, 0x02); 653 cl = bus_space_read_1(wdr->cmd_iot, 654 wdr->cmd_iohs[wd_sector], 0); 655 if (cl != 0x02) { 656 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 657 "got 0x%x != 0x02\n", 658 __func__, chp->ch_channel, cl), 659 DEBUG_PROBE); 660 ret_value &= ~0x01; 661 } 662 cl = bus_space_read_1(wdr->cmd_iot, 663 wdr->cmd_iohs[wd_cyl_lo], 0); 664 if (cl != 0x01) { 665 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 666 "got 0x%x != 0x01\n", 667 __func__, chp->ch_channel, cl), 668 DEBUG_PROBE); 669 ret_value &= ~0x01; 670 } 671 } 672 /* Register writability test, drive 1. */ 673 if (ret_value & 0x02) { 674 if (wdc->select) 675 wdc->select(chp,1); 676 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 677 0, WDSD_IBM | 0x10); 678 bus_space_write_1(wdr->cmd_iot, 679 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 680 cl = bus_space_read_1(wdr->cmd_iot, 681 wdr->cmd_iohs[wd_cyl_lo], 0); 682 if (cl != 0x02) { 683 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 684 "got 0x%x != 0x02\n", 685 __func__, chp->ch_channel, cl), 686 DEBUG_PROBE); 687 ret_value &= ~0x02; 688 } 689 bus_space_write_1(wdr->cmd_iot, 690 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 691 cl = bus_space_read_1(wdr->cmd_iot, 692 wdr->cmd_iohs[wd_cyl_lo], 0); 693 if (cl != 0x01) { 694 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 695 "got 0x%x != 0x01\n", 696 __func__, chp->ch_channel, cl), 697 DEBUG_PROBE); 698 ret_value &= ~0x02; 699 } 700 bus_space_write_1(wdr->cmd_iot, 701 wdr->cmd_iohs[wd_sector], 0, 0x01); 702 cl = bus_space_read_1(wdr->cmd_iot, 703 wdr->cmd_iohs[wd_sector], 0); 704 if (cl != 0x01) { 705 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 706 "got 0x%x != 0x01\n", 707 __func__, chp->ch_channel, cl), 708 DEBUG_PROBE); 709 ret_value &= ~0x02; 710 } 711 bus_space_write_1(wdr->cmd_iot, 712 wdr->cmd_iohs[wd_sector], 0, 0x02); 713 cl = bus_space_read_1(wdr->cmd_iot, 714 wdr->cmd_iohs[wd_sector], 0); 715 if (cl != 0x02) { 716 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 717 "got 0x%x != 0x02\n", 718 __func__, chp->ch_channel, cl), 719 DEBUG_PROBE); 720 ret_value &= ~0x02; 721 } 722 cl = bus_space_read_1(wdr->cmd_iot, 723 wdr->cmd_iohs[wd_cyl_lo], 0); 724 if (cl != 0x01) { 725 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 726 "got 0x%x != 0x01\n", 727 __func__, chp->ch_channel, cl), 728 DEBUG_PROBE); 729 ret_value &= ~0x02; 730 } 731 } 732 733 if (ret_value == 0) { 734 return 0; 735 } 736 } 737 738 #if 0 /* XXX this break some ATA or ATAPI devices */ 739 /* 740 * reset bus. Also send an ATAPI_RESET to devices, in case there are 741 * ATAPI device out there which don't react to the bus reset 742 */ 743 if (ret_value & 0x01) { 744 if (wdc->select) 745 wdc->select(chp,0); 746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 747 0, WDSD_IBM); 748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 749 ATAPI_SOFT_RESET); 750 } 751 if (ret_value & 0x02) { 752 if (wdc->select) 753 wdc->select(chp,0); 754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 755 0, WDSD_IBM | 0x10); 756 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 757 ATAPI_SOFT_RESET); 758 } 759 760 delay(5000); 761 #endif 762 763 wdc->reset(chp, RESET_POLL); 764 DELAY(2000); 765 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 766 767 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 768 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 769 WDCTL_4BIT); 770 771 #ifdef WDC_NO_IDS 772 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 773 #else 774 ret_value = __wdcwait_reset(chp, ret_value, poll); 775 #endif 776 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 777 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 778 779 /* if reset failed, there's nothing here */ 780 if (ret_value == 0) { 781 return 0; 782 } 783 784 /* 785 * Test presence of drives. First test register signatures looking 786 * for ATAPI devices. If it's not an ATAPI and reset said there may 787 * be something here assume it's ATA or OLD. Ghost will be killed 788 * later in attach routine. 789 */ 790 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 791 if ((ret_value & (0x01 << drive)) == 0) 792 continue; 793 if (wdc->select) 794 wdc->select(chp,drive); 795 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 796 WDSD_IBM | (drive << 4)); 797 delay(10); /* 400ns delay */ 798 /* Save registers contents */ 799 sc = bus_space_read_1(wdr->cmd_iot, 800 wdr->cmd_iohs[wd_seccnt], 0); 801 sn = bus_space_read_1(wdr->cmd_iot, 802 wdr->cmd_iohs[wd_sector], 0); 803 cl = bus_space_read_1(wdr->cmd_iot, 804 wdr->cmd_iohs[wd_cyl_lo], 0); 805 ch = bus_space_read_1(wdr->cmd_iot, 806 wdr->cmd_iohs[wd_cyl_hi], 0); 807 808 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 809 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 810 sn, cl, ch), DEBUG_PROBE); 811 /* 812 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 813 * we get wrong values here, so ignore it. 814 */ 815 if (chp->ch_drive != NULL) { 816 if (cl == 0x14 && ch == 0xeb) { 817 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 818 } else { 819 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 820 } 821 } 822 } 823 /* 824 * Select an existing drive before lowering spl, some WDC_NO_IDS 825 * devices incorrectly assert IRQ on nonexistent slave 826 */ 827 if (ret_value & 0x01) { 828 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 829 WDSD_IBM); 830 (void)bus_space_read_1(wdr->cmd_iot, 831 wdr->cmd_iohs[wd_status], 0); 832 } 833 return (ret_value); 834 } 835 836 void 837 wdcattach(struct ata_channel *chp) 838 { 839 struct atac_softc *atac = chp->ch_atac; 840 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 841 842 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 843 844 /* default data transfer methods */ 845 if (wdc->datain_pio == NULL) 846 wdc->datain_pio = wdc_datain_pio; 847 if (wdc->dataout_pio == NULL) 848 wdc->dataout_pio = wdc_dataout_pio; 849 /* default reset method */ 850 if (wdc->reset == NULL) 851 wdc->reset = wdc_do_reset; 852 853 /* initialise global data */ 854 if (atac->atac_bustype_ata == NULL) 855 atac->atac_bustype_ata = &wdc_ata_bustype; 856 if (atac->atac_probe == NULL) 857 atac->atac_probe = wdc_drvprobe; 858 #if NATAPIBUS > 0 859 if (atac->atac_atapibus_attach == NULL) 860 atac->atac_atapibus_attach = wdc_atapibus_attach; 861 #endif 862 863 ata_channel_attach(chp); 864 } 865 866 void 867 wdc_childdetached(device_t self, device_t child) 868 { 869 struct atac_softc *atac = device_private(self); 870 struct ata_channel *chp; 871 int i; 872 873 for (i = 0; i < atac->atac_nchannels; i++) { 874 chp = atac->atac_channels[i]; 875 if (child == chp->atabus) { 876 chp->atabus = NULL; 877 return; 878 } 879 } 880 } 881 882 int 883 wdcdetach(device_t self, int flags) 884 { 885 struct atac_softc *atac = device_private(self); 886 struct ata_channel *chp; 887 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 888 int i, error = 0; 889 890 for (i = 0; i < atac->atac_nchannels; i++) { 891 chp = atac->atac_channels[i]; 892 if (chp->atabus == NULL) 893 continue; 894 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 895 device_xname(atac->atac_dev), device_xname(chp->atabus)), 896 DEBUG_DETACH); 897 if ((error = config_detach(chp->atabus, flags)) != 0) 898 return error; 899 ata_channel_detach(chp); 900 } 901 if (adapt->adapt_refcnt != 0) 902 return EBUSY; 903 return 0; 904 } 905 906 /* restart an interrupted I/O */ 907 void 908 wdcrestart(void *v) 909 { 910 struct ata_channel *chp = v; 911 int s; 912 913 s = splbio(); 914 atastart(chp); 915 splx(s); 916 } 917 918 919 /* 920 * Interrupt routine for the controller. Acknowledge the interrupt, check for 921 * errors on the current operation, mark it done if necessary, and start the 922 * next request. Also check for a partially done transfer, and continue with 923 * the next chunk if so. 924 */ 925 int 926 wdcintr(void *arg) 927 { 928 struct ata_channel *chp = arg; 929 struct atac_softc *atac = chp->ch_atac; 930 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 931 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 932 struct ata_xfer *xfer; 933 int ret; 934 935 if (!device_is_active(atac->atac_dev)) { 936 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 937 DEBUG_INTR); 938 return (0); 939 } 940 941 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) 942 goto ignore; 943 944 xfer = ata_queue_get_active_xfer(chp); 945 if (xfer == NULL) { 946 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 947 ignore: 948 /* try to clear the pending interrupt anyway */ 949 (void)bus_space_read_1(wdr->cmd_iot, 950 wdr->cmd_iohs[wd_status], 0); 951 return (0); 952 } 953 954 /* 955 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 956 * actually has no effect, and interrupt is triggered regardless. 957 * Ignore polled commands here, they are processed separately. 958 */ 959 if (ISSET(xfer->c_flags, C_POLL)) { 960 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 961 DEBUG_INTR); 962 goto ignore; 963 } 964 965 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 966 KASSERT(xfer != NULL); 967 968 #if NATA_DMA || NATA_PIOBM 969 if (chp->ch_flags & ATACH_DMA_WAIT) { 970 wdc->dma_status = 971 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 972 xfer->c_drive, WDC_DMAEND_END); 973 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 974 /* IRQ not for us, not detected by DMA engine */ 975 return 0; 976 } 977 chp->ch_flags &= ~ATACH_DMA_WAIT; 978 } 979 #endif 980 chp->ch_flags &= ~ATACH_IRQ_WAIT; 981 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 982 ret = xfer->ops->c_intr(chp, xfer, 1); 983 if (ret == 0) /* irq was not for us, still waiting for irq */ 984 chp->ch_flags |= ATACH_IRQ_WAIT; 985 return (ret); 986 } 987 988 /* Put all disk in RESET state */ 989 void 990 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 991 { 992 struct ata_channel *chp = drvp->chnl_softc; 993 994 ata_channel_lock_owned(chp); 995 996 KASSERT(sigp == NULL); 997 998 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 999 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1000 drvp->drive), DEBUG_FUNCS); 1001 1002 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 1003 } 1004 1005 void 1006 wdc_reset_channel(struct ata_channel *chp, int flags) 1007 { 1008 struct ata_xfer *xfer; 1009 1010 ata_channel_lock_owned(chp); 1011 1012 #if NATA_DMA || NATA_PIOBM 1013 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1014 #endif 1015 1016 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1017 1018 /* 1019 * if the current command is on an ATAPI device, issue a 1020 * ATAPI_SOFT_RESET 1021 */ 1022 xfer = ata_queue_get_active_xfer_locked(chp); 1023 1024 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 1025 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 1026 ata_delay(chp, 1000, "atardl", flags); 1027 } 1028 1029 /* reset the channel */ 1030 if (flags & AT_WAIT) 1031 (void) wdcreset(chp, RESET_SLEEP); 1032 else 1033 (void) wdcreset(chp, RESET_POLL); 1034 1035 /* 1036 * wait a bit after reset; in case the DMA engines needs some time 1037 * to recover. 1038 */ 1039 ata_delay(chp, 1000, "atardl", flags); 1040 1041 /* 1042 * Look for pending xfers. If we have a shared queue, we'll also reset 1043 * the other channel if the current xfer is running on it. 1044 * Then we'll kill the eventual active transfer explicitly, so that 1045 * it is queued for retry immediately without waiting for I/O timeout. 1046 */ 1047 if (xfer) { 1048 if (xfer->c_chp != chp) { 1049 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 1050 ATACH_NODRIVE); 1051 } else { 1052 #if NATA_DMA || NATA_PIOBM 1053 /* 1054 * If we're waiting for DMA, stop the 1055 * DMA engine 1056 */ 1057 if (chp->ch_flags & ATACH_DMA_WAIT) { 1058 (*wdc->dma_finish)(wdc->dma_arg, 1059 chp->ch_channel, xfer->c_drive, 1060 WDC_DMAEND_ABRT_QUIET); 1061 chp->ch_flags &= ~ATACH_DMA_WAIT; 1062 } 1063 #endif 1064 } 1065 } 1066 1067 ata_kill_active(chp, KILL_RESET, flags); 1068 } 1069 1070 static int 1071 wdcreset(struct ata_channel *chp, int poll) 1072 { 1073 struct atac_softc *atac = chp->ch_atac; 1074 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1075 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1076 int drv_mask1 = 0, drv_mask2; 1077 1078 ata_channel_lock_owned(chp); 1079 1080 #ifdef WDC_NO_IDS 1081 poll = RESET_POLL; 1082 #endif 1083 wdc->reset(chp, poll); 1084 1085 if (chp->ch_ndrives > 0) 1086 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1087 ? 0x01 : 0x00; 1088 if (chp->ch_ndrives > 1) 1089 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1090 ? 0x02 : 0x00; 1091 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1092 (poll == RESET_SLEEP) ? 0 : 1); 1093 if (drv_mask2 != drv_mask1) { 1094 aprint_error("%s channel %d: reset failed for", 1095 device_xname(atac->atac_dev), chp->ch_channel); 1096 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1097 aprint_normal(" drive 0"); 1098 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1099 aprint_normal(" drive 1"); 1100 aprint_normal("\n"); 1101 } 1102 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1103 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1104 WDCTL_4BIT); 1105 1106 return (drv_mask1 != drv_mask2) ? 1 : 0; 1107 } 1108 1109 void 1110 wdc_do_reset(struct ata_channel *chp, int poll) 1111 { 1112 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1113 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1114 int s = 0; 1115 1116 if (poll != RESET_SLEEP) 1117 s = splbio(); 1118 if (wdc->select) 1119 wdc->select(chp,0); 1120 /* master */ 1121 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1122 delay(10); /* 400ns delay */ 1123 /* assert SRST, wait for reset to complete */ 1124 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1125 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1126 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1127 delay(2000); 1128 } 1129 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1130 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1131 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1132 WDCTL_4BIT | WDCTL_IDS); 1133 delay(10); /* 400ns delay */ 1134 if (poll != RESET_SLEEP) { 1135 /* ACK interrupt in case there is one pending left */ 1136 if (wdc->irqack) 1137 wdc->irqack(chp); 1138 splx(s); 1139 } 1140 } 1141 1142 static int 1143 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1144 { 1145 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1146 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1147 int timeout, nloop; 1148 int wflags = poll ? AT_POLL : AT_WAIT; 1149 u_int8_t st0 = 0, st1 = 0; 1150 #ifdef ATADEBUG 1151 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1152 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1153 #endif 1154 if (poll) 1155 nloop = WDCNDELAY_RST; 1156 else 1157 nloop = WDC_RESET_WAIT * hz / 1000; 1158 /* wait for BSY to deassert */ 1159 for (timeout = 0; timeout < nloop; timeout++) { 1160 if ((drv_mask & 0x01) != 0) { 1161 if (wdc->select) 1162 wdc->select(chp,0); 1163 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1164 0, WDSD_IBM); /* master */ 1165 delay(10); 1166 st0 = bus_space_read_1(wdr->cmd_iot, 1167 wdr->cmd_iohs[wd_status], 0); 1168 #ifdef ATADEBUG 1169 sc0 = bus_space_read_1(wdr->cmd_iot, 1170 wdr->cmd_iohs[wd_seccnt], 0); 1171 sn0 = bus_space_read_1(wdr->cmd_iot, 1172 wdr->cmd_iohs[wd_sector], 0); 1173 cl0 = bus_space_read_1(wdr->cmd_iot, 1174 wdr->cmd_iohs[wd_cyl_lo], 0); 1175 ch0 = bus_space_read_1(wdr->cmd_iot, 1176 wdr->cmd_iohs[wd_cyl_hi], 0); 1177 #endif 1178 } 1179 if ((drv_mask & 0x02) != 0) { 1180 if (wdc->select) 1181 wdc->select(chp,1); 1182 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1183 0, WDSD_IBM | 0x10); /* slave */ 1184 delay(10); 1185 st1 = bus_space_read_1(wdr->cmd_iot, 1186 wdr->cmd_iohs[wd_status], 0); 1187 #ifdef ATADEBUG 1188 sc1 = bus_space_read_1(wdr->cmd_iot, 1189 wdr->cmd_iohs[wd_seccnt], 0); 1190 sn1 = bus_space_read_1(wdr->cmd_iot, 1191 wdr->cmd_iohs[wd_sector], 0); 1192 cl1 = bus_space_read_1(wdr->cmd_iot, 1193 wdr->cmd_iohs[wd_cyl_lo], 0); 1194 ch1 = bus_space_read_1(wdr->cmd_iot, 1195 wdr->cmd_iohs[wd_cyl_hi], 0); 1196 #endif 1197 } 1198 1199 if ((drv_mask & 0x01) == 0) { 1200 /* no master */ 1201 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1202 /* No master, slave is ready, it's done */ 1203 goto end; 1204 } 1205 if ((drv_mask & 0x02) == 0) { 1206 /* No master, no slave: it's done */ 1207 goto end; 1208 } 1209 } else if ((drv_mask & 0x02) == 0) { 1210 /* no slave */ 1211 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1212 /* No slave, master is ready, it's done */ 1213 goto end; 1214 } 1215 } else { 1216 /* Wait for both master and slave to be ready */ 1217 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1218 goto end; 1219 } 1220 } 1221 ata_delay(chp, WDCDELAY, "atarst", wflags); 1222 } 1223 /* Reset timed out. Maybe it's because drv_mask was not right */ 1224 if (st0 & WDCS_BSY) 1225 drv_mask &= ~0x01; 1226 if (st1 & WDCS_BSY) 1227 drv_mask &= ~0x02; 1228 end: 1229 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1230 "cl=0x%x ch=0x%x\n", 1231 device_xname(chp->ch_atac->atac_dev), 1232 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1233 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1234 "cl=0x%x ch=0x%x\n", 1235 device_xname(chp->ch_atac->atac_dev), 1236 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1237 1238 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1239 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1240 st0, st1), DEBUG_PROBE); 1241 1242 return drv_mask; 1243 } 1244 1245 /* 1246 * Wait for a drive to be !BSY, and have mask in its status register. 1247 * return -1 for a timeout after "timeout" ms. 1248 */ 1249 static int 1250 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1251 { 1252 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1253 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1254 u_char status, error = 0; 1255 int xtime = 0; 1256 int rv; 1257 1258 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1259 device_xname(chp->ch_atac->atac_dev), 1260 chp->ch_channel), DEBUG_STATUS); 1261 *tfd = 0; 1262 1263 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1264 1265 for (;;) { 1266 status = 1267 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1268 if ((status & (WDCS_BSY | mask)) == bits) 1269 break; 1270 if (++xtime > timeout) { 1271 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1272 "status %x error %x (mask 0x%x bits 0x%x)\n", 1273 xtime, status, 1274 bus_space_read_1(wdr->cmd_iot, 1275 wdr->cmd_iohs[wd_error], 0), mask, bits), 1276 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1277 rv = WDCWAIT_TOUT; 1278 goto out; 1279 } 1280 delay(WDCDELAY); 1281 } 1282 #ifdef ATADEBUG 1283 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1284 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1285 #endif 1286 if (status & WDCS_ERR) 1287 error = bus_space_read_1(wdr->cmd_iot, 1288 wdr->cmd_iohs[wd_error], 0); 1289 #ifdef WDCNDELAY_DEBUG 1290 /* After autoconfig, there should be no long delays. */ 1291 if (!cold && xtime > WDCNDELAY_DEBUG) { 1292 struct ata_xfer *xfer; 1293 1294 xfer = ata_queue_get_active_xfer_locked(chp); 1295 if (xfer == NULL) 1296 printf("%s channel %d: warning: busy-wait took %dus\n", 1297 device_xname(chp->ch_atac->atac_dev), 1298 chp->ch_channel, WDCDELAY * xtime); 1299 else 1300 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1301 device_xname(chp->ch_atac->atac_dev), 1302 chp->ch_channel, xfer->c_drive, 1303 WDCDELAY * xtime); 1304 } 1305 #endif 1306 rv = WDCWAIT_OK; 1307 1308 out: 1309 *tfd = ATACH_ERR_ST(error, status); 1310 return rv; 1311 } 1312 1313 /* 1314 * Call __wdcwait(), polling using kpause() or waking up the kernel 1315 * thread if possible 1316 */ 1317 int 1318 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1319 int *tfd) 1320 { 1321 int error, i, timeout_hz = mstohz(timeout); 1322 1323 ata_channel_lock_owned(chp); 1324 1325 if (timeout_hz == 0 || 1326 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1327 error = __wdcwait(chp, mask, bits, timeout, tfd); 1328 else { 1329 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1330 if (error != 0) { 1331 if (ata_is_thread_run(chp) || (flags & AT_WAIT)) { 1332 /* 1333 * we're running in the channel thread 1334 * or some userland thread context 1335 */ 1336 for (i = 0; i < timeout_hz; i++) { 1337 if (__wdcwait(chp, mask, bits, 1338 WDCDELAY_POLL, tfd) == 0) { 1339 error = 0; 1340 break; 1341 } 1342 kpause("atapoll", true, 1, 1343 &chp->ch_lock); 1344 } 1345 } else { 1346 /* 1347 * we're probably in interrupt context, 1348 * caller must ask the thread to come back here 1349 */ 1350 return(WDCWAIT_THR); 1351 } 1352 } 1353 } 1354 return (error); 1355 } 1356 1357 1358 #if NATA_DMA 1359 /* 1360 * Busy-wait for DMA to complete 1361 */ 1362 int 1363 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1364 { 1365 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1366 int xtime; 1367 1368 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1369 wdc->dma_status = 1370 (*wdc->dma_finish)(wdc->dma_arg, 1371 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1372 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1373 return 0; 1374 delay(WDCDELAY); 1375 } 1376 /* timeout, force a DMA halt */ 1377 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1378 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1379 return 1; 1380 } 1381 #endif 1382 1383 void 1384 wdctimeout(void *arg) 1385 { 1386 struct ata_xfer *xfer; 1387 struct ata_channel *chp = arg; 1388 #if NATA_DMA || NATA_PIOBM 1389 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1390 #endif 1391 int s; 1392 1393 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1394 1395 s = splbio(); 1396 1397 callout_ack(&chp->c_timo_callout); 1398 1399 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 1400 __wdcerror(chp, "timeout not expected without pending irq"); 1401 goto out; 1402 } 1403 1404 xfer = ata_queue_get_active_xfer(chp); 1405 KASSERT(xfer != NULL); 1406 1407 if (ata_timo_xfer_check(xfer)) { 1408 /* Already logged */ 1409 goto out; 1410 } 1411 1412 __wdcerror(chp, "lost interrupt"); 1413 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1414 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1415 xfer->c_bcount, xfer->c_skip); 1416 #if NATA_DMA || NATA_PIOBM 1417 if (chp->ch_flags & ATACH_DMA_WAIT) { 1418 wdc->dma_status = 1419 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1420 xfer->c_drive, WDC_DMAEND_ABRT); 1421 chp->ch_flags &= ~ATACH_DMA_WAIT; 1422 } 1423 #endif 1424 /* 1425 * Call the interrupt routine. If we just missed an interrupt, 1426 * it will do what's needed. Else, it will take the needed 1427 * action (reset the device). 1428 */ 1429 xfer->c_flags |= C_TIMEOU; 1430 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1431 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1432 xfer->ops->c_intr(chp, xfer, 1); 1433 1434 out: 1435 splx(s); 1436 } 1437 1438 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1439 .c_start = __wdccommand_start, 1440 .c_poll = __wdccommand_poll, 1441 .c_abort = __wdccommand_done, 1442 .c_intr = __wdccommand_intr, 1443 .c_kill_xfer = __wdccommand_kill_xfer, 1444 }; 1445 1446 void 1447 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1448 { 1449 struct ata_channel *chp = drvp->chnl_softc; 1450 struct ata_command *ata_c = &xfer->c_ata_c; 1451 1452 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1453 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1454 drvp->drive), DEBUG_FUNCS); 1455 1456 /* set up an xfer and queue. Wait for completion */ 1457 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1458 ata_c->flags |= AT_POLL; 1459 if (ata_c->flags & AT_POLL) 1460 xfer->c_flags |= C_POLL; 1461 if (ata_c->flags & AT_WAIT) 1462 xfer->c_flags |= C_WAIT; 1463 xfer->c_drive = drvp->drive; 1464 xfer->c_databuf = ata_c->data; 1465 xfer->c_bcount = ata_c->bcount; 1466 xfer->ops = &wdc_cmd_xfer_ops; 1467 1468 ata_exec_xfer(chp, xfer); 1469 } 1470 1471 static int 1472 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1473 { 1474 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1475 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1476 int drive = xfer->c_drive; 1477 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1478 struct ata_command *ata_c = &xfer->c_ata_c; 1479 int tfd; 1480 1481 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1482 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1483 xfer->c_drive), DEBUG_FUNCS); 1484 1485 if (wdc->select) 1486 wdc->select(chp,drive); 1487 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1488 WDSD_IBM | (drive << 4)); 1489 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1490 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1491 case WDCWAIT_OK: 1492 break; 1493 case WDCWAIT_TOUT: 1494 ata_c->flags |= AT_TIMEOU; 1495 return ATASTART_ABORT; 1496 case WDCWAIT_THR: 1497 return ATASTART_TH; 1498 } 1499 if (ata_c->flags & AT_POLL) { 1500 /* polled command, disable interrupts */ 1501 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1502 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1503 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1504 } 1505 if ((ata_c->flags & AT_LBA48) != 0) { 1506 wdccommandext(chp, drive, ata_c->r_command, 1507 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1508 ata_c->r_device & ~0x10); 1509 } else { 1510 wdccommand(chp, drive, ata_c->r_command, 1511 (ata_c->r_lba >> 8) & 0xffff, 1512 WDSD_IBM | (drive << 4) | 1513 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1514 ((ata_c->r_lba >> 24) & 0x0f), 1515 ata_c->r_lba & 0xff, 1516 ata_c->r_count & 0xff, 1517 ata_c->r_features & 0xff); 1518 } 1519 1520 if ((ata_c->flags & AT_POLL) == 0) { 1521 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1522 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1523 wdctimeout, chp); 1524 return ATASTART_STARTED; 1525 } 1526 1527 /* 1528 * Polled command. Wait for drive ready or drq. Done in intr(). 1529 * Wait for at last 400ns for status bit to be valid. 1530 */ 1531 delay(10); /* 400ns delay */ 1532 return ATASTART_POLL; 1533 } 1534 1535 static int 1536 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1537 { 1538 __wdccommand_intr(chp, xfer, 0); 1539 return ATAPOLL_DONE; 1540 } 1541 1542 static int 1543 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1544 { 1545 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1546 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1547 struct ata_command *ata_c = &xfer->c_ata_c; 1548 int bcount = ata_c->bcount; 1549 char *data = ata_c->data; 1550 int wflags, tfd; 1551 int drive_flags; 1552 1553 if (ata_c->r_command == WDCC_IDENTIFY || 1554 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1555 /* 1556 * The IDENTIFY data has been designed as an array of 1557 * u_int16_t, so we can byteswap it on the fly. 1558 * Historically it's what we have always done so keeping it 1559 * here ensure binary backward compatibility. 1560 */ 1561 drive_flags = ATA_DRIVE_NOSTREAM | 1562 chp->ch_drive[xfer->c_drive].drive_flags; 1563 } else { 1564 /* 1565 * Other data structure are opaque and should be transferred 1566 * as is. 1567 */ 1568 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1569 } 1570 1571 #ifdef WDC_NO_IDS 1572 wflags = AT_POLL; 1573 #else 1574 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1575 /* both wait and poll, we can kpause here */ 1576 wflags = AT_WAIT | AT_POLL; 1577 } else { 1578 wflags = AT_POLL; 1579 } 1580 #endif 1581 1582 ata_channel_lock(chp); 1583 1584 again: 1585 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1586 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1587 xfer->c_drive), DEBUG_INTR); 1588 /* 1589 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1590 * Reselect again, it doesn't hurt for others commands, and the time 1591 * penalty for the extra register write is acceptable, 1592 * wdc_exec_command() isn't called often (mostly for autoconfig) 1593 */ 1594 if ((xfer->c_flags & C_ATAPI) != 0) { 1595 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1596 WDSD_IBM | (xfer->c_drive << 4)); 1597 } 1598 if ((ata_c->flags & AT_XFDONE) != 0) { 1599 /* 1600 * We have completed a data xfer. The drive should now be 1601 * in its initial state 1602 */ 1603 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1604 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1605 wflags, &tfd) == WDCWAIT_TOUT) { 1606 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1607 ata_channel_unlock(chp); 1608 return 0; /* IRQ was not for us */ 1609 } 1610 ata_c->flags |= AT_TIMEOU; 1611 } 1612 goto out; 1613 } 1614 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1615 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1616 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1617 ata_channel_unlock(chp); 1618 return 0; /* IRQ was not for us */ 1619 } 1620 ata_c->flags |= AT_TIMEOU; 1621 goto out; 1622 } 1623 if (wdc->irqack) 1624 wdc->irqack(chp); 1625 if (ata_c->flags & AT_READ) { 1626 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1627 ata_c->flags |= AT_TIMEOU; 1628 goto out; 1629 } 1630 wdc->datain_pio(chp, drive_flags, data, bcount); 1631 /* at this point the drive should be in its initial state */ 1632 ata_c->flags |= AT_XFDONE; 1633 /* 1634 * XXX checking the status register again here cause some 1635 * hardware to timeout. 1636 */ 1637 } else if (ata_c->flags & AT_WRITE) { 1638 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1639 ata_c->flags |= AT_TIMEOU; 1640 goto out; 1641 } 1642 wdc->dataout_pio(chp, drive_flags, data, bcount); 1643 ata_c->flags |= AT_XFDONE; 1644 if ((ata_c->flags & AT_POLL) == 0) { 1645 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1646 callout_reset(&chp->c_timo_callout, 1647 mstohz(ata_c->timeout), wdctimeout, chp); 1648 ata_channel_unlock(chp); 1649 return 1; 1650 } else { 1651 goto again; 1652 } 1653 } 1654 out: 1655 if (ATACH_ST(tfd) & WDCS_DWF) 1656 ata_c->flags |= AT_DF; 1657 if (ATACH_ST(tfd) & WDCS_ERR) { 1658 ata_c->flags |= AT_ERROR; 1659 ata_c->r_error = ATACH_ST(tfd); 1660 } 1661 1662 ata_channel_unlock(chp); 1663 1664 __wdccommand_done(chp, xfer); 1665 return 1; 1666 } 1667 1668 static void 1669 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1670 { 1671 struct atac_softc *atac = chp->ch_atac; 1672 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1673 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1674 struct ata_command *ata_c = &xfer->c_ata_c; 1675 bool start = true; 1676 1677 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1678 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1679 ata_c->flags), DEBUG_FUNCS); 1680 1681 if (ata_waitdrain_xfer_check(chp, xfer)) { 1682 start = false; 1683 goto out; 1684 } 1685 1686 if ((ata_c->flags & AT_READREG) != 0 && 1687 device_is_active(atac->atac_dev) && 1688 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1689 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1690 wdr->cmd_iohs[wd_status], 0); 1691 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1692 wdr->cmd_iohs[wd_error], 0); 1693 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1694 wdr->cmd_iohs[wd_seccnt], 0); 1695 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1696 wdr->cmd_iohs[wd_sector], 0) << 0; 1697 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1698 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1699 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1700 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1701 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1702 wdr->cmd_iohs[wd_sdh], 0); 1703 1704 if ((ata_c->flags & AT_LBA48) != 0) { 1705 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1706 if ((ata_c->flags & AT_POLL) != 0) 1707 bus_space_write_1(wdr->ctl_iot, 1708 wdr->ctl_ioh, wd_aux_ctlr, 1709 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1710 else 1711 bus_space_write_1(wdr->ctl_iot, 1712 wdr->ctl_ioh, wd_aux_ctlr, 1713 WDCTL_HOB|WDCTL_4BIT); 1714 } 1715 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1716 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1717 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1718 wdr->cmd_iohs[wd_sector], 0) << 24; 1719 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1720 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1721 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1722 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1723 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1724 if ((ata_c->flags & AT_POLL) != 0) 1725 bus_space_write_1(wdr->ctl_iot, 1726 wdr->ctl_ioh, wd_aux_ctlr, 1727 WDCTL_4BIT|WDCTL_IDS); 1728 else 1729 bus_space_write_1(wdr->ctl_iot, 1730 wdr->ctl_ioh, wd_aux_ctlr, 1731 WDCTL_4BIT); 1732 } 1733 } else { 1734 ata_c->r_lba |= 1735 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1736 } 1737 ata_c->r_device &= 0xf0; 1738 } 1739 1740 __wdccommand_done_end(chp, xfer); 1741 1742 ata_deactivate_xfer(chp, xfer); 1743 1744 out: 1745 if (ata_c->flags & AT_POLL) { 1746 /* enable interrupts */ 1747 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1748 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1749 wd_aux_ctlr, WDCTL_4BIT); 1750 delay(10); /* some drives need a little delay here */ 1751 } 1752 1753 if (start) 1754 atastart(chp); 1755 } 1756 1757 static void 1758 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1759 { 1760 struct ata_command *ata_c = &xfer->c_ata_c; 1761 1762 ata_c->flags |= AT_DONE; 1763 } 1764 1765 static void 1766 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1767 int reason) 1768 { 1769 struct ata_command *ata_c = &xfer->c_ata_c; 1770 bool deactivate = true; 1771 1772 switch (reason) { 1773 case KILL_GONE_INACTIVE: 1774 deactivate = false; 1775 /* FALLTHROUGH */ 1776 case KILL_GONE: 1777 ata_c->flags |= AT_GONE; 1778 break; 1779 case KILL_RESET: 1780 ata_c->flags |= AT_RESET; 1781 break; 1782 default: 1783 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1784 reason); 1785 panic("__wdccommand_kill_xfer"); 1786 } 1787 1788 __wdccommand_done_end(chp, xfer); 1789 1790 if (deactivate) 1791 ata_deactivate_xfer(chp, xfer); 1792 } 1793 1794 /* 1795 * Send a command. The drive should be ready. 1796 * Assumes interrupts are blocked. 1797 */ 1798 void 1799 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1800 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1801 u_int8_t features) 1802 { 1803 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1804 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1805 1806 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1807 "sector=%d count=%d features=%d\n", 1808 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1809 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1810 1811 if (wdc->select) 1812 wdc->select(chp,drive); 1813 1814 /* Select drive, head, and addressing mode. */ 1815 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1816 WDSD_IBM | (drive << 4) | head); 1817 /* Load parameters into the wd_features register. */ 1818 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1819 features); 1820 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1821 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1822 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1823 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1824 0, cylin >> 8); 1825 1826 /* Send command. */ 1827 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1828 return; 1829 } 1830 1831 /* 1832 * Send a 48-bit addressing command. The drive should be ready. 1833 * Assumes interrupts are blocked. 1834 */ 1835 void 1836 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1837 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1838 { 1839 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1840 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1841 1842 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1843 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1844 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1845 chp->ch_channel, drive, command, blkno, count, features, device), 1846 DEBUG_FUNCS); 1847 1848 KASSERT(drive < wdc->wdc_maxdrives); 1849 1850 if (wdc->select) 1851 wdc->select(chp,drive); 1852 1853 /* Select drive, head, and addressing mode. */ 1854 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1855 (drive << 4) | device); 1856 1857 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1858 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1859 0, features); 1860 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1861 0, count); 1862 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1863 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1864 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1865 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1866 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1867 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1868 } else { 1869 /* previous */ 1870 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1871 0, features >> 8); 1872 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1873 0, count >> 8); 1874 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1875 0, blkno >> 24); 1876 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1877 0, blkno >> 32); 1878 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1879 0, blkno >> 40); 1880 1881 /* current */ 1882 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1883 0, features); 1884 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1885 0, count); 1886 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1887 0, blkno); 1888 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1889 0, blkno >> 8); 1890 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1891 0, blkno >> 16); 1892 } 1893 1894 /* Send command. */ 1895 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1896 return; 1897 } 1898 1899 /* 1900 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1901 * tested by the caller. 1902 */ 1903 void 1904 wdccommandshort(struct ata_channel *chp, int drive, int command) 1905 { 1906 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1907 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1908 1909 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1910 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1911 command), DEBUG_FUNCS); 1912 1913 if (wdc->select) 1914 wdc->select(chp,drive); 1915 1916 /* Select drive. */ 1917 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1918 WDSD_IBM | (drive << 4)); 1919 1920 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1921 } 1922 1923 static void 1924 __wdcerror(struct ata_channel *chp, const char *msg) 1925 { 1926 struct atac_softc *atac = chp->ch_atac; 1927 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1928 1929 if (xfer == NULL) 1930 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1931 chp->ch_channel, msg); 1932 else 1933 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1934 chp->ch_channel, xfer->c_drive, msg); 1935 } 1936 1937 /* 1938 * the bit bucket 1939 */ 1940 void 1941 wdcbit_bucket(struct ata_channel *chp, int size) 1942 { 1943 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1944 1945 for (; size >= 2; size -= 2) 1946 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1947 if (size) 1948 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1949 } 1950 1951 static void 1952 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1953 { 1954 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1955 1956 if ((chp->ch_atac->atac_cap & ATAC_CAP_DATA16) == 0) { 1957 /* 1958 * ATA_DRIVE_NOSTREAM is used for the IDENTIFY 1959 * command for ... reasons. Bad reasons, but 1960 * reasons nonetheless. So, emulate it as if 1961 * it were 16-bit PIO. 1962 */ 1963 if (flags & ATA_DRIVE_NOSTREAM) { 1964 uint8_t *cp = bf; 1965 for (size_t i = 0; i < len; i++) { 1966 cp[i ^ 1] = bus_space_read_1(wdr->cmd_iot, 1967 wdr->cmd_iohs[wd_data], 0); 1968 } 1969 return; 1970 } 1971 bus_space_read_multi_1(wdr->cmd_iot, 1972 wdr->cmd_iohs[wd_data], 0, bf, len); 1973 return; 1974 } 1975 1976 #ifndef __NO_STRICT_ALIGNMENT 1977 if ((uintptr_t)bf & 1) 1978 goto unaligned; 1979 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1980 goto unaligned; 1981 #endif 1982 1983 if (flags & ATA_DRIVE_NOSTREAM) { 1984 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 1985 /* 1986 * Because consumers of IDENTIFY are too lazy to byte-swap 1987 * their own payload, we have to do it ourselves here. 1988 * XXX THIS IS SO DUMB! FIX CONSUMERS OF IDENTIFY!!! 1989 * 1990 * Don't even try to deal with 32-bit PIO in this situation. 1991 */ 1992 KASSERT((flags & ATA_DRIVE_CAP32) == 0); 1993 uint16_t *p16 = bf; 1994 for (; len > 1; len -= 2) { 1995 *p16++ = 1996 bswap16(bus_space_read_2(wdr->cmd_iot, 1997 wdr->cmd_iohs[wd_data], 1998 0)); 1999 } 2000 bf = (void *)p16; 2001 #else 2002 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 2003 bus_space_read_multi_4(wdr->data32iot, 2004 wdr->data32ioh, 0, bf, len >> 2); 2005 bf = (char *)bf + (len & ~3); 2006 len &= 3; 2007 } 2008 if (len > 1) { 2009 bus_space_read_multi_2(wdr->cmd_iot, 2010 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2011 bf = (char *)bf + (len & ~1); 2012 len &= 1; 2013 } 2014 #endif 2015 } else { 2016 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 2017 bus_space_read_multi_stream_4(wdr->data32iot, 2018 wdr->data32ioh, 0, bf, len >> 2); 2019 bf = (char *)bf + (len & ~3); 2020 len &= 3; 2021 } 2022 if (len > 1) { 2023 bus_space_read_multi_stream_2(wdr->cmd_iot, 2024 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2025 bf = (char *)bf + (len & ~1); 2026 len &= 1; 2027 } 2028 } 2029 if (len) 2030 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 2031 wdr->cmd_iohs[wd_data], 0); 2032 return; 2033 2034 #ifndef __NO_STRICT_ALIGNMENT 2035 unaligned: 2036 if (flags & ATA_DRIVE_NOSTREAM) { 2037 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 2038 KASSERT((flags & ATA_DRIVE_CAP32) == 0); 2039 #else 2040 if (flags & ATA_DRIVE_CAP32) { 2041 while (len > 3) { 2042 uint32_t val; 2043 2044 val = bus_space_read_4(wdr->data32iot, 2045 wdr->data32ioh, 0); 2046 memcpy(bf, &val, 4); 2047 bf = (char *)bf + 4; 2048 len -= 4; 2049 } 2050 } 2051 #endif 2052 while (len > 1) { 2053 uint16_t val; 2054 2055 val = bus_space_read_2(wdr->cmd_iot, 2056 wdr->cmd_iohs[wd_data], 0); 2057 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 2058 val = bswap16(val); 2059 #endif 2060 memcpy(bf, &val, 2); 2061 bf = (char *)bf + 2; 2062 len -= 2; 2063 } 2064 } else { 2065 if (flags & ATA_DRIVE_CAP32) { 2066 while (len > 3) { 2067 uint32_t val; 2068 2069 val = bus_space_read_stream_4(wdr->data32iot, 2070 wdr->data32ioh, 0); 2071 memcpy(bf, &val, 4); 2072 bf = (char *)bf + 4; 2073 len -= 4; 2074 } 2075 } 2076 while (len > 1) { 2077 uint16_t val; 2078 2079 val = bus_space_read_stream_2(wdr->cmd_iot, 2080 wdr->cmd_iohs[wd_data], 0); 2081 memcpy(bf, &val, 2); 2082 bf = (char *)bf + 2; 2083 len -= 2; 2084 } 2085 } 2086 #endif 2087 } 2088 2089 static void 2090 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 2091 { 2092 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 2093 2094 #if !defined(__BUS_SPACE_HAS_STREAM_METHODS) && _BYTE_ORDER == _BIG_ENDIAN 2095 /* 2096 * This should absolutely never be necessary. If it is, we 2097 * have bigger problems. 2098 */ 2099 KASSERT((flags & ATA_DRIVE_NOSTREAM) == 0); 2100 #endif 2101 2102 if ((chp->ch_atac->atac_cap & ATAC_CAP_DATA16) == 0) { 2103 /* 2104 * ATA_DRIVE_NOSTREAM is not exactly expected for 2105 * PIO writes, but emulate it as if it were 2106 * 16-bit PIO. 2107 */ 2108 if (flags & ATA_DRIVE_NOSTREAM) { 2109 uint8_t *cp = bf; 2110 for (size_t i = 0; i < len; i++) { 2111 bus_space_write_1(wdr->cmd_iot, 2112 wdr->cmd_iohs[wd_data], 0, 2113 cp[i ^ 1]); 2114 } 2115 return; 2116 } 2117 bus_space_write_multi_1(wdr->cmd_iot, 2118 wdr->cmd_iohs[wd_data], 0, bf, len); 2119 return; 2120 } 2121 2122 #ifndef __NO_STRICT_ALIGNMENT 2123 if ((uintptr_t)bf & 1) 2124 goto unaligned; 2125 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2126 goto unaligned; 2127 #endif 2128 2129 if (flags & ATA_DRIVE_NOSTREAM) { 2130 if (flags & ATA_DRIVE_CAP32) { 2131 bus_space_write_multi_4(wdr->data32iot, 2132 wdr->data32ioh, 0, bf, len >> 2); 2133 bf = (char *)bf + (len & ~3); 2134 len &= 3; 2135 } 2136 if (len) { 2137 bus_space_write_multi_2(wdr->cmd_iot, 2138 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2139 } 2140 } else { 2141 if (flags & ATA_DRIVE_CAP32) { 2142 bus_space_write_multi_stream_4(wdr->data32iot, 2143 wdr->data32ioh, 0, bf, len >> 2); 2144 bf = (char *)bf + (len & ~3); 2145 len &= 3; 2146 } 2147 if (len) { 2148 bus_space_write_multi_stream_2(wdr->cmd_iot, 2149 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2150 } 2151 } 2152 return; 2153 2154 #ifndef __NO_STRICT_ALIGNMENT 2155 unaligned: 2156 if (flags & ATA_DRIVE_NOSTREAM) { 2157 if (flags & ATA_DRIVE_CAP32) { 2158 while (len > 3) { 2159 uint32_t val; 2160 2161 memcpy(&val, bf, 4); 2162 bus_space_write_4(wdr->data32iot, 2163 wdr->data32ioh, 0, val); 2164 bf = (char *)bf + 4; 2165 len -= 4; 2166 } 2167 } 2168 while (len > 1) { 2169 uint16_t val; 2170 2171 memcpy(&val, bf, 2); 2172 bus_space_write_2(wdr->cmd_iot, 2173 wdr->cmd_iohs[wd_data], 0, val); 2174 bf = (char *)bf + 2; 2175 len -= 2; 2176 } 2177 } else { 2178 if (flags & ATA_DRIVE_CAP32) { 2179 while (len > 3) { 2180 uint32_t val; 2181 2182 memcpy(&val, bf, 4); 2183 bus_space_write_stream_4(wdr->data32iot, 2184 wdr->data32ioh, 0, val); 2185 bf = (char *)bf + 4; 2186 len -= 4; 2187 } 2188 } 2189 while (len > 1) { 2190 uint16_t val; 2191 2192 memcpy(&val, bf, 2); 2193 bus_space_write_stream_2(wdr->cmd_iot, 2194 wdr->cmd_iohs[wd_data], 0, val); 2195 bf = (char *)bf + 2; 2196 len -= 2; 2197 } 2198 } 2199 #endif 2200 } 2201
Indexes created Sun Oct 25 00:26:45 UTC 2026