HomeSort by: relevance | last modified time | path
    Searched defs:imm6 (Results 1 - 21 of 21) sorted by relevancy

  /src/external/gpl3/gdb/dist/sim/arm/
thumbemu.c 194 ARMword imm6; local
203 imm6 = tBITS (0, 5);
208 simm32 = (J1 << 19) | (J2 << 18) | (imm6 << 12) | (imm11 << 1);
  /src/external/gpl3/gdb.old/dist/sim/arm/
thumbemu.c 194 ARMword imm6; local
203 imm6 = tBITS (0, 5);
208 simm32 = (J1 << 19) | (J2 << 18) | (imm6 << 12) | (imm11 << 1);
  /src/external/gpl3/binutils/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon10627
  /src/external/gpl3/binutils.old/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon12091
  /src/external/gpl3/gdb/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon18738
  /src/external/gpl3/gdb.old/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon21479
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 6587 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); local
6593 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
  /src/external/gpl3/gdb/dist/gdb/
mep-tdep.c 1557 /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */
1715 CORE_ADDR imm6 = ADD_OFFSET (insn);
1717 reg[rn] = pv_add_constant (reg[rn], imm6);
1710 CORE_ADDR imm6 = ADD_OFFSET (insn); local
  /src/external/gpl3/gdb.old/dist/gdb/
mep-tdep.c 1557 /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */
1715 CORE_ADDR imm6 = ADD_OFFSET (insn);
1717 reg[rn] = pv_add_constant (reg[rn], imm6);
1710 CORE_ADDR imm6 = ADD_OFFSET (insn); local
  /src/external/gpl3/binutils/dist/gas/config/
bfin-parse.c 266 #define imm6(x) EXPR_VALUE (x) macro
4410 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
4567 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
4636 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
4637 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 1, IS_A1 ((yyvsp[-3].reg)));
4663 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
4841 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
4842 (yyval.instr) = DSP32SHIFTIMM (3, 0, imm6 ((yyvsp[0].expr)), 0, 2, IS_A1 ((yyvsp[-4].reg)));
4855 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 3, IS_A1 ((yyvsp[-5].reg)));
  /src/external/gpl3/binutils/dist/opcodes/
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5942 if ((imm6 & 0x20) == 0)
5949 && ((imm6 & 0x30) == 0x20))
6933 reason = "invalid imm6";
6937 reason = "fsi = 0 and invalid imm6";
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7744 imm6 &= 0x1f;
7747 if ((imm6 & 0x20) != 0
5940 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7740 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
bfin-dis.c 92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
471 #define imm6(x) fmtconst (c_imm6, x, 0, outf) macro
4370 OUTS (outf, imm6 (immag));
4405 OUTS (outf, imm6 (immag));
4483 OUTS (outf, imm6 (immag));
  /src/external/gpl3/binutils.old/dist/gas/config/
bfin-parse.c 266 #define imm6(x) EXPR_VALUE (x) macro
4410 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
4567 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
4636 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
4637 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 1, IS_A1 ((yyvsp[-3].reg)));
4663 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
4841 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
4842 (yyval.instr) = DSP32SHIFTIMM (3, 0, imm6 ((yyvsp[0].expr)), 0, 2, IS_A1 ((yyvsp[-4].reg)));
4855 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 3, IS_A1 ((yyvsp[-5].reg)));
  /src/external/gpl3/binutils.old/dist/opcodes/
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5942 if ((imm6 & 0x20) == 0)
5949 && ((imm6 & 0x30) == 0x20))
6933 reason = "invalid imm6";
6937 reason = "fsi = 0 and invalid imm6";
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7744 imm6 &= 0x1f;
7747 if ((imm6 & 0x20) != 0
5940 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7740 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
bfin-dis.c 92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
471 #define imm6(x) fmtconst (c_imm6, x, 0, outf) macro
4370 OUTS (outf, imm6 (immag));
4405 OUTS (outf, imm6 (immag));
4483 OUTS (outf, imm6 (immag));
  /src/external/gpl3/gdb/dist/opcodes/
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5942 if ((imm6 & 0x20) == 0)
5949 && ((imm6 & 0x30) == 0x20))
6933 reason = "invalid imm6";
6937 reason = "fsi = 0 and invalid imm6";
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7744 imm6 &= 0x1f;
7747 if ((imm6 & 0x20) != 0
5940 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7740 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
bfin-dis.c 92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
471 #define imm6(x) fmtconst (c_imm6, x, 0, outf) macro
4370 OUTS (outf, imm6 (immag));
4405 OUTS (outf, imm6 (immag));
4483 OUTS (outf, imm6 (immag));
  /src/external/gpl3/gdb/dist/sim/bfin/
bfin-sim.c 170 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
325 #define imm6(x) fmtconst_val (c_imm6, x, 0) macro
5308 int shift = imm6 (DREG (src0) & 0xFFFF);
5430 int shift = imm6 (DREG (src0) & 0xFFFF);
5933 int shift = imm6 (immag);
6092 int count = imm6 (immag);
6103 int count = imm6 (newimmag);
6114 int shift = imm6 (immag);
6129 int count = imm6 (newimmag);
  /src/external/gpl3/gdb.old/dist/opcodes/
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
6037 unsigned long imm6 = arm_decode_field (given, 16, 21);
6038 if ((imm6 & 0x20) == 0)
6045 && ((imm6 & 0x30) == 0x20))
7029 reason = "invalid imm6";
7033 reason = "fsi = 0 and invalid imm6";
7837 unsigned imm6 = (given & 0x3f0000) >> 16;
7840 imm6 &= 0x1f;
7843 if ((imm6 & 0x20) != 0
6036 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7836 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
bfin-dis.c 92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
471 #define imm6(x) fmtconst (c_imm6, x, 0, outf) macro
4370 OUTS (outf, imm6 (immag));
4405 OUTS (outf, imm6 (immag));
4483 OUTS (outf, imm6 (immag));
  /src/external/gpl3/gdb.old/dist/sim/bfin/
bfin-sim.c 170 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
325 #define imm6(x) fmtconst_val (c_imm6, x, 0) macro
5308 int shift = imm6 (DREG (src0) & 0xFFFF);
5430 int shift = imm6 (DREG (src0) & 0xFFFF);
5933 int shift = imm6 (immag);
6092 int count = imm6 (immag);
6103 int count = imm6 (newimmag);
6114 int shift = imm6 (immag);
6129 int count = imm6 (newimmag);

Completed in 111 milliseconds