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    Searched defs:input_clk (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_led.c 65 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ local
69 div = input_clk / freq;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_vega20_ppt.c 2609 int32_t input_index, input_clk, input_vol, i; local
2635 input_clk = input[i + 1];
2643 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2644 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2646 input_clk,
2652 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2653 od_table->GfxclkFmin = input_clk;
2655 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2656 od_table->GfxclkFmax = input_clk;
2684 input_clk = input[i + 1]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega20_hwmgr.c 2925 int32_t input_index, input_clk, input_vol, i; local
2948 input_clk = input[i + 1];
2956 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2957 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2959 input_clk,
2965 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2966 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2970 od_table->GfxclkFmin = input_clk;
2972 od_table->GfxclkFmax = input_clk;
2991 input_clk = input[i + 1]
    [all...]
amdgpu_smu7_hwmgr.c 4866 uint32_t input_clk; local
4907 input_clk = input[i+1] * 100;
4910 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4911 podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
4912 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
amdgpu_vega10_hwmgr.c 5237 uint32_t input_clk; local
5280 input_clk = input[i+1] * 100;
5283 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5284 dpm_table->dpm_levels[input_level].value = input_clk;
5285 podn_vdd_dep_table->entries[input_level].clk = input_clk;

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