| amdgpu_umc_v6_1.c | 99 uint64_t mc_umc_status; local in function:umc_v6_1_query_correctable_error_count
145 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
146 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
147 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
148 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
156 uint64_t mc_umc_status; local in function:umc_v6_1_querry_uncorrectable_error_count
170 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
171 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
172 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
173 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 |
218 uint64_t mc_umc_status, err_addr, retired_page, mc_umc_addrt0; local in function:umc_v6_1_query_error_address
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