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  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_display.c 5536 u32 divsel, phaseinc, auxdiv, phasedir = 0; local
5555 phaseinc = desired_divisor % iclk_pi_range;
5571 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5576 phaseinc);
5585 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5611 u32 divsel, phaseinc, auxdiv; local
5631 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5640 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;

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