HomeSort by: relevance | last modified time | path
    Searched defs:psr (Results 1 - 25 of 58) sorted by relevancy

1 2 3

  /src/sys/arch/ia64/stand/ia64/ski/
ssc.c 39 * PSR.dt register is not preserved properly and causes further memory
41 * PSR.dt across the SSC call. We do this by saving and restoring psr.l
49 register u_int64_t psr; local
52 __asm __volatile("mov %0=psr;;" : "=r"(psr));
57 __asm __volatile("mov psr.l=%0;; srlz.d" :: "r"(psr));
  /src/sys/arch/sparc/sparc/
process_machdep.c 125 int psr = l->l_md.md_tf->tf_psr & ~PSR_ICC; local
131 l->l_md.md_tf->tf_psr = psr | (regs->r_psr & PSR_ICC);
trap.c 222 trap(unsigned type, int psr, int pc, struct trapframe *tf)
241 if (psr & PSR_PS) {
297 snprintb(bits, sizeof(bits), PSR_BITS, psr);
298 printf("trap type 0x%x: pc=0x%x npc=0x%x psr=%s\n",
335 snprintb(bits, sizeof(bits), PSR_BITS, psr);
336 printf("trap type 0x%x: pc=0x%x npc=0x%x psr=%s\n",
759 mem_access_fault(unsigned type, int ser, u_int v, int pc, int psr,
826 if (psr & PSR_PS) {
922 if (psr & PSR_PS) {
965 if ((psr & PSR_PS) == 0)
978 int pc, psr; local
    [all...]
  /src/sys/arch/ia64/stand/efi/libefi/
exec.c 99 u_int64_t psr; local
100 __asm __volatile("mov %0=psr;;" : "=r" (psr));
101 __asm __volatile("rsm psr.ic|psr.i;; srlz.i;;");
102 return psr;
106 restore_ic(u_int64_t psr)
108 __asm __volatile("mov psr.l=%0;; srlz.i" :: "r" (psr));
112 * Entered with psr.ic and psr.i both zero
117 u_int64_t psr; local
138 u_int64_t psr; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dmub_psr.c 42 * Get PSR state from firmware.
51 * Enable/Disable PSR.
73 * Set PSR level.
97 * Setup PSR by programming phy registers and sending psr hw context values to firmware.
193 * Construct PSR object.
195 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
197 psr->ctx = ctx;
198 psr->funcs = &psr_funcs;
202 * Allocate and initialize PSR object
206 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); local
    [all...]
  /src/sys/arch/ia64/include/
cpufunc.h 201 __asm __volatile ("rsm psr.i");
208 __asm __volatile ("ssm psr.i;; srlz.d");
214 register_t psr; local
216 __asm __volatile ("mov %0=psr;;" : "=r"(psr));
218 return (psr & IA64_PSR_I) ? 1 : 0;
  /src/external/gpl3/gdb/dist/gdb/
sparc-netbsd-tdep.c 43 0 * 4, /* %psr */
104 ULONGEST psr;
167 psr = get_frame_memory_unsigned (this_frame, addr, 4);
168 if (psr & PSR_EF)
103 ULONGEST psr; local
ia64-linux-nat.c 66 This PSR bit is set in
287 PT_CR_IPSR, /* psr */
537 ULONGEST psr; local
539 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
540 if (!(psr & IA64_PSR_DB))
542 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
544 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
692 CORE_ADDR psr; local
703 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
704 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoin
    [all...]
sparc-linux-tdep.c 205 32 * 4, /* %psr */
261 ULONGEST psr;
271 Note that after we return from the dummy call, the PSR et al.
274 regcache_cooked_read_unsigned (regcache, SPARC32_PSR_REGNUM, &psr);
275 psr &= ~PSR_SYSCALL;
276 regcache_cooked_write_unsigned (regcache, SPARC32_PSR_REGNUM, psr);
258 ULONGEST psr; local
  /src/external/gpl3/gdb.old/dist/gdb/
sparc-netbsd-tdep.c 43 0 * 4, /* %psr */
104 ULONGEST psr;
167 psr = get_frame_memory_unsigned (this_frame, addr, 4);
168 if (psr & PSR_EF)
103 ULONGEST psr; local
ia64-linux-nat.c 66 This PSR bit is set in
287 PT_CR_IPSR, /* psr */
538 ULONGEST psr; local
540 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
541 if (!(psr & IA64_PSR_DB))
543 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
545 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
693 CORE_ADDR psr; local
704 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
705 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoin
    [all...]
sparc-linux-tdep.c 205 32 * 4, /* %psr */
261 ULONGEST psr;
271 Note that after we return from the dummy call, the PSR et al.
274 regcache_cooked_read_unsigned (regcache, SPARC32_PSR_REGNUM, &psr);
275 psr &= ~PSR_SYSCALL;
276 regcache_cooked_write_unsigned (regcache, SPARC32_PSR_REGNUM, psr);
258 ULONGEST psr; local
  /src/sys/arch/arm/at91/
at91pio.c 128 uint32_t psr, osr, pin; local
154 psr = PIO_READ(sc, PIO_PSR); // only ports
157 psr &= ~at91_gpio_mask(sc->sc_pid);
160 if (psr & (1 << j))
  /src/sys/arch/ia64/ia64/
machdep.c 268 uint64_t psr; local
283 __asm __volatile("mov %0=psr" : "=r"(psr));
284 __asm __volatile("rsm psr.ic|psr.i");
290 __asm __volatile("mov psr.l=%0" :: "r" (psr));
298 uint64_t psr; local
311 __asm __volatile("mov %0=psr" : "=r"(psr));
330 uint64_t psr; local
    [all...]
  /src/sys/dev/isa/
if_ntwoc_isa.c 151 u_int8_t psr; local
153 /* get old psr value replace old window with new */
154 psr = bus_space_read_1(sca->sc_iot, sca->sc_ioh, NTWOC_PSR);
155 psr &= ~NTWOC_PG_MSK;
156 psr |= ((addr >> sca->scu_pageshift) & NTWOC_PG_MSK);
157 bus_space_write_1(sca->sc_iot, sca->sc_ioh, NTWOC_PSR, psr);
  /src/sys/arch/sparc/include/
psl.h 91 * SPARC V9 PSTATE register (what replaces the PSR in V9)
243 * GCC pseudo-functions for manipulating PSR (primarily PIL field).
248 int psr; local
250 __asm volatile("rd %%psr,%0" : "=r" (psr));
251 return (psr);
266 __asm volatile("wr %0,0,%%psr" : : "r" (newpsr) : "memory");
273 int psr, oldipl; local
276 * wrpsr xors two values: we choose old psr and old ipl here,
277 * which gives us the same value as the old psr but with al
321 int psr, oldipl; local
352 int psr; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_psr.c 42 * DOC: Panel Self Refresh (PSR/SRD)
45 * panels witch have a remote frame buffer (RFB) implemented according to PSR
46 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
54 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
58 * The implementation uses the hardware-based PSR support which automatically
63 * part doesn't work too well, hence why the i915 PSR support uses the
90 switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
112 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
114 trans_shift = dev_priv->psr.transcoder;
119 if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ
1013 struct i915_psr *psr = &dev_priv->psr; local
1201 struct i915_psr *psr = &dev_priv->psr; local
1424 struct i915_psr *psr = &dev_priv->psr; local
1450 struct i915_psr *psr = &dev_priv->psr; local
1473 struct i915_psr *psr = &dev_priv->psr; local
    [all...]
  /src/external/bsd/dhcpcd/dist/src/
privsep-root.c 204 struct psr_error psr = { local
210 { .iov_base = &psr, .iov_len = sizeof(psr) },
226 psr.psr_result = err;
227 psr.psr_errno = errno;
  /src/external/gpl3/gdb/dist/gdb/stubs/
sparc-stub.c 119 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR };
145 mov %psr, %l0
224 st %l0, [%sp + (24 + 65) * 4] ! PSR
233 mov %l4, %psr ! Turn on traps, disable interrupts
250 ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
257 mov %l1, %psr ! Make sure that traps are disabled
662 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
668 unsigned long *newsp, psr; local
670 psr = registers[PSR];
    [all...]
  /src/external/gpl3/gdb/dist/sim/erc32/
sis.h 73 uint32_t psr; /* IU registers */ member in struct:pstate
  /src/external/gpl3/gdb/dist/sim/frv/
traps.c 309 PSR.ET=1
310 PSR.S=PSR.PS
313 PSR.ET=BPSR.BET
314 PSR.S=BPSR.BS
324 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
337 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
349 USI psr = GET_PSR ();
352 SET_PSR_ET (psr, 1);
353 SET_PSR_S (psr, GET_PSR_PS (psr))
348 USI psr = GET_PSR (); local
357 USI psr = GET_PSR (); local
    [all...]
  /src/external/gpl3/gdb.old/dist/gdb/stubs/
sparc-stub.c 119 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR };
145 mov %psr, %l0
224 st %l0, [%sp + (24 + 65) * 4] ! PSR
233 mov %l4, %psr ! Turn on traps, disable interrupts
250 ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
257 mov %l1, %psr ! Make sure that traps are disabled
662 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
668 unsigned long *newsp, psr; local
670 psr = registers[PSR];
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/erc32/
sis.h 73 uint32_t psr; /* IU registers */ member in struct:pstate
  /src/external/gpl3/gdb.old/dist/sim/frv/
traps.c 309 PSR.ET=1
310 PSR.S=PSR.PS
313 PSR.ET=BPSR.BET
314 PSR.S=BPSR.BS
324 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
337 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
349 USI psr = GET_PSR ();
352 SET_PSR_ET (psr, 1);
353 SET_PSR_S (psr, GET_PSR_PS (psr))
348 USI psr = GET_PSR (); local
357 USI psr = GET_PSR (); local
    [all...]
  /src/sys/arch/mac68k/mac68k/
machdep.c 2233 u_short psr; local
2249 switch (get_pte(addr, pte, &psr)) {
2268 psr &= 0x0007; /* Number of levels we went */
2269 for (i = 0; i < psr; i++)

Completed in 51 milliseconds

1 2 3