HomeSort by: relevance | last modified time | path
    Searched defs:reg_base (Results 1 - 16 of 16) sorted by relevancy

  /src/external/gpl3/gdb/dist/sim/bfin/
dv-eth_phy.c 40 #define reg_base() offsetof(struct eth_phy, regs[0]) macro
41 #define reg_offset(reg) (offsetof(struct eth_phy, reg) - reg_base())
89 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
120 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
  /src/external/gpl3/gdb.old/dist/sim/bfin/
dv-eth_phy.c 40 #define reg_base() offsetof(struct eth_phy, regs[0]) macro
41 #define reg_offset(reg) (offsetof(struct eth_phy, reg) - reg_base())
89 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
120 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_wopcm.c 206 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); local
210 !(reg_base & GUC_WOPCM_OFFSET_VALID))
213 *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
interrupt.c 159 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
334 regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
336 regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
362 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
368 i915_mmio_reg_offset(up_irq_info->reg_base));
370 i915_mmio_reg_offset(up_irq_info->reg_base));
409 unsigned int reg_base; local
416 reg_base = i915_mmio_reg_offset(info->reg_base);
420 regbase_to_imr(reg_base)))) {
480 u32 reg_base; local
    [all...]
interrupt.h 180 i915_reg_t reg_base; member in struct:intel_gvt_irq_info
  /src/external/gpl3/gdb.old/dist/opcodes/
nios2-dis.c 280 struct nios2_reg *reg_base; local
303 reg_base = nios2_control_regs ();
304 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
308 reg_base = nios2_regs;
317 reg_base = nios2_coprocessor_regs ();
326 reg_base = nios2_coprocessor_regs ();
335 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
341 reg_base = nios2_regs;
353 reg_base = nios2_coprocessor_regs ();
377 reg_base = nios2_coprocessor_regs ()
    [all...]
tic6x-dis.c 819 unsigned int reg_base = 0; local
929 reg_base = 16;
941 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
947 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
958 snprintf (operands[op_num], 24, "b%u", reg_base + fld_val);
969 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
975 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
984 reg_side, reg_base + fld_val + 1,
985 reg_side, reg_base + fld_val);
994 reg_side, reg_base + fld_val + 1
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
tic6x-dis.c 819 unsigned int reg_base = 0; local
929 reg_base = 16;
941 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
947 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
958 snprintf (operands[op_num], 24, "b%u", reg_base + fld_val);
969 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
975 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
984 reg_side, reg_base + fld_val + 1,
985 reg_side, reg_base + fld_val);
994 reg_side, reg_base + fld_val + 1
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
tic6x-dis.c 819 unsigned int reg_base = 0; local
929 reg_base = 16;
941 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
947 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
958 snprintf (operands[op_num], 24, "b%u", reg_base + fld_val);
969 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
975 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
984 reg_side, reg_base + fld_val + 1,
985 reg_side, reg_base + fld_val);
994 reg_side, reg_base + fld_val + 1
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
tic6x-dis.c 819 unsigned int reg_base = 0; local
929 reg_base = 16;
941 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
947 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
958 snprintf (operands[op_num], 24, "b%u", reg_base + fld_val);
969 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
975 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val);
984 reg_side, reg_base + fld_val + 1,
985 reg_side, reg_base + fld_val);
994 reg_side, reg_base + fld_val + 1
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx.h 107 uint32_t reg_base; member in struct:amdgpu_scratch
  /src/external/gpl3/gcc.old/dist/gcc/config/avr/
avr.cc 4357 int reg_base = true_regnum (base);
4359 if (reg_dest == reg_base) /* R = (R) */
4384 int reg_base = true_regnum (XEXP (base, 0));
4386 if (reg_base == reg_dest)
4442 int reg_base = true_regnum (base);
4447 if (reg_base > 0)
4452 if (reg_dest == reg_base) /* R = (R) */
4457 if (reg_base != REG_X)
4472 int reg_base = true_regnum (XEXP (base, 0));
4500 if (reg_base == REG_X
4356 int reg_base = true_regnum (base); local
4383 int reg_base = true_regnum (XEXP (base, 0)); local
4441 int reg_base = true_regnum (base); local
4471 int reg_base = true_regnum (XEXP (base, 0)); local
4577 int reg_base = true_regnum (base); local
4623 int reg_base = true_regnum (XEXP (base, 0)); local
4671 int reg_base = true_regnum (base); local
4851 int reg_base = true_regnum (base); local
4911 int reg_base = REGNO (XEXP (base, 0)); local
4955 int reg_base = true_regnum (base); local
5213 int reg_base = true_regnum (base); local
5246 int reg_base = true_regnum (base); local
5280 int reg_base = true_regnum (base); local
5418 int reg_base = true_regnum (base); local
5457 int reg_base = REGNO (XEXP (base, 0)); local
5494 int reg_base = true_regnum (base); local
5752 int reg_base = true_regnum (base); local
5862 int reg_base = true_regnum (base); local
5894 int reg_base = REGNO (XEXP (base, 0)); local
5930 int reg_base = true_regnum (base); local
    [all...]
  /src/external/gpl3/gcc/dist/gcc/config/avr/
avr.cc 5003 int reg_base = true_regnum (base);
5005 if (reg_dest == reg_base) /* R = (R) */
5030 int reg_base = true_regnum (XEXP (base, 0));
5032 if (reg_base == reg_dest)
5087 int reg_base = true_regnum (base);
5092 if (reg_base > 0)
5097 if (reg_dest == reg_base) /* R = (R) */
5102 if (reg_base != REG_X)
5117 int reg_base = true_regnum (XEXP (base, 0));
5145 if (reg_base == REG_X
5002 int reg_base = true_regnum (base); local
5029 int reg_base = true_regnum (XEXP (base, 0)); local
5086 int reg_base = true_regnum (base); local
5116 int reg_base = true_regnum (XEXP (base, 0)); local
5222 int reg_base = true_regnum (base); local
5268 int reg_base = true_regnum (XEXP (base, 0)); local
5316 int reg_base = true_regnum (base); local
5496 int reg_base = true_regnum (base); local
5556 int reg_base = REGNO (XEXP (base, 0)); local
5600 int reg_base = true_regnum (base); local
5858 int reg_base = true_regnum (base); local
5891 int reg_base = true_regnum (base); local
5925 int reg_base = true_regnum (base); local
6063 int reg_base = true_regnum (base); local
6102 int reg_base = REGNO (XEXP (base, 0)); local
6139 int reg_base = true_regnum (base); local
6397 int reg_base = true_regnum (base); local
6507 int reg_base = true_regnum (base); local
6539 int reg_base = REGNO (XEXP (base, 0)); local
6575 int reg_base = true_regnum (base); local
    [all...]
  /src/external/gpl3/gdb/dist/gdb/
arm-tdep.c 12121 uint32_t reg_base , reg_dest;
12132 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
12143 precedes a LDR instruction having R15 as reg_base, it
12152 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
12159 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
12197 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
12478 uint32_t reg_base, addr_mode;
12489 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
12511 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
12522 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval)
12120 uint32_t reg_base , reg_dest; local
12477 uint32_t reg_base, addr_mode; local
    [all...]
  /src/external/gpl3/gdb.old/dist/gdb/
arm-tdep.c 12125 uint32_t reg_base , reg_dest;
12136 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
12147 preceeds a LDR instruction having R15 as reg_base, it
12156 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
12163 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval);
12201 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
12482 uint32_t reg_base, addr_mode;
12493 reg_base = bits (arm_insn_r->arm_insn, 16, 19);
12515 record_buf[arm_insn_r->reg_rec_count++] = reg_base;
12526 regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval)
12124 uint32_t reg_base , reg_dest; local
12481 uint32_t reg_base, addr_mode; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon.h 743 uint32_t reg_base; member in struct:radeon_scratch

Completed in 57 milliseconds