| /src/sys/arch/arm/nvidia/ |
| tegra_clock.h | 69 u_int set_reg; member in struct:tegra_gate_clk
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| tegra124_car.c | 349 .set_reg = (_set), \
672 u_int set_reg; member in struct:tegra124_car_rst
678 u_int set_reg; member in struct:tegra124_car_reset_reg
1372 if (tgate->set_reg == tgate->clr_reg) {
1373 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg);
1379 bus_space_write_4(bst, bsh, tgate->set_reg, v);
1382 reg = tgate->set_reg;
1545 rst->set_reg = tegra124_car_reset_regs[reg].set_reg;
1566 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask)
[all...] |
| tegra210_car.c | 361 .set_reg = (_set), \
686 u_int set_reg; member in struct:tegra210_car_rst
692 u_int set_reg; member in struct:tegra210_car_reset_reg
1470 if (tgate->set_reg == tgate->clr_reg) {
1471 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg);
1477 bus_space_write_4(bst, bsh, tgate->set_reg, v);
1480 reg = tgate->set_reg;
1635 rst->set_reg = tegra210_car_reset_regs[reg].set_reg;
1656 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask)
[all...] |
| /src/external/gpl3/gcc/dist/gcc/ |
| web.cc | 84 void set_reg (rtx r) { reg_pvt = r; } function in struct:web_entry
280 root->set_reg (newreg);
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| /src/external/gpl3/gcc.old/dist/gcc/ |
| web.cc | 84 void set_reg (rtx r) { reg_pvt = r; } function in struct:web_entry
280 root->set_reg (newreg);
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| /src/external/gpl3/gdb.old/dist/sim/rl78/ |
| cpu.c | 127 set_reg (RL78_Register regno, SI val) function
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| /src/external/gpl3/gdb/dist/sim/rl78/ |
| cpu.c | 127 set_reg (RL78_Register regno, SI val) function
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| /src/external/gpl3/gcc/dist/gcc/config/iq2000/ |
| iq2000.cc | 393 rtx set_reg;
417 || (set_reg = operands[0]) == 0)
428 set_reg = operands[0];
429 if (set_reg == 0)
432 while (GET_CODE (set_reg) == SUBREG)
433 set_reg = SUBREG_REG (set_reg);
435 mode = GET_MODE (set_reg);
437 iq2000_load_reg = set_reg;
440 iq2000_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1)
389 rtx set_reg; local
[all...] |
| /src/external/gpl3/gcc/dist/libgcc/config/ia64/ |
| unwind-ia64.c | 465 set_reg (struct unw_reg_info *reg, enum unw_where where,
610 set_reg (sr->curr.reg + save_order[i], UNW_WHERE_GR,
642 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_GR,
657 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_SPILL_HOME,
675 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME,
686 set_reg (sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME,
703 set_reg (sr->curr.reg + UNW_REG_F2 + i, UNW_WHERE_SPILL_HOME,
720 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_GR,
735 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME,
746 set_reg (sr->curr.reg + UNW_REG_PSP, UNW_WHERE_NONE
463 set_reg (struct unw_reg_info *reg, enum unw_where where, function
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/iq2000/ |
| iq2000.cc | 394 rtx set_reg;
418 || (set_reg = operands[0]) == 0)
429 set_reg = operands[0];
430 if (set_reg == 0)
433 while (GET_CODE (set_reg) == SUBREG)
434 set_reg = SUBREG_REG (set_reg);
436 mode = GET_MODE (set_reg);
438 iq2000_load_reg = set_reg;
441 iq2000_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1)
390 rtx set_reg; local
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/ia64/ |
| unwind-ia64.c | 465 set_reg (struct unw_reg_info *reg, enum unw_where where,
610 set_reg (sr->curr.reg + save_order[i], UNW_WHERE_GR,
642 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_GR,
657 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_SPILL_HOME,
675 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME,
686 set_reg (sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME,
703 set_reg (sr->curr.reg + UNW_REG_F2 + i, UNW_WHERE_SPILL_HOME,
720 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_GR,
735 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME,
746 set_reg (sr->curr.reg + UNW_REG_PSP, UNW_WHERE_NONE
463 set_reg (struct unw_reg_info *reg, enum unw_where where, function
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon.h | 1981 int (*set_reg)(struct radeon_device *rdev, int reg, member in struct:radeon_asic::__anon5531
2829 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
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