| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gem_fence_reg.c | 50 * have their own tiling state bits and don't need fences.
52 * Also note that fences only support X and Y tiling and hence can't be used for
53 * the fancier new tiling formats like W, Ys and Yf.
142 unsigned int tiling = i915_gem_object_get_tiling(vma->obj); local
143 bool is_y_tiled = tiling == I915_TILING_Y;
248 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
409 * and tiling format.
515 * Commit delayed tiling changes if we have an object still
527 * DOC: tiling swizzling details
529 * The idea behind tiling is to increase cache hit rates by rearrangin
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/ |
| omp-general.h | 71 tree tiling; /* Tiling values (if non null). */ member in struct:omp_for_data
|
| omp-offload.cc | 80 unsigned e_mask; /* Partitioning of element loops (when tiling). */
750 the specified loop of the nest. This is 1 if we're not tiling.
1473 bool tiling = (loop->flags & OLF_TILE) != 0; local
1481 = !seq_par && this_mask == (tiling ? this_mask & -this_mask : 0);
1568 /* When tiling, vector goes to the element loop, and failing
1612 bool tiling = loop->flags & OLF_TILE; local
1630 /* Grab two axes if tiling, and we've not assigned anything */
1631 if (tiling && !(loop->mask | loop->e_mask))
1640 if (tiling && !loop->e_mask)
1658 if (assign && (!loop->mask || (tiling && !loop->e_mask) || !outer_assign)
[all...] |
| omp-expand.cc | 1556 tree tiling = fd->tiling; local
1563 /* When tiling, the first operand of the tile clause applies to the
1578 if (tiling)
1582 tree tile = TREE_VALUE (tiling);
1594 tiling = TREE_CHAIN (tiling);
7491 (this ignores tiling):
7610 /* Tiling vars. */
7647 if (fd->collapse > 1 || fd->tiling)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| i915_gem_mman.c | 29 unsigned int tiling; member in struct:tile
42 if (tile->tiling == I915_TILING_NONE)
48 if (tile->tiling == I915_TILING_X) {
101 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
103 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n",
104 tile->tiling, tile->stride, err);
108 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
154 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%llu + %u [0x%llx]) of 0x%x, found 0x%x\n",
159 tile->tiling ? tile_row_pages(obj) : 0,
160 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride
309 int tiling; local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/ |
| omp-general.h | 73 tree tiling; /* Tiling values (if non null). */ member in struct:omp_for_data
|
| omp-offload.cc | 80 unsigned e_mask; /* Partitioning of element loops (when tiling). */
780 the specified loop of the nest. This is 1 if we're not tiling.
1503 bool tiling = (loop->flags & OLF_TILE) != 0; local
1511 = !seq_par && this_mask == (tiling ? this_mask & -this_mask : 0);
1598 /* When tiling, vector goes to the element loop, and failing
1642 bool tiling = loop->flags & OLF_TILE; local
1660 /* Grab two axes if tiling, and we've not assigned anything */
1661 if (tiling && !(loop->mask | loop->e_mask))
1670 if (tiling && !loop->e_mask)
1688 if (assign && (!loop->mask || (tiling && !loop->e_mask) || !outer_assign)
[all...] |
| omp-expand.cc | 1557 tree tiling = fd->tiling; local
1564 /* When tiling, the first operand of the tile clause applies to the
1579 if (tiling)
1583 tree tile = TREE_VALUE (tiling);
1595 tiling = TREE_CHAIN (tiling);
7580 (this ignores tiling):
7699 /* Tiling vars. */
7736 if (fd->collapse > 1 || fd->tiling)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display_types.h | 617 unsigned int tiling; member in struct:intel_initial_plane_config
|
| intel_display.c | 3432 switch (plane_config->tiling) {
3437 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3440 MISSING_CASE(plane_config->tiling);
3641 if (plane_config->tiling)
3841 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
9117 plane_config->tiling = I915_TILING_X;
9137 if (plane_config->tiling)
10289 u32 val, base, offset __unused, stride_mult, tiling, alpha; local
10328 tiling = val & PLANE_CTL_TILED_MASK;
10329 switch (tiling) {
16937 unsigned int tiling, stride; local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/c/ |
| c-parser.cc | 19236 bool tiling = false;
19245 tiling = true;
19281 gcc_assert (tiling || (collapse >= 1 && ordered >= 0));
19231 bool tiling = false; local
|
| /src/external/gpl3/gcc/dist/gcc/c/ |
| c-parser.cc | 22501 bool tiling = false;
22511 tiling = true;
22534 gcc_assert (tiling || (collapse >= 1 && ordered >= 0));
22496 bool tiling = false; local
|
