| /src/sys/crypto/blake2/ |
| blake2s.c | 94 uint32_t v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v10,v11,v12,v13,v14,v15; local
107 v8 = blake2s_iv[0];
129 BLAKE2S_G(v0, v4, v8, v12, m[sigma[ 0]], m[sigma[ 1]]);
135 BLAKE2S_G(v2, v7, v8, v13, m[sigma[12]], m[sigma[13]]);
140 h[0] ^= v0 ^ v8;
|
| /src/sys/external/bsd/compiler_rt/dist/lib/tsan/rtl/ |
| tsan_ppc_regs.h | 73 #define v8 8 macro
|
| /src/external/gpl3/gcc/dist/libsanitizer/tsan/ |
| tsan_ppc_regs.h | 73 #define v8 8 macro
|
| /src/external/gpl3/gcc.old/dist/libsanitizer/tsan/ |
| tsan_ppc_regs.h | 73 #define v8 8 macro
|
| /src/lib/libm/ld128/ |
| e_lgammal_r.c | 125 v8 = 2.86424622754753198010525786005443539e-02L, variable
292 y*(v8+y*(v9+y*(v10+y*v11))))))))));
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| sparc-opc.c | 64 to be a superset of v8. Unimplemented insns trap and are then theoretically
68 recognizes all v8 insns. */
69 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \ macro
137 { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },
141 /* ??? Don't some v8 priviledged insns conflict with v9? */
853 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 },
854 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */
855 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */
856 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */
857 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 },
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| sparc-opc.c | 64 to be a superset of v8. Unimplemented insns trap and are then theoretically
68 recognizes all v8 insns. */
69 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \ macro
137 { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },
141 /* ??? Don't some v8 priviledged insns conflict with v9? */
853 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 },
854 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */
855 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */
856 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */
857 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 },
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| ppc-asm.h | 148 #define v8 8 macro
|
| /src/external/gpl3/gcc.old/dist/gcc/config/rs6000/ |
| ppc-asm.h | 148 #define v8 8 macro
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| sparc-opc.c | 64 to be a superset of v8. Unimplemented insns trap and are then theoretically
68 recognizes all v8 insns. */
69 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \ macro
137 { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },
141 /* ??? Don't some v8 priviledged insns conflict with v9? */
853 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 },
854 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */
855 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */
856 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */
857 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 },
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| sparc-opc.c | 64 to be a superset of v8. Unimplemented insns trap and are then theoretically
68 recognizes all v8 insns. */
69 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \ macro
137 { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },
141 /* ??? Don't some v8 priviledged insns conflict with v9? */
853 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 },
854 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */
855 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */
856 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */
857 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 },
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-sparc.c | 43 /* ??? The default value should be V8, but sparclite support was added
45 the future we can set this to V8. */
220 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
240 { "v8", "v8", v8, 32, 1, 0, 0 },
241 { "v8a", "v8", v8, 32, 1, 0, 0 },
283 { NULL, NULL, v8, 0, 0, 0, 0 }
470 if (startswith (arg, "v8")
219 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, enumerator in enum:sparc_arch_types
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-sparc.c | 43 /* ??? The default value should be V8, but sparclite support was added
45 the future we can set this to V8. */
220 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
240 { "v8", "v8", v8, 32, 1, 0, 0 },
241 { "v8a", "v8", v8, 32, 1, 0, 0 },
282 { NULL, NULL, v8, 0, 0, 0, 0 }
469 if (startswith (arg, "v8")
219 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, enumerator in enum:sparc_arch_types
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/sparc/ |
| sparc.cc | 1679 fprintf (stderr, "V8 ");
1736 { "v8", MASK_ISA, MASK_V8 },
1898 /* FsMULd is a V8 instruction. */
1936 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
3523 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
7553 needs partial registers on v8. On v9, structures with integer
8329 int v8 = 0;
8337 v8 = 1;
8347 if (v8)
8355 gcc_assert (!v8);
8314 int v8 = 0; local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/sparc/ |
| sparc.cc | 1687 fprintf (stderr, "V8 ");
1744 { "v8", MASK_ISA, MASK_V8 },
1906 /* FsMULd is a V8 instruction. */
1944 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
3531 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
7538 needs partial registers on v8. On v9, structures with integer
8314 int v8 = 0;
8322 v8 = 1;
8332 if (v8)
8340 gcc_assert (!v8);
8299 int v8 = 0; local
[all...] |
| /src/external/gpl3/binutils/dist/bfd/ |
| elf32-arm.c | 14161 static const int v8[] = local
14163 T(V8), /* PRE_V4. */
14164 T(V8), /* V4. */
14165 T(V8), /* V4T. */
14166 T(V8), /* V5T. */
14167 T(V8), /* V5TE. */
14168 T(V8), /* V5TEJ. */
14169 T(V8), /* V6. */
14170 T(V8), /* V6KZ. */
14171 T(V8), /* V6T2. *
[all...] |
| /src/external/gpl3/binutils.old/dist/bfd/ |
| elf32-arm.c | 14288 const int v8[] = local
14290 T(V8), /* PRE_V4. */
14291 T(V8), /* V4. */
14292 T(V8), /* V4T. */
14293 T(V8), /* V5T. */
14294 T(V8), /* V5TE. */
14295 T(V8), /* V5TEJ. */
14296 T(V8), /* V6. */
14297 T(V8), /* V6KZ. */
14298 T(V8), /* V6T2. *
[all...] |
| /src/external/gpl3/gdb/dist/bfd/ |
| elf32-arm.c | 14282 const int v8[] = local
14284 T(V8), /* PRE_V4. */
14285 T(V8), /* V4. */
14286 T(V8), /* V4T. */
14287 T(V8), /* V5T. */
14288 T(V8), /* V5TE. */
14289 T(V8), /* V5TEJ. */
14290 T(V8), /* V6. */
14291 T(V8), /* V6KZ. */
14292 T(V8), /* V6T2. *
[all...] |
| /src/external/gpl3/gdb.old/dist/bfd/ |
| elf32-arm.c | 14204 const int v8[] = local
14206 T(V8), /* PRE_V4. */
14207 T(V8), /* V4. */
14208 T(V8), /* V4T. */
14209 T(V8), /* V5T. */
14210 T(V8), /* V5TE. */
14211 T(V8), /* V5TEJ. */
14212 T(V8), /* V6. */
14213 T(V8), /* V6KZ. */
14214 T(V8), /* V6T2. *
[all...] |
| /src/sys/dev/pci/ |
| if_iwmreg.h | 6205 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ member in union:iwm_scan_req_umac::__anon3354
|
