| /src/sys/dev/pci/ixgbe/ |
| if_sriov.c | 433 u32 vmolr, vec_bit, vec_reg, mta_reg; local
445 vec_reg = (vf->mc_hash[i] >> 5) & 0x7F;
447 mta_reg = IXGBE_READ_REG(&sc->hw, IXGBE_MTA(vec_reg));
449 IXGBE_WRITE_REG(&sc->hw, IXGBE_MTA(vec_reg), mta_reg);
|
| /src/external/gpl3/gcc/dist/gcc/config/riscv/ |
| riscv-v.cc | 4061 rtx ptr, vec_offset, vec_reg; local
4068 vec_reg = ops[0];
4076 vec_reg = ops[4];
4083 machine_mode vec_mode = GET_MODE (vec_reg);
4133 = {vec_reg, mask, ptr, vec_offset};
4138 rtx store_ops[] = {mask, ptr, vec_offset, vec_reg};
4147 = {vec_reg, mask, ptr, vec_offset};
4152 rtx store_ops[] = {mask, ptr, vec_offset, vec_reg};
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| simulator.c | 11522 vec_reg (unsigned v, unsigned o) function
11545 aarch64_set_vec_u8 (cpu, vec_reg (vd, i + k), j,
11556 aarch64_set_vec_u16 (cpu, vec_reg (vd, i + k), j,
11567 aarch64_set_vec_u32 (cpu, vec_reg (vd, i + k), j,
11578 aarch64_set_vec_u64 (cpu, vec_reg (vd, i + k), j,
11655 aarch64_get_vec_u8 (cpu, vec_reg (vd, i + k), j));
11667 aarch64_get_vec_u16 (cpu, vec_reg (vd, i + k), j));
11679 aarch64_get_vec_u32 (cpu, vec_reg (vd, i + k), j));
11691 aarch64_get_vec_u64 (cpu, vec_reg (vd, i + k), j));
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| simulator.c | 11522 vec_reg (unsigned v, unsigned o) function
11545 aarch64_set_vec_u8 (cpu, vec_reg (vd, i + k), j,
11556 aarch64_set_vec_u16 (cpu, vec_reg (vd, i + k), j,
11567 aarch64_set_vec_u32 (cpu, vec_reg (vd, i + k), j,
11578 aarch64_set_vec_u64 (cpu, vec_reg (vd, i + k), j,
11655 aarch64_get_vec_u8 (cpu, vec_reg (vd, i + k), j));
11667 aarch64_get_vec_u16 (cpu, vec_reg (vd, i + k), j));
11679 aarch64_get_vec_u32 (cpu, vec_reg (vd, i + k), j));
11691 aarch64_get_vec_u64 (cpu, vec_reg (vd, i + k), j));
|
