| intel_dpll_mgr.c | 1299 struct skl_wrpll_params *wrpll_params)
1364 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1373 struct skl_wrpll_params wrpll_params = { 0, }; local in function:skl_ddi_hdmi_pll_dividers
1384 &wrpll_params))
1388 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1389 wrpll_params.dco_integer;
1391 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1392 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1393 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1394 DPLL_CFGCR2_PDIV(wrpll_params.pdiv)
2330 struct skl_wrpll_params wrpll_params = { 0, }; local in function:cnl_ddi_hdmi_pll_dividers
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