1 /* $NetBSD: if_ath_pci.c,v 1.50 2018/12/09 10:38:53 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 /* 39 * Copyright (c) 2003 40 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 52 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 56 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: if_ath_pci.c,v 1.50 2018/12/09 10:38:53 jdolecek Exp $"); 67 68 /* 69 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/errno.h> 76 #include <sys/device.h> 77 #include <sys/module.h> 78 79 #include <external/isc/atheros_hal/dist/ah.h> 80 81 #include <dev/ic/ath_netbsd.h> 82 #include <dev/ic/athvar.h> 83 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcidevs.h> 87 88 /* 89 * PCI configuration space registers 90 */ 91 #define ATH_PCI_MMBA PCI_BAR(0) /* memory mapped base */ 92 93 struct ath_pci_softc { 94 struct ath_softc sc_sc; 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_tag; 97 pci_intr_handle_t sc_pih; 98 void *sc_ih; 99 bus_space_tag_t sc_iot; 100 bus_space_handle_t sc_ioh; 101 bus_size_t sc_mapsz; 102 }; 103 104 static void ath_pci_attach(device_t, device_t, void *); 105 static int ath_pci_detach(device_t, int); 106 static int ath_pci_match(device_t, cfdata_t, void *); 107 static bool ath_pci_setup(struct ath_pci_softc *); 108 109 CFATTACH_DECL_NEW(ath_pci, sizeof(struct ath_pci_softc), 110 ath_pci_match, ath_pci_attach, ath_pci_detach, NULL); 111 112 static int 113 ath_pci_match(device_t parent, cfdata_t match, void *aux) 114 { 115 const char *devname; 116 struct pci_attach_args *pa = aux; 117 118 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 119 return (devname != NULL) ? 1 : 0; 120 } 121 122 static bool 123 ath_pci_suspend(device_t self, const pmf_qual_t *qual) 124 { 125 struct ath_pci_softc *sc = device_private(self); 126 127 ath_suspend(&sc->sc_sc); 128 if (sc->sc_ih != NULL) { 129 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 130 sc->sc_ih = NULL; 131 } 132 return true; 133 } 134 135 static bool 136 ath_pci_resume(device_t self, const pmf_qual_t *qual) 137 { 138 struct ath_pci_softc *sc = device_private(self); 139 140 /* XXX re-establishing interrupt shouldn't be needed */ 141 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_pih, IPL_NET, 142 ath_intr, &sc->sc_sc, device_xname(self)); 143 if (sc->sc_ih == NULL) { 144 aprint_error_dev(self, "couldn't map interrupt\n"); 145 return false; 146 } 147 return ath_resume(&sc->sc_sc); 148 } 149 150 static void 151 ath_pci_attach(device_t parent, device_t self, void *aux) 152 { 153 struct ath_pci_softc *psc = device_private(self); 154 struct ath_softc *sc = &psc->sc_sc; 155 struct pci_attach_args *pa = aux; 156 pci_chipset_tag_t pc = pa->pa_pc; 157 const char *intrstr = NULL; 158 const char *devname; 159 pcireg_t mem_type; 160 char intrbuf[PCI_INTRSTR_LEN]; 161 162 sc->sc_dev = self; 163 sc->sc_dmat = pa->pa_dmat; 164 psc->sc_pc = pc; 165 psc->sc_tag = pa->pa_tag; 166 167 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 168 aprint_normal(": %s\n", devname); 169 170 if (!ath_pci_setup(psc)) 171 goto bad; 172 173 /* 174 * Setup memory-mapping of PCI registers. 175 */ 176 mem_type = pci_mapreg_type(pc, pa->pa_tag, ATH_PCI_MMBA); 177 if (mem_type != PCI_MAPREG_TYPE_MEM && 178 mem_type != PCI_MAPREG_MEM_TYPE_64BIT) { 179 aprint_error_dev(self, "bad pci register type %d\n", 180 (int)mem_type); 181 goto bad; 182 } 183 if (pci_mapreg_map(pa, ATH_PCI_MMBA, mem_type, 0, &psc->sc_iot, 184 &psc->sc_ioh, NULL, &psc->sc_mapsz) != 0) { 185 aprint_error_dev(self, "cannot map register space\n"); 186 goto bad; 187 } 188 189 sc->sc_st = HALTAG(psc->sc_iot); 190 sc->sc_sh = HALHANDLE(psc->sc_ioh); 191 192 /* 193 * Arrange interrupt line. 194 */ 195 if (pci_intr_map(pa, &psc->sc_pih)) { 196 aprint_error("couldn't map interrupt\n"); 197 goto bad1; 198 } 199 200 intrstr = pci_intr_string(pc, psc->sc_pih, intrbuf, sizeof(intrbuf)); 201 psc->sc_ih = pci_intr_establish_xname(pc, psc->sc_pih, IPL_NET, 202 ath_intr, sc, device_xname(self)); 203 if (psc->sc_ih == NULL) { 204 aprint_error("couldn't map interrupt\n"); 205 goto bad1; 206 } 207 208 aprint_verbose_dev(self, "interrupting at %s\n", intrstr); 209 210 if (ath_attach(PCI_PRODUCT(pa->pa_id), sc) != 0) 211 goto bad3; 212 213 if (pmf_device_register(self, ath_pci_suspend, ath_pci_resume)) { 214 pmf_class_network_register(self, &sc->sc_if); 215 pmf_device_suspend(self, &sc->sc_qual); 216 } else 217 aprint_error_dev(self, "couldn't establish power handler\n"); 218 return; 219 bad3: 220 pci_intr_disestablish(pc, psc->sc_ih); 221 psc->sc_ih = NULL; 222 bad1: 223 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 224 psc->sc_mapsz = 0; 225 bad: 226 return; 227 } 228 229 static int 230 ath_pci_detach(device_t self, int flags) 231 { 232 struct ath_pci_softc *psc = device_private(self); 233 int rv; 234 235 if ((rv = ath_detach(&psc->sc_sc)) != 0) 236 return rv; 237 238 pmf_device_deregister(self); 239 240 if (psc->sc_ih != NULL) { 241 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 242 psc->sc_ih = NULL; 243 } 244 245 if (psc->sc_mapsz != 0) { 246 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 247 psc->sc_mapsz = 0; 248 } 249 250 return 0; 251 } 252 253 static bool 254 ath_pci_setup(struct ath_pci_softc *sc) 255 { 256 int rc; 257 pcireg_t bhlc, csr, icr, lattimer; 258 259 if ((rc = pci_set_powerstate(sc->sc_pc, sc->sc_tag, PCI_PWR_D0)) != 0) 260 aprint_debug("%s: pci_set_powerstate %d\n", __func__, rc); 261 /* 262 * Enable memory mapping and bus mastering. 263 */ 264 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 265 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 266 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 267 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 268 269 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 270 aprint_error_dev(sc->sc_sc.sc_dev, 271 "couldn't enable memory mapping\n"); 272 return false; 273 } 274 if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { 275 aprint_error_dev(sc->sc_sc.sc_dev, 276 "couldn't enable bus mastering\n"); 277 return false; 278 } 279 280 /* 281 * XXX Both this comment and code are replicated in 282 * XXX cardbus_rescan(). 283 * 284 * Make sure the latency timer is set to some reasonable 285 * value. 286 * 287 * I will set the initial value of the Latency Timer here. 288 * 289 * While a PCI device owns the bus, its Latency Timer counts 290 * down bus cycles from its initial value to 0. Minimum 291 * Grant tells for how long the device wants to own the 292 * bus once it gets access, in units of 250ns. 293 * 294 * On a 33 MHz bus, there are 8 cycles per 250ns. So I 295 * multiply the Minimum Grant by 8 to find out the initial 296 * value of the Latency Timer. 297 * 298 * I never set a Latency Timer less than 0x10, since that 299 * is what the old code did. 300 */ 301 bhlc = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG); 302 icr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_INTERRUPT_REG); 303 lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr))); 304 if (PCI_LATTIMER(bhlc) < lattimer) { 305 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 306 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 307 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG, bhlc); 308 } 309 return true; 310 } 311 312 MODULE(MODULE_CLASS_DRIVER, if_ath_pci, "ath,pci"); 313 314 #ifdef _MODULE 315 #include "ioconf.c" 316 #endif 317 318 static int 319 if_ath_pci_modcmd(modcmd_t cmd, void *opaque) 320 { 321 int error = 0; 322 323 switch (cmd) { 324 case MODULE_CMD_INIT: 325 #ifdef _MODULE 326 error = config_init_component(cfdriver_ioconf_if_ath_pci, 327 cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); 328 #endif 329 return error; 330 case MODULE_CMD_FINI: 331 #ifdef _MODULE 332 error = config_fini_component(cfdriver_ioconf_if_ath_pci, 333 cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); 334 #endif 335 return error; 336 default: 337 return ENOTTY; 338 } 339 } 340
Indexes created Sun Oct 25 00:26:45 UTC 2026