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  /src/crypto/external/bsd/heimdal/dist/lib/asn1/
asn1-common.h 58 #define ASN1_MALLOC_ENCODE(T, B, BL, S, L, R) \
60 (BL) = length_##T((S)); \
61 (B) = malloc((BL)); \
65 (R) = encode_##T(((unsigned char*)(B)) + (BL) - 1, (BL), \
  /src/games/tetris/
shapes.c 51 #define BL B_COLS-1 /* bottom left */
60 /* 4*/ { 4, 12, { ML, BL, MR, } },
63 /* 7*/ { 7, 0, { TC, ML, BL, } },
73 /*17*/ { 5, 5, { TC, BC, BL, } },
  /src/sys/lib/libkern/arch/hppa/
prefix.h 39 BL .+8,r1\
45 BL .+8,r1\
51 BL .+8,r1\
57 BL .+8,r1\
76 #define MILLI_BLE(lbl) BL lbl,r31
77 #define MILLI_BLEN(lbl) BL,n lbl,r31
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64SLSHardening.cpp 247 // Transform a BLR to a BL as follows:
261 // | BL __llvm_slsblr_thunk_xN |
273 // This function merely needs to transform BLR xN into BL
289 BLOpcode = AArch64::BL;
313 // BL __llvm_slsblraa_thunk_x<N>_x<M>
337 MachineInstr *BL = BuildMI(MBB, MBBI, DL, TII->get(BLOpcode)).addSym(Sym);
339 // Now copy the implicit operands from BLR to BL and copy other necessary
341 // However, both BLR and BL instructions implictly use SP and implicitly
345 // operands from the BL created above before we copy over all implicit
349 for (unsigned OpIdx = BL->getNumExplicitOperands()
    [all...]
AArch64LowerHomogeneousPrologEpilog.cpp 419 /// bl _OUTLINED_FUNCTION_EPILOG_x30x29x19x20x21x22
463 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
487 /// bl _OUTLINED_FUNCTION_PROLOG_FRAME32_x30x29x19x20x21x22
493 /// bl _OUTLINED_FUNCTION_PROLOG_x30x29x19x20x21x22
533 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
545 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/PDB/
UDTLayout.cpp 208 auto BL = std::make_unique<BaseClassLayout>(*this, Offset, false,
211 AllBases.push_back(BL.get());
212 addChildToLayout(std::move(BL));
252 auto BL =
254 AllBases.push_back(BL.get());
259 addChildToLayout(std::move(BL));
270 for (BaseClassLayout *BL : AllBases) {
271 if (BL->hasVBPtrAtOffset(Off - BL->getOffsetInParent()))
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMSLSHardening.cpp 294 MachineInstr *BL =
299 : BuildMI(MBB, MBBI, DL, TII->get(ARM::BL)).addGlobalAddress(GV);
301 // Now copy the implicit operands from IndirectCall to BL and copy other
303 // However, both IndirectCall and BL instructions implictly use SP and
307 // implicit operands from the BL created above before we copy over all
311 for (unsigned OpIdx = BL->getNumExplicitOperands();
312 OpIdx < BL->getNumOperands(); OpIdx++) {
313 MachineOperand Op = BL->getOperand(OpIdx);
325 BL->RemoveOperand(FirstOpIdxToRemove);
326 BL->RemoveOperand(SecondOpIdxToRemove)
    [all...]
  /src/external/bsd/pcc/dist/pcc/arch/i86/
macdefs.h 167 #define BL 016
203 { BL, BH, AXBX, DXBX, CXBX, BXSI, BXDI, -1 },\
224 { AX, AL, AH, BX, BL, BH, AXDX, AXCX, AXSI, /* axbx */\
232 { DX, DL, DH, BX, BL, BH, AXDX, DXCX, DXSI, /* dxbx */\
238 { CX, CL, CH, BX, BL, BH, AXCX, DXCX, CXSI, /* cxbx */\
244 { BX, BL, BH, SI, AXBX, DXBX, CXBX, BXDI, /* bxsi */\
246 { BX, BL, BH, DI, AXBX, DXBX, CXBX, BXSI, /* bxdi */\
  /src/external/bsd/pcc/dist/pcc/arch/i386/
macdefs.h 184 #define BL 016
220 { BL, BH, EAXEBX, EDXEBX, ECXEBX, EBXESI, EBXEDI, -1 },\
241 { EAX, AL, AH, EBX, BL, BH, EAXEDX, EAXECX, EAXESI, /* eaxebx */\
249 { EDX, DL, DH, EBX, BL, BH, EAXEDX, EDXECX, EDXESI, /* edxebx */\
255 { ECX, CL, CH, EBX, BL, BH, EAXECX, EDXECX, ECXESI, /* ecxebx */\
261 { EBX, BL, BH, ESI, EAXEBX, EDXEBX, ECXEBX, EBXEDI, /* ebxesi */\
263 { EBX, BL, BH, EDI, EAXEBX, EDXEBX, ECXEBX, EBXESI, /* ebxedi */\
  /src/sys/arch/i386/include/
bioscall.h 68 #define BL r_bx.biosreg_quarter[BIOSREG_LO]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.h 34 BL,
  /src/external/gpl3/binutils/dist/opcodes/
mcore-opc.h 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
92 { "loopt", BL, 0, 0x0400 },
  /src/external/gpl3/binutils.old/dist/opcodes/
mcore-opc.h 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
92 { "loopt", BL, 0, 0x0400 },
  /src/external/gpl3/gdb.old/dist/opcodes/
mcore-opc.h 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
92 { "loopt", BL, 0, 0x0400 },
  /src/external/gpl3/gdb.old/dist/gdb/arch/
aarch64-insn.h 56 /* BL 1001 01ii iiii iiii iiii iiii iiii iiii */
63 BL = 0x80000000 | B,
215 /* Visit instruction B/BL OFFSET. */
253 /* Write a B or BL instruction into *BUF.
256 BL #offset
264 aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0)))
  /src/external/gpl3/gdb/dist/gdb/arch/
aarch64-insn.h 56 /* BL 1001 01ii iiii iiii iiii iiii iiii iiii */
63 BL = 0x80000000 | B,
215 /* Visit instruction B/BL OFFSET. */
253 /* Write a B or BL instruction into *BUF.
256 BL #offset
264 aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0)))
  /src/external/gpl3/gdb/dist/opcodes/
mcore-opc.h 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
92 { "loopt", BL, 0, 0x0400 },
  /src/external/gpl3/gcc/dist/libdecnumber/bid/
bid2dpd_dpd2bid.c 290 UINT64 exp, BL, d109;
324 BL = bcoeff.w[0] - BH.w[0] * 1000000000000000000ull;
329 __mul_64x64_to_128 (BT2, BL, d109);
331 BLL32 = (unsigned int) BL - BLH32 * 1000000000;
  /src/external/gpl3/gcc.old/dist/libdecnumber/bid/
bid2dpd_dpd2bid.c 290 UINT64 exp, BL, d109;
324 BL = bcoeff.w[0] - BH.w[0] * 1000000000000000000ull;
329 __mul_64x64_to_128 (BT2, BL, d109);
331 BLL32 = (unsigned int) BL - BLH32 * 1000000000;
  /src/external/gpl3/gdb/dist/libdecnumber/bid/
bid2dpd_dpd2bid.c 288 UINT64 exp, BL, d109;
308 BL = bcoeff.w[0] - BH.w[0] * 1000000000000000000ull;
313 __mul_64x64_to_128 (BT2, BL, d109);
315 BLL32 = (unsigned int) BL - BLH32 * 1000000000;
  /src/external/gpl3/gdb.old/dist/libdecnumber/bid/
bid2dpd_dpd2bid.c 288 UINT64 exp, BL, d109;
308 BL = bcoeff.w[0] - BH.w[0] * 1000000000000000000ull;
313 __mul_64x64_to_128 (BT2, BL, d109);
315 BLL32 = (unsigned int) BL - BLH32 * 1000000000;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 90 {codeview::RegisterId::BL, X86::BL},
633 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
645 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
646 return X86::BL;
682 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
718 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
754 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
  /src/external/gpl3/gcc/dist/libgcc/config/sh/
crt1.S 223 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
233 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
239 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
  /src/external/gpl3/gcc.old/dist/libgcc/config/sh/
crt1.S 223 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
233 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
239 ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.h 32 BL,

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