| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/ |
| AVRELFStreamer.cpp | 12 static unsigned getEFlagsForFeatureSet(const FeatureBitset &Features) {
16 if (Features[AVR::ELFArchAVR1])
18 else if (Features[AVR::ELFArchAVR2])
20 else if (Features[AVR::ELFArchAVR25])
22 else if (Features[AVR::ELFArchAVR3])
24 else if (Features[AVR::ELFArchAVR31])
26 else if (Features[AVR::ELFArchAVR35])
28 else if (Features[AVR::ELFArchAVR4])
30 else if (Features[AVR::ELFArchAVR5])
32 else if (Features[AVR::ELFArchAVR51]
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Basic/Targets/ |
| AMDGPU.cpp | 179 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
192 Features["ci-insts"] = true;
193 Features["dot1-insts"] = true;
194 Features["dot2-insts"] = true;
195 Features["dot5-insts"] = true;
196 Features["dot6-insts"] = true;
197 Features["dot7-insts"] = true;
198 Features["dl-insts"] = true;
199 Features["flat-address-space"] = true;
200 Features["16-bit-insts"] = true
[all...] |
| PPC.cpp | 30 /// configured set of features.
31 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
34 for (const auto &Feature : Features) {
277 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
279 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
294 Features["power9-vector"] = (CPU == "pwr9");
295 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
300 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
305 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
311 Features["extdiv"] = llvm::StringSwitch<bool>(CPU
[all...] |
| WebAssembly.cpp | 95 void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap<bool> &Features,
100 Features["simd128"] = true;
111 Features["simd128"] = false;
116 void WebAssemblyTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
120 setSIMDLevel(Features, SIMD128, Enabled);
122 Features[Name] = Enabled;
126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
129 Features["nontrapping-fptoint"] = true;
130 Features["sign-ext"] = true;
131 Features["bulk-memory"] = true
[all...] |
| SystemZ.h | 99 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
104 Features["transactional-execution"] = true;
106 Features["vector"] = true;
108 Features["vector-enhancements-1"] = true;
110 Features["vector-enhancements-2"] = true;
111 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
114 bool handleTargetFeatures(std::vector<std::string> &Features,
119 for (const auto &Feature : Features) {
|
| BPF.cpp | 50 bool BPFTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
52 for (const auto &Feature : Features) {
|
| Hexagon.cpp | 96 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
99 Features["audio"] = true;
105 Features[CPUFeature] = true;
107 Features["long-calls"] = false;
109 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
112 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
114 for (auto &F : Features) {
|
| /src/external/apache2/llvm/dist/clang/lib/Driver/ToolChains/Arch/ |
| AArch64.cpp | 66 // Decode AArch64 features from string like +[no]featureA+[no]featureB+...
68 std::vector<StringRef> &Features,
76 Features.push_back(FeatureName);
86 Features.push_back("+f32mm");
94 std::vector<StringRef> &Features) {
103 Features.push_back("+neon");
106 if (!llvm::AArch64::getArchFeatures(ArchKind, Features))
110 if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
115 !DecodeAArch64Features(D, Split.second, Features, ArchKind))
124 std::vector<StringRef> &Features) {
[all...] |
| RISCV.cpp | 170 // Set the hardware features for the extensions that are supported.
173 std::vector<StringRef> &Features,
249 // Set target features.
250 // TODO: Hardware features to be handled in Support/TargetParser.cpp.
251 // TODO: Use version number when setting target features.
262 Features.push_back("+experimental-v");
263 Features.push_back("+experimental-zvamo");
264 Features.push_back("+experimental-zvlsseg");
266 Features.push_back(Args.MakeArgString("+experimental-" + Ext));
268 Features.push_back(Args.MakeArgString("+" + Ext))
[all...] |
| M68k.cpp | 70 std::vector<StringRef> &Features) {
74 Features.push_back("-hard-float");
78 Features.push_back("+reserve-a0");
80 Features.push_back("+reserve-a1");
82 Features.push_back("+reserve-a2");
84 Features.push_back("+reserve-a3");
86 Features.push_back("+reserve-a4");
88 Features.push_back("+reserve-a5");
90 Features.push_back("+reserve-a6");
92 Features.push_back("+reserve-d0")
[all...] |
| VE.cpp | 22 std::vector<StringRef> &Features) {}
|
| X86.cpp | 33 // FIXME: We should also incorporate the detected target features for use
112 std::vector<StringRef> &Features) {
119 Features.push_back(
125 // x86_64h implies quite a few of the more modern subtarget features
127 Features.push_back("-rdrnd");
128 Features.push_back("-aes");
129 Features.push_back("-pclmul");
130 Features.push_back("-rtm");
131 Features.push_back("-fsgsbase");
135 // Add features to be compatible with gcc for Android
[all...] |
| SystemZ.cpp | 55 std::vector<llvm::StringRef> &Features) {
59 Features.push_back("+transactional-execution");
61 Features.push_back("-transactional-execution");
66 Features.push_back("+vector");
68 Features.push_back("-vector");
73 Features.push_back("+soft-float");
|
| VE.h | 24 std::vector<llvm::StringRef> &Features);
|
| Mips.cpp | 193 std::vector<StringRef> &Features) {
262 Features.push_back("+noabicalls");
264 Features.push_back("-noabicalls");
269 Features.push_back("-long-calls");
271 Features.push_back("+long-calls");
278 Features.push_back("+xgot");
280 Features.push_back("-xgot");
288 Features.push_back("+soft-float");
295 Features.push_back("+nan2008");
297 Features.push_back("-nan2008")
[all...] |
| ARM.cpp | 68 std::vector<StringRef> &Features) {
70 if (!llvm::ARM::getHWDivFeatures(HWDivID, Features))
77 std::vector<StringRef> &Features) {
79 if (!llvm::ARM::getFPUFeatures(FPUID, Features))
84 // Decode ARM features from string like +[no]featureA+[no]featureB+...
87 std::vector<StringRef> &Features,
93 if (!appendArchExtFeatures(CPU, ArchKind, Feature, Features, ArgFPUID))
100 std::vector<StringRef> &Features) {
105 llvm::ARM::getExtensionFeatures(Extension, Features);
114 std::vector<StringRef> &Features,
[all...] |
| AArch64.h | 25 std::vector<llvm::StringRef> &Features);
|
| X86.h | 29 std::vector<llvm::StringRef> &Features);
|
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| AArch64TargetParser.cpp | 1 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
9 // This file implements a target parser to recognise AArch64 hardware features
63 std::vector<StringRef> &Features) {
68 Features.push_back("+fp-armv8");
70 Features.push_back("+neon");
72 Features.push_back("+crc");
74 Features.push_back("+crypto");
76 Features.push_back("+dotprod");
78 Features.push_back("+fp16fml");
80 Features.push_back("+fullfp16")
[all...] |
| Host.cpp | 307 // Look for the CPU features.
310 if (Lines[I].startswith("features")) {
571 // Read control register 0 (XCR0). Used to detect features such as AVX.
604 const unsigned *Features,
607 return (Features[F / 32] & (1U << (F % 32))) != 0;
885 const unsigned *Features,
888 return (Features[F / 32] & (1U << (F % 32))) != 0;
1005 unsigned *Features) {
1009 Features[F / 32] |= 1U << (F % 32);
1145 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Object/ |
| ELFObjectFile.cpp | 101 SubtargetFeatures Features;
108 Features.AddFeature("mips2");
111 Features.AddFeature("mips3");
114 Features.AddFeature("mips4");
117 Features.AddFeature("mips5");
120 Features.AddFeature("mips32");
123 Features.AddFeature("mips64");
126 Features.AddFeature("mips32r2");
129 Features.AddFeature("mips64r2");
132 Features.AddFeature("mips32r6")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| SubtargetFeature.cpp | 42 // Don't add empty features.
45 Features.push_back(hasFlag(String) ? String.lower()
50 // Break up string into separate features
51 Split(Features, Initial);
55 return join(Features.begin(), Features.end(), ",");
59 for (auto &F : Features)
71 // FIXME: This is an inelegant way of specifying the features of a
|
| /src/external/apache2/llvm/dist/clang/lib/Basic/ |
| TargetID.cpp | 27 auto Features = T.isAMDGCN() ? llvm::AMDGPU::getArchAttrAMDGCN(ProcKind)
29 if (Features & llvm::AMDGPU::FEATURE_SRAMECC)
31 if (Features & llvm::AMDGPU::FEATURE_XNACK)
60 // name or features are valid for the processor.
62 // A target ID is a processor name followed by a list of target features
78 auto Features = Split.second;
79 if (Features.empty())
86 while (!Features.empty()) {
87 auto Splits = Features.split(':');
98 Features = Splits.second
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/PDB/Native/ |
| InfoStream.cpp | 70 Features |= PdbFeatureContainsIdStream;
73 Features |= PdbFeatureNoTypeMerging;
76 Features |= PdbFeatureMinimalDebugInfo;
100 return !!(Features & PdbFeatureContainsIdStream);
119 PdbRaw_Features InfoStream::getFeatures() const { return Features; }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyTargetMachine.cpp | 167 Attribute FSAttr = F.getFnAttribute("target-features");
185 // Take the union of all features used in the module and use it for each
197 FeatureBitset Features = coalesceFeatures(M);
199 std::string FeatureStr = getFeatureString(Features);
207 if (!Features[WebAssembly::FeatureAtomics])
210 if (!Features[WebAssembly::FeatureBulkMemory])
218 recordFeatures(M, Features, StrippedAtomics || StrippedTLS);
226 FeatureBitset Features =
232 Features |= WasmTM->getSubtargetImpl(F)->getFeatureBits();
233 return Features;
[all...] |
