| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyOptimizeLiveIntervals.cpp | 75 auto &LIS = getAnalysis<LiveIntervals>();
91 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
112 LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
113 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
114 LIS.RemoveMachineInstrFromMaps(*MI);
|
| WebAssemblyMemIntrinsicResults.cpp | 88 LiveIntervals &LIS) {
91 LiveInterval *FromLI = &LIS.getInterval(FromReg);
92 LiveInterval *ToLI = &LIS.getInterval(ToReg);
94 SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot();
109 SlotIndex WhereIdx = LIS.getInstructionIndex(*Where);
134 LIS.extendToIndices(*ToLI, Indices);
137 LIS.shrinkToUses(FromLI);
151 MachineDominatorTree &MDT, LiveIntervals &LIS,
174 return replaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS);
189 auto &LIS = getAnalysis<LiveIntervals>()
[all...] |
| WebAssemblyRegStackify.cpp | 103 LiveIntervals &LIS) {
268 const LiveIntervals &LIS) {
273 // MRI doesn't know what the Def is. Try asking LIS.
274 if (const VNInfo *ValNo = LIS.getInterval(Reg).getVNInfoBefore(
275 LIS.getInstructionIndex(*Insert)))
276 return LIS.getInstructionFromIndex(ValNo->def);
285 MachineDominatorTree &MDT, LiveIntervals &LIS) {
291 const LiveInterval &LI = LIS.getInterval(Reg);
293 LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot());
296 const auto &Result = LI.Query(LIS.getInstructionIndex(*I.getParent()))
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| CalcSpillWeights.h | 48 LiveIntervals &LIS;
58 VirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS,
61 : MF(MF), LIS(LIS), VRM(VRM), Loops(Loops), MBFI(MBFI) {}
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIOptimizeExecMaskingPreRA.cpp | 33 LiveIntervals *LIS;
91 LiveIntervals *LIS, Register Reg,
93 SlotIndex AndIdx = LIS->getInstructionIndex(And);
94 SlotIndex SelIdx = LIS->getInstructionIndex(Sel);
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx);
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx))
133 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS);
149 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);
163 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS);
182 if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And)
[all...] |
| GCNRegPressure.h | 112 const LiveIntervals &LIS;
118 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
150 // filling live regs upon this point using LIS
157 // to reported by LIS
173 // filling live regs upon this point using LIS.
198 const LiveIntervals &LIS,
202 const LiveIntervals &LIS,
212 getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
215 auto &SII = *LIS.getSlotIndexes();
227 if (!LIS.hasInterval(Reg)
[all...] |
| SILowerControlFlow.cpp | 71 LiveIntervals *LIS = nullptr;
264 if (!LIS) {
269 LIS->InsertMachineInstrInMaps(*CopyExec);
273 LIS->ReplaceMachineInstrInMaps(MI, *And);
276 LIS->InsertMachineInstrInMaps(*Xor);
277 LIS->InsertMachineInstrInMaps(*SetExec);
278 LIS->InsertMachineInstrInMaps(*NewBr);
280 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
286 LIS->removeInterval(SaveExecReg);
287 LIS->createAndComputeVirtRegInterval(SaveExecReg)
[all...] |
| GCNIterativeScheduler.cpp | 47 const LiveIntervals *LIS,
56 if (!I->isDebugInstr() && LIS)
57 OS << LIS->getInstructionIndex(*I);
63 if (!I->isDebugInstr() && LIS)
64 OS << LIS->getInstructionIndex(*I);
69 if (LIS) OS << LIS->getInstructionIndex(*End) << '\t';
78 const LiveIntervals *LIS) {
82 const auto LiveIns = getLiveRegsBefore(*Begin, *LIS);
87 const auto LiveOuts = getLiveRegsAfter(*BottomMI, *LIS);
[all...] |
| GCNRegPressure.cpp | 24 const LiveIntervals &LIS,
27 << *LIS.getInstructionFromIndex(SI);
31 if (!LIS.hasInterval(Reg))
33 const auto &LI = LIS.getInterval(Reg);
193 // use mask has been tracked before using LIS.
201 const LiveIntervals &LIS) {
211 // For a tentative schedule LIS isn't updated yet but livemask should remain
214 auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
215 return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
219 collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS,
[all...] |
| SIWholeQuadMode.cpp | 158 LiveIntervals *LIS;
320 LiveQueryResult UseLRQ = LR.Query(LIS->getInstructionIndex(UseMI));
360 const MachineBasicBlock *MBB = LIS->getMBBFromIndex(Value->def);
368 if (const VNInfo *VN = LR.getVNInfoBefore(LIS->getMBBEndIdx(*PI))) {
378 MachineInstr *MI = LIS->getInstructionFromIndex(Value->def);
404 LiveQueryResult LRQ = LR.Query(LIS->getInstructionIndex(*MI));
451 LiveRange &LR = LIS->getInterval(Reg);
459 LiveRange &LR = LIS->getRegUnit(*RegUnit);
460 const VNInfo *Value = LR.Query(LIS->getInstructionIndex(MI)).valueIn();
727 LIS->InsertMachineInstrInMaps(*Save)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
46 LiveInterval &OldLI = LIS.getInterval(OldReg);
47 VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
66 LIS.getInterval(VReg).markNotSpillable();
86 LiveInterval &OrigLI = LIS.getInterval(Original);
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
123 LiveInterval &li = LIS.getInterval(MO.getReg());
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
177 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
182 LIS.removeInterval(Reg)
[all...] |
| PHIElimination.cpp | 70 LiveIntervals *LIS;
151 LIS = getAnalysisIfAvailable<LiveIntervals>();
156 if (!DisableEdgeSplitting && (LV || LIS)) {
205 if (LIS)
206 LIS->RemoveMachineInstrFromMaps(*DefMI);
213 if (LIS)
214 LIS->RemoveMachineInstrFromMaps(*I.first);
379 if (LIS) {
380 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy);
382 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB)
[all...] |
| RegAllocBase.cpp | 57 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
62 LIS = &lis;
78 enqueue(&LIS->getInterval(Reg));
95 LIS->removeInterval(VirtReg->reg());
150 assert(LIS->hasInterval(Reg));
152 LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
158 LIS->removeInterval(SplitVirtReg->reg());
173 LIS->RemoveMachineInstrFromMaps(*DeadInst);
|
| CalcSpillWeights.cpp | 41 calculateSpillWeightAndHint(LIS.getInterval(Reg));
80 static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS,
93 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
113 const LiveInterval &SrcLI = LIS.getInterval(Reg);
119 MI = LIS.getInstructionFromIndex(VNI->def);
123 if (!TII.isTriviallyReMaterializable(*MI, LIS.getAliasAnalysis()))
169 const LiveInterval &OrigInt = LIS.getInterval(Original);
186 MachineBasicBlock *localMBB = LIS.getMBBFromIndex(*End);
187 assert(localMBB == LIS.getMBBFromIndex(*Start) &&
226 SlotIndex SI = LIS.getInstructionIndex(*MI)
[all...] |
| RenameIndependentSubregs.cpp | 72 SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR,
74 : ConEQ(LIS), SR(&SR), Index(Index) {}
104 LiveIntervals *LIS;
143 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
162 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents));
189 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
223 SlotIndex Pos = LIS->getInstructionIndex(*MI);
271 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
303 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
304 const SlotIndexes &Indexes = *LIS->getSlotIndexes()
[all...] |
| RegAllocPBQP.cpp | 162 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
169 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
181 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
184 void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
193 LiveIntervals &LIS = G.getMetadata().LIS;
201 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight();
310 LiveIntervals &LIS = G.getMetadata().LIS;
334 LiveInterval &LI = LIS.getInterval(VReg)
[all...] |
| InlineSpiller.cpp | 88 LiveIntervals &LIS;
142 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
150 IPA(LIS, mf.getNumBlockIDs()) {}
161 LiveIntervals &LIS;
202 : MF(MF), LIS(Pass.getAnalysis<LiveIntervals>()),
276 static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
280 LIS.getInterval(MO.getReg());
297 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
350 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
387 SlotIndex Idx = LIS.getInstructionIndex(CopyMI)
[all...] |
| LiveDebugVariables.cpp | 310 ArrayRef<unsigned> SpillOffsets, LiveIntervals &LIS,
318 LiveIntervals &LIS);
443 /// \param LIS Live intervals analysis.
448 LiveIntervals &LIS);
464 MachineRegisterInfo &MRI, LiveIntervals &LIS);
469 LiveIntervals &LIS, LexicalScopes &LS);
474 LiveIntervals &LIS);
485 void emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
506 LiveIntervals &LIS, const TargetInstrInfo &TII,
521 void emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII
[all...] |
| LiveDebugVariables.h | 45 LiveIntervals &LIS);
|
| SplitKit.cpp | 59 InsertPointAnalysis::InsertPointAnalysis(const LiveIntervals &lis,
61 : LIS(lis), LastInsertPoint(BBNum) {}
68 SlotIndex MBBEnd = LIS.getMBBEndIdx(&MBB);
87 LIP.first = LIS.getInstructionIndex(*FirstTerm);
100 LIP.second = LIS.getInstructionIndex(MI);
112 return LIS.isLiveInToMBB(CurLI, EHPad);
124 if (auto *I = LIS.getInstructionFromIndex(LIP.second))
144 if (LIP == LIS.getMBBEndIdx(&MBB))
146 return LIS.getInstructionFromIndex(LIP)
[all...] |
| RegisterCoalescer.cpp | 131 LiveIntervals *LIS = nullptr;
338 if (LIS->shrinkToUses(LI, Dead)) {
342 LIS->splitSeparateComponents(*LI, SplitLIs);
352 LIS->RemoveMachineInstrFromMaps(*MI);
589 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS,
604 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
606 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
607 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
643 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
657 LIS->getInstructionFromIndex(ValS->end.getPrevSlot())
[all...] |
| TwoAddressInstructionPass.cpp | 98 LiveIntervals *LIS;
200 static bool isPlainlyKilled(MachineInstr *MI, Register Reg, LiveIntervals *LIS);
290 LiveIntervals *LIS) {
291 if (LIS && Reg.isVirtual() && !LIS->isNotInMIMap(*MI)) {
298 LiveInterval &LI = LIS->getInterval(Reg);
304 SlotIndex useIdx = LIS->getInstructionIndex(*MI);
332 LiveIntervals *LIS, bool allowFalsePositives) {
338 if (!isPlainlyKilled(DefMI, Reg, LIS))
463 if (!isPlainlyKilled(MI, RegC, LIS))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 67 LiveIntervals *LIS;
109 SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
118 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill()
213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
281 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg);
299 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
308 LIS->getVNInfoAllocator())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TileConfig.cpp | 84 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
171 LIS.InsertMachineInstrInMaps(*NewMI);
186 SlotIndex SIdx = LIS.InsertMachineInstrInMaps(*NewMI);
187 LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()});
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 169 LiveIntervals *LIS = nullptr;
319 MachineInstr *MI = LIS->getInstructionFromIndex(K);
335 LiveInterval &LI = LIS->getInterval(Reg);
343 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
420 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
427 LiveInterval &LI = LIS->getInterval(Reg);
428 LI.computeSubRangeUndefs(Undefs, LM, *MRI, *LIS->getSlotIndexes());
431 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
432 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI);
443 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI)
[all...] |
