| /src/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/tests/ |
| sanitizer_ring_buffer_test.cc | 37 RingBuffer<T> *RB;
40 RB = RingBuffer<T>::New(Size);
41 EXPECT_EQ(RB->size(), Size);
42 RB->Delete();
45 RB = RingBuffer<T>::New(4);
46 EXPECT_EQ(RB->size(), 4U);
48 EXPECT_EQ((int64_t)(*RB)[0], (int64_t)a0); \
49 EXPECT_EQ((int64_t)(*RB)[1], (int64_t)a1); \
50 EXPECT_EQ((int64_t)(*RB)[2], (int64_t)a2); \
51 EXPECT_EQ((int64_t)(*RB)[3], (int64_t)a3)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/microblaze/ |
| microblaze.isa | 31 CARRY = C_calc(RA, RB, 0);
32 RD = RA + RB;
39 CARRY = C_calc(RB, ~RA, 1);
40 RD = RB + ~RA + 1;
47 CARRY = C_calc(RA, RB, C_rd);
48 RD = RA + RB + C_rd;
55 CARRY = C_calc(RB, ~RA, C_rd);
56 RD = RB + ~RA + C_rd;
63 RD = RA + RB;
69 RD = RB + ~RA + 1
[all...] |
| /src/external/gpl3/gdb/dist/sim/microblaze/ |
| microblaze.isa | 31 CARRY = C_calc(RA, RB, 0);
32 RD = RA + RB;
39 CARRY = C_calc(RB, ~RA, 1);
40 RD = RB + ~RA + 1;
47 CARRY = C_calc(RA, RB, C_rd);
48 RD = RA + RB + C_rd;
55 CARRY = C_calc(RB, ~RA, C_rd);
56 RD = RB + ~RA + C_rd;
63 RD = RA + RB;
69 RD = RB + ~RA + 1
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
1661 /* The RS and RB fields in an X form instruction when they must be the same.
1681 int64_t rb = (insn >> 11) & 0x1f; local
1683 if (rs != rb)
1688 /* The RB field in an lswx instruction, which has special value
2903 /* The RA and RB fields in a VX form instruction when they must be the same.
3451 /* The RB field in an X, XO, M, or MDS form instruction. */
3452 #define RB RAOPT + 1
3456 /* The RS and RB fields in an X form instruction when they must be the same.
3458 #define RSB RB +
[all...] |
| arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}
[all...] |
| arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC }
31 #define ARG_32BIT_ZARBRC { ZA, RB, RC }
32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC }
33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM
[all...] |
| arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }},
95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }},
98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }},
101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }},
113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }}
[all...] |
| or1k-opc.c | 235 /* l.jr $rB */
238 { { MNEM, ' ', OP (RB), 0 } },
241 /* l.jalr $rB */
244 { { MNEM, ' ', OP (RB), 0 } },
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
373 /* l.sw ${simm16-split}($rA),$rB */
376 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
379 /* l.sb ${simm16-split}($rA),$rB */
382 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
1661 /* The RS and RB fields in an X form instruction when they must be the same.
1681 int64_t rb = (insn >> 11) & 0x1f; local
1683 if (rs != rb)
1688 /* The RB field in an lswx instruction, which has special value
2903 /* The RA and RB fields in a VX form instruction when they must be the same.
3451 /* The RB field in an X, XO, M, or MDS form instruction. */
3452 #define RB RAOPT + 1
3456 /* The RS and RB fields in an X form instruction when they must be the same.
3458 #define RSB RB +
[all...] |
| arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}
[all...] |
| arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC }
31 #define ARG_32BIT_ZARBRC { ZA, RB, RC }
32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC }
33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM
[all...] |
| arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }},
95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }},
98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }},
101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }},
113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }}
[all...] |
| or1k-opc.c | 235 /* l.jr $rB */
238 { { MNEM, ' ', OP (RB), 0 } },
241 /* l.jalr $rB */
244 { { MNEM, ' ', OP (RB), 0 } },
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
373 /* l.sw ${simm16-split}($rA),$rB */
376 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
379 /* l.sb ${simm16-split}($rA),$rB */
382 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
1615 /* The RS and RB fields in an X form instruction when they must be the same.
1635 int64_t rb = (insn >> 11) & 0x1f; local
1637 if (rs != rb)
1642 /* The RB field in an lswx instruction, which has special value
2835 /* The RA and RB fields in a VX form instruction when they must be the same.
3373 /* The RB field in an X, XO, M, or MDS form instruction. */
3374 #define RB RAOPT + 1
3378 /* The RS and RB fields in an X form instruction when they must be the same.
3380 #define RSB RB +
[all...] |
| arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}
[all...] |
| arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC }
31 #define ARG_32BIT_ZARBRC { ZA, RB, RC }
32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC }
33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM
[all...] |
| arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }},
95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }},
98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }},
101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }},
113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }}
[all...] |
| or1k-opc.c | 235 /* l.jr $rB */
238 { { MNEM, ' ', OP (RB), 0 } },
241 /* l.jalr $rB */
244 { { MNEM, ' ', OP (RB), 0 } },
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
373 /* l.sw ${simm16-split}($rA),$rB */
376 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
379 /* l.sb ${simm16-split}($rA),$rB */
382 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
1661 /* The RS and RB fields in an X form instruction when they must be the same.
1681 int64_t rb = (insn >> 11) & 0x1f; local
1683 if (rs != rb)
1688 /* The RB field in an lswx instruction, which has special value
2903 /* The RA and RB fields in a VX form instruction when they must be the same.
3451 /* The RB field in an X, XO, M, or MDS form instruction. */
3452 #define RB RAOPT + 1
3456 /* The RS and RB fields in an X form instruction when they must be the same.
3458 #define RSB RB +
[all...] |
| arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }},
47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }},
77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }},
83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }},
98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}
[all...] |
| arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC }
31 #define ARG_32BIT_ZARBRC { ZA, RB, RC }
32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC }
33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
42 #define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM
[all...] |
| arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }},
95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }},
98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }},
101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }},
113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }}
[all...] |
| /src/external/bsd/flex/dist/examples/manual/ |
| expr.lex | 26 ")" return(RB);
|
| expr.y | 19 %token LB RB
42 | LB exp RB { $$ = $2; }
|
| /src/external/apache2/llvm/dist/clang/lib/Rewrite/ |
| HTMLRewrite.cpp | 58 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E,
62 RB.InsertTextAfter(B, StartTag);
63 RB.InsertTextBefore(E, EndTag);
77 RB.InsertTextBefore(LastNonWhiteSpace+1, EndTag);
96 RB.InsertTextAfter(i, StartTag);
116 RewriteBuffer &RB = R.getEditBuffer(FID);
129 RB.ReplaceText(FilePos, 1, " ");
133 RB.ReplaceText(FilePos, 1, "<hr>");
142 RB.ReplaceText(FilePos, 1,
146 RB.ReplaceText(FilePos, 1, StringRef(" ", NumSpaces))
[all...] |
