| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clock_source.h | 74 SRII(PIXEL_RATE_CNTL, OTG, 0),\
75 SRII(PIXEL_RATE_CNTL, OTG, 1),\
76 SRII(PIXEL_RATE_CNTL, OTG, 2),\
77 SRII(PIXEL_RATE_CNTL, OTG, 3),\
78 SRII(PIXEL_RATE_CNTL, OTG, 4),\
79 SRII(PIXEL_RATE_CNTL, OTG, 5)
91 SRII(PIXEL_RATE_CNTL, OTG, 0),\
92 SRII(PIXEL_RATE_CNTL, OTG, 1),\
93 SRII(PIXEL_RATE_CNTL, OTG, 2),\
94 SRII(PIXEL_RATE_CNTL, OTG, 3
[all...] |
| dce_hwseq.h | 182 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
183 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
184 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
185 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
217 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
218 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
219 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
220 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
221 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
222 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5),
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_optc.h | 37 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
38 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
39 SRI(OTG_VREADY_PARAM, OTG, inst),\
40 SRI(OTG_BLANK_CONTROL, OTG, inst),\
41 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
42 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
43 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
44 SRI(OTG_H_TOTAL, OTG, inst),\
45 SRI(OTG_H_BLANK_START_END, OTG, inst),\
46 SRI(OTG_H_SYNC_A, OTG, inst),
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_optc.h | 35 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
36 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
37 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
38 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
39 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
40 SRI(OTG_DSC_START_POSITION, OTG, inst),\
46 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 235 IRQ_REG_ENTRY(OTG, reg_num,\
243 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 239 IRQ_REG_ENTRY(OTG, reg_num,\
247 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 232 IRQ_REG_ENTRY(OTG, reg_num,\
240 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/ |
| ulcb-kf.dtsi | 69 dr_mode = "otg";
82 dr_mode = "otg";
168 otg-extlpn-hog {
172 line-name = "OTG EXTLPn";
175 otg-offvbusn-hog {
179 line-name = "OTG OFFVBUSn";
240 dr_mode = "otg";
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/ingenic/ |
| gcw0.dts | 256 /* USB OTG */
367 * USB OTG is not yet working reliably, the ID detection
369 * Until this is fixed, disable OTG by not providing the
413 pins_otg: otg {
414 otg-vbus-pin {
415 function = "otg";
416 groups = "otg-vbus";
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| qcom-apq8064-cm-qs600.dts | 153 /* OTG */
156 dr_mode = "otg";
|
| qcom-apq8064-asus-nexus7-flo.dts | 86 /* msm otg HSUSB_VDDCX */
324 /* OTG */
327 dr_mode = "otg";
|
| qcom-apq8064-ifc6410.dts | 247 /* OTG */
250 dr_mode = "otg";
|
| sun8i-h2-plus-bananapi-m2-zero.dts | 259 dr_mode = "otg";
267 * OTG. The Vbus of these two connectors are connected together, so
|
| motorola-mapphone-common.dtsi | 670 /* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
|
| exynos4412-p4note.dtsi | 430 /* USB OTG */
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8mm-var-som-symphony.dts | 90 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
|
| imx8mn-var-som-symphony.dts | 80 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
|
| imx8mq-pico-pi.dts | 29 reg_usb_otg_vbus: regulator-usb-otg-vbus {
297 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
|
| imx8mm-nitrogen-r2.dts | 365 /* USB OTG port */
367 dr_mode = "otg";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/ |
| meson-gxbb-odroidc2.dts | 296 "USB HUB nRESET", "USB OTG Power En",
|
