1 /* $NetBSD: meson_dwmac.c,v 1.17 2026/06/22 20:26:34 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.17 2026/06/22 20:26:34 jakllsch Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 #include <dev/fdt/dwc_gmac_fdt_subr.h> 52 53 #define PRG_ETHERNET_ADDR0 0x00 54 #define CLKGEN_ENABLE __BIT(12) 55 #define RMII_CLK_I_INVERTED __BIT(11) 56 #define PHY_CLK_ENABLE __BIT(10) 57 #define MP2_CLK_OUT_DIV __BITS(9,7) 58 #define TX_CLK_DELAY __BITS(6,5) 59 #define PHY_INTERFACE_SEL __BIT(0) 60 61 static const struct device_compatible_entry compat_data[] = { 62 { .compat = "amlogic,meson8b-dwmac" }, 63 { .compat = "amlogic,meson-gx-dwmac" }, 64 { .compat = "amlogic,meson-gxbb-dwmac" }, 65 { .compat = "amlogic,meson-axg-dwmac" }, 66 DEVICE_COMPAT_EOL 67 }; 68 69 static int 70 meson_dwmac_reset_eth(const int phandle) 71 { 72 struct fdtbus_gpio_pin *pin_reset; 73 const u_int *reset_delay_us; 74 bool reset_active_low; 75 int len, val; 76 77 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", 78 GPIO_PIN_OUTPUT); 79 if (pin_reset == NULL) 80 return ENXIO; 81 82 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 83 if (reset_delay_us == NULL || len != 12) 84 return ENXIO; 85 86 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 87 88 val = reset_active_low ? 1 : 0; 89 90 fdtbus_gpio_write(pin_reset, val); 91 delay(be32toh(reset_delay_us[0])); 92 fdtbus_gpio_write(pin_reset, !val); 93 delay(be32toh(reset_delay_us[1])); 94 fdtbus_gpio_write(pin_reset, val); 95 delay(be32toh(reset_delay_us[2])); 96 97 return 0; 98 } 99 100 static int 101 meson_dwmac_reset_phy(const int phandle) 102 { 103 struct fdtbus_gpio_pin *pin_reset; 104 const u_int *reset_assert_us, *reset_deassert_us, *reset_gpios; 105 bool reset_active_low; 106 int len, val; 107 108 pin_reset = fdtbus_gpio_acquire(phandle, "reset-gpios", 109 GPIO_PIN_OUTPUT); 110 if (pin_reset == NULL) 111 return ENXIO; 112 113 reset_assert_us = fdtbus_get_prop(phandle, "reset-assert-us", &len); 114 if (reset_assert_us == NULL || len != 4) 115 return ENXIO; 116 reset_deassert_us = fdtbus_get_prop(phandle, "reset-deassert-us", &len); 117 if (reset_deassert_us == NULL || len != 4) 118 return ENXIO; 119 reset_gpios = fdtbus_get_prop(phandle, "reset-gpios", &len); 120 if (reset_gpios == NULL || len != 12) 121 return ENXIO; 122 123 reset_active_low = be32toh(reset_gpios[2]); 124 125 val = reset_active_low ? 1 : 0; 126 127 fdtbus_gpio_write(pin_reset, val); 128 delay(be32toh(reset_assert_us[0])); 129 fdtbus_gpio_write(pin_reset, !val); 130 delay(be32toh(reset_deassert_us[0])); 131 132 return 0; 133 } 134 135 static void 136 meson_dwmac_set_mode_rgmii(int phandle, bus_space_tag_t bst, 137 bus_space_handle_t bsh, struct clk *clkin) 138 { 139 u_int tx_delay; 140 uint32_t val; 141 142 #define DIV_ROUND_OFF(x, y) (((x) + (y) / 2) / (y)) 143 const u_int div = DIV_ROUND_OFF(clk_get_rate(clkin), 250000000); 144 145 if (of_getprop_uint32(phandle, "amlogic,tx-delay-ns", &tx_delay) != 0) 146 tx_delay = 2; 147 148 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 149 val |= PHY_INTERFACE_SEL; 150 val &= ~TX_CLK_DELAY; 151 val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY); 152 val &= ~MP2_CLK_OUT_DIV; 153 val |= __SHIFTIN(div, MP2_CLK_OUT_DIV); 154 val |= PHY_CLK_ENABLE; 155 val |= CLKGEN_ENABLE; 156 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 157 } 158 159 static void 160 meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst, 161 bus_space_handle_t bsh) 162 { 163 uint32_t val; 164 165 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 166 val &= ~PHY_INTERFACE_SEL; 167 val |= RMII_CLK_I_INVERTED; 168 val &= ~TX_CLK_DELAY; 169 val |= CLKGEN_ENABLE; 170 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 171 } 172 173 static int 174 meson_dwmac_intr(void *arg) 175 { 176 struct dwc_gmac_softc * const sc = arg; 177 178 return dwc_gmac_intr(sc); 179 } 180 181 static int 182 meson_dwmac_match(device_t parent, cfdata_t cf, void *aux) 183 { 184 struct fdt_attach_args * const faa = aux; 185 186 return of_compatible_match(faa->faa_phandle, compat_data); 187 } 188 189 static void 190 meson_dwmac_attach(device_t parent, device_t self, void *aux) 191 { 192 struct dwc_gmac_softc * const sc = device_private(self); 193 struct fdt_attach_args * const faa = aux; 194 const int phandle = faa->faa_phandle; 195 int miiclk, phandle_phy, phy = MII_PHY_ANY; 196 u_int miiclk_rate; 197 bus_space_handle_t prgeth_bsh; 198 struct fdtbus_reset *rst_gmac; 199 struct clk *clk_gmac, *clk_in[2]; 200 const char *phy_mode; 201 char intrstr[128]; 202 bus_addr_t addr[2]; 203 bus_size_t size[2]; 204 205 if (fdtbus_get_reg(phandle, 0, &addr[0], &size[0]) != 0 || 206 fdtbus_get_reg(phandle, 1, &addr[1], &size[1]) != 0) { 207 aprint_error(": couldn't get registers\n"); 208 return; 209 } 210 211 sc->sc_dev = self; 212 sc->sc_bst = faa->faa_bst; 213 if (bus_space_map(sc->sc_bst, addr[0], size[0], 0, &sc->sc_bsh) != 0 || 214 bus_space_map(sc->sc_bst, addr[1], size[1], 0, &prgeth_bsh) != 0) { 215 aprint_error(": couldn't map registers\n"); 216 return; 217 } 218 sc->sc_dmat = faa->faa_dmat; 219 220 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 221 aprint_error(": failed to decode interrupt\n"); 222 return; 223 } 224 225 clk_gmac = fdtbus_clock_get(phandle, "stmmaceth"); 226 clk_in[0] = fdtbus_clock_get(phandle, "clkin0"); 227 clk_in[1] = fdtbus_clock_get(phandle, "clkin1"); 228 if (clk_gmac == NULL || clk_in[0] == NULL || clk_in[1] == NULL) { 229 aprint_error(": couldn't get clocks\n"); 230 return; 231 } 232 233 rst_gmac = fdtbus_reset_get(phandle, "stmmaceth"); 234 235 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 236 if (phy_mode == NULL) { 237 aprint_error(": missing 'phy-mode' property\n"); 238 return; 239 } 240 phandle_phy = fdtbus_get_phandle(phandle, "phy-handle"); 241 if (phandle_phy > 0) { 242 of_getprop_uint32(phandle_phy, "reg", &phy); 243 } else { 244 phandle_phy = phandle; 245 } 246 247 if (strncmp(phy_mode, "rgmii", 5) == 0) { 248 meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]); 249 } else if (strcmp(phy_mode, "rmii") == 0) { 250 meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh); 251 } else { 252 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 253 return; 254 } 255 256 if (clk_enable(clk_gmac) != 0) { 257 aprint_error(": couldn't enable clock\n"); 258 return; 259 } 260 261 if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) { 262 aprint_error(": couldn't de-assert reset\n"); 263 return; 264 } 265 266 aprint_naive("\n"); 267 aprint_normal(": Gigabit Ethernet Controller\n"); 268 269 if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 270 FDT_INTR_MPSAFE, meson_dwmac_intr, sc, 271 device_xname(sc->sc_dev)) == NULL) { 272 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 273 return; 274 } 275 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 276 277 /* 278 * Depending on the DTS, we need to check either the "snps,...", 279 * properties on the ethernet node, or the "reset-..." 280 * properties on the phy node for the MAC reset information. 281 */ 282 283 if (of_hasprop(phandle, "snps,reset-gpio")) { 284 if (meson_dwmac_reset_eth(phandle) != 0) 285 aprint_error_dev(self, "reset failed\n"); 286 } else { 287 if (meson_dwmac_reset_phy(phandle_phy) != 0) 288 aprint_error_dev(self, "PHY reset failed\n"); 289 } 290 291 dwc_gmac_preattach_fdt(phandle, sc); 292 293 miiclk_rate = clk_get_rate(clk_gmac); 294 if (miiclk_rate > 250 * 1000 * 1000) 295 miiclk = GMAC_MII_CLK_250_300M_DIV124; 296 else if (miiclk_rate > 150 * 1000 * 1000) 297 miiclk = GMAC_MII_CLK_150_250M_DIV102; 298 else if (miiclk_rate > 100 * 1000 * 1000) 299 miiclk = GMAC_MII_CLK_100_150M_DIV62; 300 else if (miiclk_rate > 60 * 1000 * 1000) 301 miiclk = GMAC_MII_CLK_60_100M_DIV42; 302 else if (miiclk_rate > 35 * 1000 * 1000) 303 miiclk = GMAC_MII_CLK_35_60M_DIV26; 304 else 305 miiclk = GMAC_MII_CLK_25_35M_DIV16; 306 307 dwc_gmac_attach(sc, phy, miiclk); 308 } 309 310 CFATTACH_DECL_NEW(meson_dwmac, sizeof(struct dwc_gmac_softc), 311 meson_dwmac_match, meson_dwmac_attach, NULL, NULL); 312
Indexes created Sun Oct 25 00:26:45 UTC 2026