/src/sys/dev/ic/ |
igpio.c | 164 struct igpio_bank_setup *ibs; local in function:igpio_find_bank_setup 166 for (ibs = igpio_bank_setup; ibs->ibs_acpi_hid; ibs++) { 167 if (strcmp(ib->ib_sc->sc_acpi_hid, ibs->ibs_acpi_hid) != 0) 169 if (ibs->ibs_barno != barno) 172 return ibs; 237 struct igpio_bank_setup *ibs; local in function:igpio_attach 314 ibs = ib->ib_setup; 318 i, ibs->ibs_barno, ibs->ibs_first_pin, ibs->ibs_last_pin)) 380 struct igpio_bank_setup *ibs = ib->ib_setup; local in function:igpio_detach 420 struct igpio_bank_setup *ibs = ib->ib_setup; local in function:igpio_find_group 446 struct igpio_bank_setup *ibs = ib->ib_setup; local in function:igpio_groupcfg 744 struct igpio_bank_setup *ibs = ib->ib_setup; local in function:igpio_intr [all...] |
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_vm_sdma.c | 103 struct amdgpu_ib *ib = p->job->ibs; 150 struct amdgpu_ib *ib = p->job->ibs; 180 struct amdgpu_ib *ib = p->job->ibs; 218 ndw -= p->job->ibs->length_dw; 260 pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]);
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amdgpu_job.h | 49 struct amdgpu_ib *ibs; member in struct:amdgpu_job
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amdgpu_job.c | 83 (*job)->ibs = (void *)&(*job)[1]; 103 r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]); 120 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 178 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence); 237 DRM_INFO("Skip scheduling IBs!\n"); 239 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 242 DRM_ERROR("Error scheduling IBs (%d)\n", r);
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amdgpu_ib.c | 49 * IBs (Indirect Buffers) and areas of GPU accessible memory where 54 * put in IBs for execution by the requested ring. 65 * Request an IB (all asics). IBs are allocated using the 110 * @num_ibs: number of IBs to schedule 111 * @ibs: IB objects to schedule 123 * IBs, one for the CE and one for the DE. If there is a CE IB (called 128 struct amdgpu_ib *ibs, struct amdgpu_job *job, 132 struct amdgpu_ib *ib = &ibs[0]; 225 ib = &ibs[i]; 227 /* drop preamble IBs if we don't have a context switch * [all...] |
amdgpu_jpeg.c | 156 ib = &job->ibs[0];
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amdgpu_ttm.c | 2204 src_addr += job->ibs[0].gpu_addr; 2208 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 2211 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2212 WARN_ON(job->ibs[0].length_dw > num_dw); 2218 flags, &job->ibs[0].ptr[num_dw]); 2223 &job->ibs[0].ptr[num_dw]); 2286 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2294 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2295 WARN_ON(job->ibs[0].length_dw > num_dw); 2308 DRM_ERROR("Error scheduling IBs (%d)\n", r) [all...] |
amdgpu_uvd.c | 912 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 959 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 1001 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 1031 DRM_ERROR("UVD-IBs need a msg command!\n"); 1080 ib = &job->ibs[0];
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amdgpu_vce.c | 460 ib = &job->ibs[0]; 538 ib = &job->ibs[0]; 725 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 961 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1120 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
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amdgpu_gmc_v10_0.c | 383 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 384 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
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amdgpu_vcn.c | 402 ib = &job->ibs[0]; 571 ib = &job->ibs[0]; 624 ib = &job->ibs[0];
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amdgpu.h | 461 struct amdgpu_ib *ibs, struct amdgpu_job *job, 517 return p->job->ibs[ib_idx].ptr[idx]; 524 p->job->ibs[ib_idx].ptr[idx] = value;
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amdgpu_uvd_v7_0.c | 238 ib = &job->ibs[0]; 300 ib = &job->ibs[0]; 338 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 1263 * @p: the CS parser with the IBs 1271 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
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amdgpu_amdkfd.c | 597 ib = &job->ibs[0];
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amdgpu_trace.h | 157 __entry->dw = p->job->ibs[i].length_dw;
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amdgpu_uvd_v6_0.c | 228 ib = &job->ibs[0]; 291 ib = &job->ibs[0]; 329 * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
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amdgpu_cs.c | 310 * It means that in order to get full max MBps, at least 5 IBs per 752 ib = &p->job->ibs[j]; 892 ib = &parser->job->ibs[j];
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/src/tests/usr.bin/rump_server/ |
t_disk.sh | 80 echo 'test string' | dd of=testfile ibs=512 count=1 conv=sync
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/src/sys/arch/powerpc/include/booke/ |
openpicreg.h | 168 #define MSIIR_BIT(srs, ibs) (((srs) << 29) | ((ibs) << 24))
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