| /src/sys/arch/m68k/fpe/ |
| fpu_emulate.h | 190 struct instruction { struct
193 int is_advance; /* length of instruction */
237 int fpu_emul_fmovecr(struct fpemu *, struct instruction *);
238 int fpu_emul_fstore(struct fpemu *, struct instruction *);
239 int fpu_emul_fscale(struct fpemu *, struct instruction *);
270 int fpu_decode_ea(struct frame *, struct instruction *,
272 int fpu_load_ea(struct frame *, struct instruction *,
274 int fpu_store_ea(struct frame *, struct instruction *,
|
| fpu_calcea.c | 56 static int decode_ea6(struct frame *, struct instruction *,
58 static int fetch_immed(struct frame *, struct instruction *, int *);
59 static int fetch_disp(struct frame *, struct instruction *, int, int *);
71 fpu_decode_ea(struct frame *frame, struct instruction *insn,
212 decode_ea6(struct frame *frame, struct instruction *insn, struct insn_ea *ea,
298 fpu_load_ea(struct frame *frame, struct instruction *insn, struct insn_ea *ea,
439 fpu_store_ea(struct frame *frame, struct instruction *insn, struct insn_ea *ea,
553 fetch_immed(struct frame *frame, struct instruction *insn, int *dst)
619 fetch_disp(struct frame *frame, struct instruction *insn, int size, int *res)
|
| fpu_emulate.c | 62 static int fpu_emul_fmovmcr(struct fpemu *, struct instruction *);
63 static int fpu_emul_fmovm(struct fpemu *, struct instruction *);
64 static int fpu_emul_arith(struct fpemu *, struct instruction *);
65 static int fpu_emul_type1(struct fpemu *, struct instruction *);
66 static int fpu_emul_brcc(struct fpemu *, struct instruction *);
82 * Emulate a floating-point instruction.
89 static struct instruction insn;
111 * already set to the instruction following the faulting
112 * instruction. We need to calculate that, anyway. The
113 * fslw is the PC of the faulted instruction, which is wha
[all...] |
| fpu_fmovecr.c | 101 fpu_emul_fmovecr(struct fpemu *fe, struct instruction *insn)
|
| fpu_fstore.c | 45 fpu_emul_fstore(struct fpemu *fe, struct instruction *insn)
|
| /src/sys/arch/atari/atari/ |
| vectors.s | 41 VECTOR(illinst) | 4: illegal instruction
43 VECTOR(chkinst) | 6: CHK instruction
44 VECTOR(trapvinst) | 7: TRAPV instruction
79 VECTOR(illinst) | 33: TRAP instruction vector
87 VECTOR(illinst) | 36: TRAP instruction vector
88 VECTOR(illinst) | 37: TRAP instruction vector
89 VECTOR(illinst) | 38: TRAP instruction vector
90 VECTOR(illinst) | 39: TRAP instruction vector
91 VECTOR(illinst) | 40: TRAP instruction vector
92 VECTOR(illinst) | 41: TRAP instruction vecto
[all...] |
| /src/sys/dev/microcode/aic7xxx/ |
| aicasm_insformat.h | 4 * Instruction formats for the sequencer program downloaded to
104 struct instruction { struct
108 STAILQ_ENTRY(instruction) links;
|
| aicasm.h | 92 struct instruction *seq_alloc(void);
|
| aicasm.c | 104 static STAILQ_HEAD(,instruction) seq_program;
326 struct instruction *cur_instr;
355 struct instruction *cur_instr;
530 struct instruction *cur_instr;
617 /* Don't count this instruction as it is in a patch
672 * one and wait for our instruction pointer to
736 struct instruction *
739 struct instruction *new_instr;
741 new_instr = (struct instruction *)malloc(sizeof(struct instruction));
[all...] |
| /src/sys/arch/m68k/060sp/dist/ |
| changes | 49 3) For an opclass three FP instruction where the effective addressing
70 next instruction, and the result created in fp0 will be
86 For instruction read access errors, the info stacked is:
88 PC = PC of instruction being emulated
90 ADDRESS = PC of instruction being emulated
110 PC = PC of instruction being emulated
|
| ilsp.doc | 44 and the "cmp2" instruction. These instructions are not
46 exception vector #61 "Unimplemented Integer Instruction".
80 function. A branch instruction located at the selected entry point
87 For example, to use a 64-bit multiply instruction,
124 An example of using the "cmp2" instruction is as follows:
137 If the instruction being emulated is a divide and the source
139 instruction, executes an implemented divide using a zero
142 point to the correct instruction, the user will at least be able
|
| fskeletn.s | 119 # instruction.
138 # instruction.
157 # instruction.
176 # instruction.
197 # bit in the FPSR, and does an "rte". The instruction that caused the
236 # frame to the PC of the instruction causing the exception, and does an "rte".
237 # The execution of the instruction then proceeds with an enabled floating-point
254 # This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
|
| iskeletn.s | 65 # Instruction exception handler. For a normal exit, the
68 # Unimplemented Integer Instruction stack frame with
69 # the PC pointing to the instruction following the instruction
71 # To simply continue execution at the next instruction, just
82 # Instruction exception handler. If the instruction was a "chk2"
84 # a CHK exception stack frame from the Unimplemented Integer Instruction
115 # Instruction exception handler isp_unimp(). If the instruction is a 64-bi
[all...] |
| fplsp.doc | 46 "FP Unimplemented Instruction".
80 function. A branch instruction located at the selected entry point
87 There are 3 entry-points for each instruction type: single precision,
90 As an example, the "fsin" library instruction can be passed an
119 For example, if the instruction being emulated should cause a
135 the instruction but rather simply executes it.
|
| isp.s | 340 # _isp_unimp(): 060ISP entry point for Unimplemented Instruction #
343 # "Unimplemented Integer Instruction" exception in an operating #
347 # _imem_read_{word,long}() - read instruction word/longword #
376 # This handler fetches the first instruction longword from #
436 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
437 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
559 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
560 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
609 # The instruction that was just emulated was also being traced. The trace
610 # trap for this instruction will be lost unless we jump to the trace handler
[all...] |
| os.s | 113 # Reads from data/instruction memory while in supervisor mode.
320 # Read an instruction word from user memory.
326 # d0 - instruction word in d0
349 # Read an instruction longword from user memory.
355 # d0 - instruction longword in d0
418 # This is the exit point for the 060FPSP when an instruction is being traced
419 # and there are no other higher priority exceptions pending for this instruction
436 # The sample routine below simply executes an "rte" instruction which
|
| ilsp.s | 73 # _060LSP__idivu64_(): Emulate 64-bit unsigned div instruction. #
74 # _060LSP__idivs64_(): Emulate 64-bit signed div instruction. #
78 # 64-bit divide instruction. #
98 # Restore sign info if signed instruction. Set the condition #
101 # divide instruction. This way, the operating system can record that #
490 # _060LSP__imulu64_(): Emulate 64-bit unsigned mul instruction #
491 # _060LSP__imuls64_(): Emulate 64-bit signed mul instruction. #
495 # 64-bit multiply instruction. #
774 # instruction. #
917 # (3) keep 'X', 'N', and 'V' from before instruction
[all...] |
| /src/sys/arch/acorn32/doc/ |
| bootoptions | 65 icache Enable instruction cache
|
| /src/sys/arch/i386/stand/pxeboot/ |
| start_pxe.S | 62 # ljmp to the next instruction to adjust %cs
|
| /src/sys/arch/hppa/spmath/ |
| float.h | 419 #define Set_exceptiontype_and_instr_field(exception,instruction,object) \
420 object = ((exception) << 26) | (instruction)
|
| /src/sys/arch/mips/mips/ |
| copy.S | 263 move t0, v0 # dependent instruction
386 * Have to flush instruction cache afterwards.
411 * See if access to addr with a len type instruction causes a machine check.
434 move t0, v0 # dependent instruction
|
| cache_r4k_subr.S | 112 PTR_SLL t0, INT_SCALESHIFT # shift to instruction index
180 * Macro to emit 32 cache instruction with the right op and offset in the
|
| /src/lib/libc/arch/sparc/gen/ |
| divrem.m4 | 258 ! non-restoring fixup here (one instruction only!)
|
| /src/sys/arch/hppa/stand/common/ |
| srt0.S | 107 ; with separate instruction and data caches, we must flush our data
|
| /src/sys/lib/libkern/arch/sparc/ |
| divrem.m4 | 258 ! non-restoring fixup here (one instruction only!)
|
