| /src/sys/arch/powerpc/pci/ |
| pchb.c | 80 pcireg_t reg1, reg2; local in function:mpc105_print
83 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR1);
103 switch (reg1 & MPC105_PICR1_L2_MP) {
123 pcireg_t reg1, reg2; local in function:mpc106_print
126 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR1);
146 switch (reg1 & MPC106_PICR1_EXT_L2_EN) {
148 switch (reg1 & MPC106_PICR1_L2_MP) {
164 switch (reg1 & MPC106_PICR1_L2_MP) {
182 pcireg_t reg1; local in function:ibm82660_print
188 reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_nv04.c | 54 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
62 if (reg1 > 0x405c)
63 setPLL_double_highregs(devinit, reg1, pv);
65 setPLL_double_lowregs(devinit, reg1, pv);
67 setPLL_single(devinit, reg1, pv);
|
| priv.h | 28 int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
|
| /src/sys/arch/sgimips/ioc/ |
| oioc.c | 98 uint32_t reg1, reg2; local in function:oioc_attach
118 reg1 = 12 << OIOC2_CONFIG_HIWAT_SHFT;
119 reg1 |= OIOC2_CONFIG_BURST_MASK;
120 bus_space_write_4(sc->sc_iot, sc->sc_ioh, OIOC2_CONFIG, reg1);
123 if ((reg2 & (reg1 | OIOC2_CONFIG_NOSYNC_MASK)) == reg1)
|
| /src/sys/arch/hppa/spmath/ |
| md.h | 75 #define mdrr(reg1,reg2,result) {result_hi = reg1;result_lo = reg2;}
|
| /src/sys/dev/ic/ |
| rtwvar.h | 118 * Complete outstanding read and/or write ops on [reg0, reg1]
119 * ([reg1, reg0]) before starting new ops on the same region. See
123 rtw_barrier(const struct rtw_regs *r, int reg0, int reg1, int flags)
125 bus_space_barrier(r->r_bt, r->r_bh, MIN(reg0, reg1),
126 MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags);
133 #define RTW_SYNC(regs, reg0, reg1) \
134 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
137 #define RTW_WBW(regs, reg0, reg1) \
138 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE
[all...] |
| /src/sys/arch/hpcsh/dev/ |
| psh3lcd.c | 72 uint8_t reg1; member in struct:psh3lcd_x0_bcd
83 uint8_t reg1; member in struct:psh3lcd_xx0_bcd
144 bcr1 == psh3lcd_x0_bcd[i].reg1 &&
161 for (i = 0; psh3lcd_xx0_bcd[i].reg1 != 0; i++)
162 if (bcr1 == psh3lcd_xx0_bcd[i].reg1 &&
165 if (psh3lcd_xx0_bcd[i].reg1 == 0)
174 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_xx0_bcd[index].reg1);
183 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_x0_bcd[index].reg1);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_nv04.c | 190 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
192 bool head_a = (reg1 == 0x680508);
203 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1,
209 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
210 uint32_t oldpll1 = nvkm_rd32(device, reg1);
217 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
225 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
227 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
251 switch (reg1) {
[all...] |
| /src/sys/arch/hppa/hppa/ |
| locore.S | 89 #define _DEBUG_PUTCHAR(reg1, reg2) ! \
90 ldil L%COM1_TX_REG, %reg1 ! \
91 stb %reg2, R%COM1_TX_REG(%sr1, %reg1) ! \
92 ldil L%10000000, %reg1 ! \
94 comb,<>,n %reg1, %r0, -8 ! \
95 sub %reg1, %reg2, %reg1
96 #define DEBUG_PUTCHAR(reg1, reg2, ch) ! \
98 _DEBUG_PUTCHAR(reg1,reg2)
99 #define _DEBUG_DUMPN(reg1, reg2, reg3, p) !
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
111 .enable_reg = SRI(reg1, block, reg_num),\
113 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
115 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
116 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
192 .enable_reg = SRI(reg1, block, reg_num),\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
194 .enable_reg = SRI(reg1, block, reg_num),\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
190 .enable_reg = SRI(reg1, block, reg_num),\
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
|
| /src/games/warp/ |
| config.sh | 103 reg1='register'
|
| /src/sys/arch/mips/cavium/dev/ |
| octeon_pkovar.h | 91 octpko_cmd_word0(int sz1, int sz0, int s1, int reg1, int s0, int reg0,
99 __SHIFTIN(reg1, PKO_CMD_WORD0_REG1) |
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_virt.c | 54 uint32_t reg0, uint32_t reg1,
65 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
90 pr_err("failed to write reg %x wait reg %x\n", reg0, reg1);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_hw.c | 136 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
147 if (reg1 <= 0x405c) {
174 uint32_t reg1, pll1, pll2 = 0; local in function:nouveau_hw_get_pllvals
179 if (ret || !(reg1 = pll_lim.reg))
182 pll1 = nvif_rd32(device, reg1);
183 if (reg1 <= 0x405c)
184 pll2 = nvif_rd32(device, reg1 + 4);
186 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
191 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF)
[all...] |
| /src/sys/arch/hpcmips/dev/ |
| plumicu.c | 332 plumreg_t reg1, reg2, reg_ext, reg_pccard; local in function:plumicu_intr
337 reg1 = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG);
350 if (!(pic->ic_ackpat1 & reg1))
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| clk.h | 126 int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
|
| /src/sys/dev/usb/ |
| uchcom.c | 447 uint8_t reg1, uint8_t val1, uint8_t reg2, uint8_t val2)
451 (unsigned)reg1, (unsigned)val1,
455 reg1|((uint16_t)reg2<<8), val1|((uint16_t)val2<<8));
460 uint8_t reg1, uint8_t *rval1, uint8_t reg2, uint8_t *rval2)
468 reg1|((uint16_t)reg2<<8), 0, buf, sizeof(buf), &actin);
474 (unsigned)reg1, (unsigned)buf[0],
|
| /src/sys/arch/hpcmips/tx/ |
| txcom.c | 539 txreg_t reg, reg1; local in function:txcom_setbaudrate
547 reg1 = tx_conf_read(chip->sc_tc, ofs);
548 reg1 &= ~TX39_UARTCTRL1_ENUART;
549 tx_conf_write(chip->sc_tc, ofs, reg1);
556 reg1 |= TX39_UARTCTRL1_ENUART;
557 tx_conf_write(chip->sc_tc, ofs, reg1);
|
| /src/sys/dev/isa/ |
| wbsio.c | 370 uint8_t reg0, reg1, rev; local in function:wbsio_search
385 reg1 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_HM_ADDR_MSB);
390 iobase = (reg1 << 8) | (reg0 & ~0x7);
537 uint8_t reg0, reg1; local in function:wbsio_gpio_rt_init
545 reg1 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_GPIO_ADDR_MSB);
546 iobase = (reg1 << 8) | (reg0 & ~0x7);
|
| ess.c | 615 u_char reg1; local in function:ess_identify
632 if ((reg1 = ess_rdsp(sc)) != 0x68) {
633 printf("ess: First ID byte wrong (0x%02x)\n", reg1);
647 sc->sc_version = (reg1 << 8) + reg2;
654 reg1 = ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL);
655 reg2 = reg1 ^ 0x04; /* toggle bit 2 */
674 ess_write_mix_reg(sc, ESS_MREG_VOLUME_CTRL, reg1);
683 reg1 = ess_read_mix_reg(sc, ESS_MREG_SAMPLE_RATE);
684 reg2 = reg1 ^ 0xff; /* toggle all bits */
717 reg1 = ess_read_mix_reg(sc, ESS_MREG_VOLUME_CTRL)
[all...] |
| /src/sys/arch/hpcmips/vr/ |
| vrc4172gpio.c | 161 u_int16_t reg0, reg1; local in function:read_4
164 reg1 = read_2(sc, off + VRC2_EXGP_OFFSET);
166 return (reg0|(reg1<<16));
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| r128_drv.h | 407 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
408 (((reg1) >> 2) << 11) | ((reg0) >> 2))
|
