1 /* $NetBSD: pciide_common.c,v 1.74 2026/03/30 16:43:45 tls Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 30 /* 31 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by Christopher G. Demetriou 44 * for the NetBSD Project. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * PCI IDE controller driver. 62 * 63 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 64 * sys/dev/pci/ppb.c, revision 1.16). 65 * 66 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 67 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 68 * 5/16/94" from the PCI SIG. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.74 2026/03/30 16:43:45 tls Exp $"); 74 75 #include <sys/param.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pciidereg.h> 81 #include <dev/pci/pciidevar.h> 82 83 #include <dev/ic/wdcreg.h> 84 85 #ifdef ATADEBUG 86 #ifndef ATADEBUG_PCIIDE_MASK 87 #define ATADEBUG_PCIIDE_MASK 0 88 #endif 89 int atadebug_pciide_mask = ATADEBUG_PCIIDE_MASK; 90 #endif 91 92 #if NATA_DMA 93 static const char dmaerrfmt[] = 94 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 95 #endif 96 97 /* Default product description for devices not known from this controller */ 98 const struct pciide_product_desc default_product_desc = { 99 0, 100 0, 101 "Generic PCI IDE controller", 102 default_chip_map, 103 }; 104 105 const struct pciide_product_desc * 106 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp) 107 { 108 for (; pp->chip_map != NULL; pp++) 109 if (PCI_PRODUCT(id) == pp->ide_product) 110 break; 111 112 if (pp->chip_map == NULL) 113 return NULL; 114 return pp; 115 } 116 117 void 118 pciide_common_attach(struct pciide_softc *sc, const struct pci_attach_args *pa, 119 const struct pciide_product_desc *pp) 120 { 121 pci_chipset_tag_t pc = pa->pa_pc; 122 pcitag_t tag = pa->pa_tag; 123 #if NATA_DMA 124 pcireg_t csr; 125 #endif 126 const char *displaydev = NULL; 127 int dontprint = 0; 128 129 sc->sc_pci_id = pa->pa_id; 130 if (pp == NULL) { 131 /* should only happen for generic pciide devices */ 132 sc->sc_pp = &default_product_desc; 133 } else { 134 sc->sc_pp = pp; 135 /* if ide_name == NULL, printf is done in chip-specific map */ 136 if (pp->ide_name) 137 displaydev = pp->ide_name; 138 else 139 dontprint = 1; 140 } 141 142 if (dontprint) { 143 aprint_naive("disk controller\n"); 144 aprint_normal("\n"); /* ??? */ 145 } else 146 pci_aprint_devinfo_fancy(pa, "disk controller", displaydev, 1); 147 148 sc->sc_pc = pa->pa_pc; 149 sc->sc_tag = pa->pa_tag; 150 151 #if NATA_DMA 152 /* Set up DMA defaults; these might be adjusted by chip_map. */ 153 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 154 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 155 #endif 156 157 #ifdef ATADEBUG 158 if (atadebug_pciide_mask & DEBUG_PROBE) 159 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 160 #endif 161 sc->sc_wdcdev.cap |= WDC_CAPABILITY_ZERO_ABSENT; 162 163 sc->sc_pp->chip_map(sc, pa); 164 165 #if NATA_DMA 166 if (sc->sc_dma_ok) { 167 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 168 csr |= PCI_COMMAND_MASTER_ENABLE; 169 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 170 } 171 #endif 172 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 173 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 174 } 175 176 int 177 pciide_common_detach(struct pciide_softc *sc, int flags) 178 { 179 struct pciide_channel *cp; 180 struct ata_channel *wdc_cp; 181 struct wdc_regs *wdr; 182 int channel, drive; 183 int rv; 184 185 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags); 186 if (rv) 187 return rv; 188 189 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 190 channel++) { 191 cp = &sc->pciide_channels[channel]; 192 wdc_cp = &cp->ata_channel; 193 wdr = CHAN_TO_WDC_REGS(wdc_cp); 194 195 if (wdc_cp->ch_flags & ATACH_DISABLED) 196 continue; 197 198 if (wdr->cmd_ios != 0) 199 bus_space_unmap(wdr->cmd_iot, 200 wdr->cmd_baseioh, wdr->cmd_ios); 201 if (cp->compat != 0) { 202 if (wdr->ctl_ios != 0) 203 bus_space_unmap(wdr->ctl_iot, 204 wdr->ctl_ioh, wdr->ctl_ios); 205 } else { 206 if (cp->ctl_ios != 0) 207 bus_space_unmap(wdr->ctl_iot, 208 cp->ctl_baseioh, cp->ctl_ios); 209 } 210 211 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) { 212 #if NATA_DMA 213 pciide_dma_table_teardown(sc, channel, drive); 214 #endif 215 } 216 } 217 218 #if NATA_DMA 219 if (sc->sc_dma_ios != 0) 220 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 221 if (sc->sc_ba5_ss != 0) 222 bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss); 223 #endif 224 225 return 0; 226 } 227 228 int 229 pciide_detach(device_t self, int flags) 230 { 231 struct pciide_softc *sc = device_private(self); 232 struct pciide_channel *cp; 233 int channel; 234 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 235 bool has_compat_chan; 236 237 has_compat_chan = false; 238 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 239 channel++) { 240 cp = &sc->pciide_channels[channel]; 241 if (cp->compat != 0) { 242 has_compat_chan = true; 243 } 244 } 245 246 if (has_compat_chan != false) 247 return EBUSY; 248 #endif 249 250 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 251 channel++) { 252 cp = &sc->pciide_channels[channel]; 253 if (cp->compat != 0) 254 if (cp->ih != NULL) { 255 pciide_unmap_compat_intr(sc->sc_pc, cp, channel); 256 cp->ih = NULL; 257 } 258 } 259 260 if (sc->sc_pci_ih != NULL) { 261 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih); 262 sc->sc_pci_ih = NULL; 263 } 264 265 return pciide_common_detach(sc, flags); 266 } 267 268 /* tell whether the chip is enabled or not */ 269 int 270 pciide_chipen(struct pciide_softc *sc, const struct pci_attach_args *pa) 271 { 272 pcireg_t csr; 273 274 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) { 275 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 276 "I/O access disabled at bridge\n"); 277 return 0; 278 } 279 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 280 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) { 281 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 282 "I/O access disabled at device\n"); 283 return 0; 284 } 285 return 1; 286 } 287 288 void 289 pciide_mapregs_compat(const struct pci_attach_args *pa, 290 struct pciide_channel *cp, int compatchan) 291 { 292 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 293 struct ata_channel *wdc_cp = &cp->ata_channel; 294 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 295 int i; 296 297 cp->compat = 1; 298 299 wdr->cmd_iot = pa->pa_iot; 300 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 301 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 302 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 303 "couldn't map %s channel cmd regs\n", cp->name); 304 goto bad; 305 } 306 wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE; 307 308 wdr->ctl_iot = pa->pa_iot; 309 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 310 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 311 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 312 "couldn't map %s channel ctl regs\n", cp->name); 313 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 314 goto bad; 315 } 316 wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE; 317 318 for (i = 0; i < WDC_NREG; i++) { 319 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 320 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 321 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 322 "couldn't subregion %s channel cmd regs\n", 323 cp->name); 324 goto bad; 325 } 326 } 327 wdc_init_shadow_regs(wdr); 328 wdr->data32iot = wdr->cmd_iot; 329 wdr->data32ioh = wdr->cmd_iohs[0]; 330 return; 331 332 bad: 333 cp->ata_channel.ch_flags |= ATACH_DISABLED; 334 return; 335 } 336 337 void 338 pciide_mapregs_native(const struct pci_attach_args *pa, 339 struct pciide_channel *cp, int (*pci_intr)(void *)) 340 { 341 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 342 struct ata_channel *wdc_cp = &cp->ata_channel; 343 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 344 const char *intrstr; 345 pci_intr_handle_t intrhandle; 346 int i; 347 char intrbuf[PCI_INTRSTR_LEN]; 348 349 cp->compat = 0; 350 351 if (sc->sc_pci_ih == NULL) { 352 if (pci_intr_map(pa, &intrhandle) != 0) { 353 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 354 "couldn't map native-PCI interrupt\n"); 355 goto bad; 356 } 357 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 358 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 359 intrhandle, IPL_BIO, pci_intr, sc, 360 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 361 if (sc->sc_pci_ih != NULL) { 362 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 363 "using %s for native-PCI interrupt\n", 364 intrstr ? intrstr : "unknown interrupt"); 365 } else { 366 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 367 "couldn't establish native-PCI interrupt"); 368 if (intrstr != NULL) 369 aprint_error(" at %s", intrstr); 370 aprint_error("\n"); 371 goto bad; 372 } 373 } 374 cp->ih = sc->sc_pci_ih; 375 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 376 PCI_MAPREG_TYPE_IO, 0, 377 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) { 378 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 379 "couldn't map %s channel cmd regs\n", cp->name); 380 goto bad; 381 } 382 383 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 384 PCI_MAPREG_TYPE_IO, 0, 385 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) { 386 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 387 "couldn't map %s channel ctl regs\n", cp->name); 388 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 389 goto bad; 390 } 391 /* 392 * In native mode, 4 bytes of I/O space are mapped for the control 393 * register, the control register is at offset 2. Pass the generic 394 * code a handle for only one byte at the right offset. 395 */ 396 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 397 &wdr->ctl_ioh) != 0) { 398 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 399 "unable to subregion %s channel ctl regs\n", cp->name); 400 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 401 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios); 402 goto bad; 403 } 404 405 for (i = 0; i < WDC_NREG; i++) { 406 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 407 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 408 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 409 "couldn't subregion %s channel cmd regs\n", 410 cp->name); 411 goto bad; 412 } 413 } 414 wdc_init_shadow_regs(wdr); 415 wdr->data32iot = wdr->cmd_iot; 416 wdr->data32ioh = wdr->cmd_iohs[0]; 417 return; 418 419 bad: 420 cp->ata_channel.ch_flags |= ATACH_DISABLED; 421 return; 422 } 423 424 #if NATA_DMA 425 void 426 pciide_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 427 { 428 pcireg_t maptype; 429 bus_addr_t addr; 430 struct pciide_channel *pc; 431 int reg, chan; 432 bus_size_t size; 433 434 /* 435 * Map DMA registers 436 * 437 * Note that sc_dma_ok is the right variable to test to see if 438 * DMA can be done. If the interface doesn't support DMA, 439 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 440 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 441 * non-zero if the interface supports DMA and the registers 442 * could be mapped. 443 * 444 * XXX Note that despite the fact that the Bus Master IDE specs 445 * XXX say that "The bus master IDE function uses 16 bytes of IO 446 * XXX space," some controllers (at least the United 447 * XXX Microelectronics UM8886BF) place it in memory space. 448 */ 449 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 450 PCIIDE_REG_BUS_MASTER_DMA); 451 452 switch (maptype) { 453 case PCI_MAPREG_TYPE_IO: 454 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 455 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 456 &addr, NULL, NULL) == 0); 457 if (sc->sc_dma_ok == 0) { 458 aprint_verbose( 459 ", but unused (couldn't query registers)"); 460 break; 461 } 462 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 463 && addr >= 0x10000) { 464 sc->sc_dma_ok = 0; 465 aprint_verbose( 466 ", but unused (registers at unsafe address " 467 "%#lx)", (unsigned long)addr); 468 break; 469 } 470 /* FALLTHROUGH */ 471 472 case PCI_MAPREG_MEM_TYPE_32BIT: 473 sc->sc_dma_ok = (pci_mapreg_map(pa, 474 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 475 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) 476 == 0); 477 sc->sc_dmat = pa->pa_dmat; 478 if (sc->sc_dma_ok == 0) { 479 aprint_verbose(", but unused (couldn't map registers)"); 480 } else { 481 sc->sc_wdcdev.dma_arg = sc; 482 sc->sc_wdcdev.dma_init = pciide_dma_init; 483 sc->sc_wdcdev.dma_start = pciide_dma_start; 484 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 485 } 486 487 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 488 PCIIDE_OPTIONS_NODMA) { 489 aprint_verbose( 490 ", but unused (forced off by config file)"); 491 sc->sc_dma_ok = 0; 492 } else { 493 if (device_getprop_bool(sc->sc_wdcdev.sc_atac.atac_dev, 494 "pciide-disable-dma")) { 495 aprint_verbose( 496 ", but unused (disabled by platform)"); 497 sc->sc_dma_ok = 0; 498 } 499 } 500 break; 501 502 default: 503 sc->sc_dma_ok = 0; 504 aprint_verbose( 505 ", but unsupported register maptype (0x%x)", maptype); 506 } 507 508 if (sc->sc_dma_ok == 0) 509 return; 510 511 /* 512 * Set up the default handles for the DMA registers. 513 * Just reserve 32 bits for each handle, unless space 514 * doesn't permit it. 515 */ 516 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 517 pc = &sc->pciide_channels[chan]; 518 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 519 size = 4; 520 if (size > (IDEDMA_SCH_OFFSET - reg)) 521 size = IDEDMA_SCH_OFFSET - reg; 522 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 523 IDEDMA_SCH_OFFSET * chan + reg, size, 524 &pc->dma_iohs[reg]) != 0) { 525 sc->sc_dma_ok = 0; 526 aprint_verbose(", but can't subregion offset %d " 527 "size %lu", reg, (u_long)size); 528 return; 529 } 530 } 531 } 532 } 533 #endif /* NATA_DMA */ 534 535 int 536 pciide_compat_intr(void *arg) 537 { 538 struct pciide_channel *cp = arg; 539 540 #ifdef DIAGNOSTIC 541 /* should only be called for a compat channel */ 542 if (cp->compat == 0) 543 panic("pciide compat intr called for non-compat chan %p", cp); 544 #endif 545 return (wdcintr(&cp->ata_channel)); 546 } 547 548 int 549 pciide_pci_intr(void *arg) 550 { 551 struct pciide_softc *sc = arg; 552 struct pciide_channel *cp; 553 struct ata_channel *wdc_cp; 554 int i, rv, crv; 555 556 rv = 0; 557 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 558 cp = &sc->pciide_channels[i]; 559 wdc_cp = &cp->ata_channel; 560 561 /* If a compat channel skip. */ 562 if (cp->compat) 563 continue; 564 565 /* if this channel not waiting for intr, skip */ 566 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 567 continue; 568 569 crv = wdcintr(wdc_cp); 570 if (crv == 0) 571 ; /* leave rv alone */ 572 else if (crv == 1) 573 rv = 1; /* claim the intr */ 574 else if (rv == 0) /* crv should be -1 in this case */ 575 rv = crv; /* if we've done no better, take it */ 576 } 577 return (rv); 578 } 579 580 #if NATA_DMA 581 void 582 pciide_channel_dma_setup(struct pciide_channel *cp) 583 { 584 int drive, s; 585 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 586 struct ata_drive_datas *drvp; 587 588 KASSERT(cp->ata_channel.ch_ndrives != 0); 589 590 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) { 591 drvp = &cp->ata_channel.ch_drive[drive]; 592 /* If no drive, skip */ 593 if (drvp->drive_type == ATA_DRIVET_NONE) 594 continue; 595 /* setup DMA if needed */ 596 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 597 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) || 598 sc->sc_dma_ok == 0) { 599 s = splbio(); 600 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA); 601 splx(s); 602 continue; 603 } 604 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 605 drive) != 0) { 606 /* Abort DMA setup */ 607 s = splbio(); 608 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA); 609 splx(s); 610 continue; 611 } 612 } 613 } 614 615 #define NIDEDMA_TABLES(sc) \ 616 (MAXPHYS/(uimin((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1) 617 618 int 619 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 620 { 621 int error; 622 const bus_size_t dma_table_size = 623 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc); 624 struct pciide_dma_maps *dma_maps = 625 &sc->pciide_channels[channel].dma_maps[drive]; 626 627 /* If table was already allocated, just return */ 628 if (dma_maps->dma_table) 629 return 0; 630 631 /* Allocate memory for the DMA tables and map it */ 632 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 633 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg, 634 1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) { 635 aprint_error(dmaerrfmt, 636 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 637 "allocate", drive, error); 638 return error; 639 } 640 if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg, 641 dma_maps->dmamap_table_nseg, dma_table_size, 642 (void **)&dma_maps->dma_table, 643 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 644 aprint_error(dmaerrfmt, 645 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 646 "map", drive, error); 647 return error; 648 } 649 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 650 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 651 (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE); 652 /* Create and load table DMA map for this disk */ 653 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 654 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 655 &dma_maps->dmamap_table)) != 0) { 656 aprint_error(dmaerrfmt, 657 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 658 "create", drive, error); 659 return error; 660 } 661 if ((error = bus_dmamap_load(sc->sc_dmat, 662 dma_maps->dmamap_table, 663 dma_maps->dma_table, 664 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 665 aprint_error(dmaerrfmt, 666 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 667 "load", drive, error); 668 return error; 669 } 670 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 671 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 672 DEBUG_PROBE); 673 /* Create a xfer DMA map for this drive */ 674 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 675 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 676 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 677 &dma_maps->dmamap_xfer)) != 0) { 678 aprint_error(dmaerrfmt, 679 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 680 "create xfer", drive, error); 681 return error; 682 } 683 return 0; 684 } 685 686 void 687 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive) 688 { 689 struct pciide_channel *cp; 690 struct pciide_dma_maps *dma_maps; 691 692 cp = &sc->pciide_channels[channel]; 693 dma_maps = &cp->dma_maps[drive]; 694 695 if (dma_maps->dma_table == NULL) 696 return; 697 698 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer); 699 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table); 700 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table); 701 bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table, 702 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc)); 703 bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg, 704 dma_maps->dmamap_table_nseg); 705 706 dma_maps->dma_table = NULL; 707 708 return; 709 } 710 711 int 712 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive, 713 void *databuf, size_t datalen, int flags) 714 { 715 int error, seg; 716 struct pciide_channel *cp = &sc->pciide_channels[channel]; 717 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 718 719 error = bus_dmamap_load(sc->sc_dmat, 720 dma_maps->dmamap_xfer, 721 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 722 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 723 if (error) { 724 aprint_error(dmaerrfmt, 725 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 726 "load xfer", drive, error); 727 return error; 728 } 729 730 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 731 dma_maps->dmamap_xfer->dm_mapsize, 732 (flags & WDC_DMA_READ) ? 733 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 734 735 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 736 bus_addr_t phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 737 bus_size_t len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 738 739 #ifdef DIAGNOSTIC 740 /* A segment must not cross a 64k boundary */ 741 { 742 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 743 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 744 printf("pciide_dma: seg %d addr 0x%" PRIx64 745 " len 0x%" PRIx64 " not properly aligned\n", 746 seg, (uint64_t)phys, (uint64_t)len); 747 panic("pciide_dma: buf align"); 748 } 749 } 750 #endif 751 /* 752 * Some controllers get really upset if the length 753 * of any DMA segment is odd. This isn't something 754 * that's going to happen in normal steady-state 755 * operation (reading VM pages, etc.), but physio users 756 * don't have as many guard rails. 757 * 758 * Consider an 8K read request that starts at an odd 759 * offset within a page. At first blush, all of the 760 * checks pass because it's a sector-rounded size, but 761 * unless the buffer spans 2 physically contiguous pages, 762 * it's going to result in 2 odd-length DMA segments. 763 * 764 * Odd start addresses are also frowned upon, so we 765 * catch those here, too. 766 * 767 * Returning EINVAL here will cause the upper layers to 768 * fall back onto PIO. 769 */ 770 if ((phys & 1) != 0 || (len & 1) != 0) { 771 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 772 "Invalid DMA segment: " 773 "seg %d addr 0x%" PRIx64 " len 0x%" PRIx64 "\n", 774 seg, (uint64_t)phys, (uint64_t)len); 775 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 776 return EINVAL; 777 } 778 dma_maps->dma_table[seg].base_addr = htole32(phys); 779 dma_maps->dma_table[seg].byte_count = 780 htole32(len & IDEDMA_BYTE_COUNT_MASK); 781 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 782 seg, le32toh(dma_maps->dma_table[seg].byte_count), 783 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 784 785 } 786 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 787 htole32(IDEDMA_BYTE_COUNT_EOT); 788 789 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 790 dma_maps->dmamap_table->dm_mapsize, 791 BUS_DMASYNC_PREWRITE); 792 793 #ifdef DIAGNOSTIC 794 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 795 printf("pciide_dma_dmamap_setup: addr 0x%lx " 796 "not properly aligned\n", 797 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 798 panic("pciide_dma_init: table align"); 799 } 800 #endif 801 /* remember flags */ 802 dma_maps->dma_flags = flags; 803 804 return 0; 805 } 806 807 int 808 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen, 809 int flags) 810 { 811 struct pciide_softc *sc = v; 812 int error; 813 struct pciide_channel *cp = &sc->pciide_channels[channel]; 814 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 815 816 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 817 databuf, datalen, flags)) != 0) 818 return error; 819 /* Maps are ready. Start DMA function */ 820 /* Clear status bits */ 821 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 822 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 823 /* Write table addr */ 824 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 825 dma_maps->dmamap_table->dm_segs[0].ds_addr); 826 /* set read/write */ 827 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 828 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 829 return 0; 830 } 831 832 void 833 pciide_dma_start(void *v, int channel, int drive) 834 { 835 struct pciide_softc *sc = v; 836 struct pciide_channel *cp = &sc->pciide_channels[channel]; 837 838 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 839 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 840 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 841 | IDEDMA_CMD_START); 842 } 843 844 int 845 pciide_dma_finish(void *v, int channel, int drive, int force) 846 { 847 struct pciide_softc *sc = v; 848 u_int8_t status; 849 int error = 0; 850 struct pciide_channel *cp = &sc->pciide_channels[channel]; 851 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 852 853 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 854 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 855 DEBUG_XFERS); 856 857 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 858 return WDC_DMAST_NOIRQ; 859 860 /* stop DMA channel */ 861 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 862 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 863 & ~IDEDMA_CMD_START); 864 865 /* Unload the map of the data buffer */ 866 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 867 dma_maps->dmamap_xfer->dm_mapsize, 868 (dma_maps->dma_flags & WDC_DMA_READ) ? 869 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 870 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 871 872 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 873 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n", 874 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 875 drive, status); 876 error |= WDC_DMAST_ERR; 877 } 878 879 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 880 aprint_error("%s:%d:%d: bus-master DMA error: missing " 881 "interrupt, status=0x%x\n", 882 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 883 channel, drive, status); 884 error |= WDC_DMAST_NOIRQ; 885 } 886 887 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 888 /* data underrun, may be a valid condition for ATAPI */ 889 error |= WDC_DMAST_UNDER; 890 } 891 return error; 892 } 893 894 void 895 pciide_irqack(struct ata_channel *chp) 896 { 897 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 898 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 899 900 /* clear status bits in IDE DMA registers */ 901 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 902 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 903 } 904 #endif /* NATA_DMA */ 905 906 /* some common code used by several chip_map */ 907 int 908 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 909 { 910 struct pciide_channel *cp = &sc->pciide_channels[channel]; 911 sc->wdc_chanarray[channel] = &cp->ata_channel; 912 cp->name = PCIIDE_CHANNEL_NAME(channel); 913 cp->ata_channel.ch_channel = channel; 914 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 915 916 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 917 "%s channel %s to %s mode\n", cp->name, 918 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 919 "configured" : "wired", 920 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 921 "native-PCI" : "compatibility"); 922 return 1; 923 } 924 925 /* some common code used by several chip channel_map */ 926 void 927 pciide_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 928 pcireg_t interface, int (*pci_intr)(void *)) 929 { 930 struct ata_channel *wdc_cp = &cp->ata_channel; 931 932 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 933 pciide_mapregs_native(pa, cp, pci_intr); 934 else { 935 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 936 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 937 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 938 } 939 wdcattach(wdc_cp); 940 } 941 942 /* 943 * generic code to map the compat intr. 944 */ 945 void 946 pciide_map_compat_intr(const struct pci_attach_args *pa, 947 struct pciide_channel *cp, int compatchan) 948 { 949 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 950 951 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 952 cp->ih = 953 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev, 954 pa, compatchan, pciide_compat_intr, cp); 955 if (cp->ih == NULL) { 956 #endif 957 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 958 "no compatibility interrupt for use by %s " 959 "channel\n", cp->name); 960 cp->ata_channel.ch_flags |= ATACH_DISABLED; 961 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 962 } 963 #endif 964 } 965 966 void 967 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp, 968 int compatchan) 969 { 970 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 971 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 972 973 pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev, 974 sc->sc_pc, compatchan, cp->ih); 975 #endif 976 } 977 978 void 979 default_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 980 { 981 struct pciide_channel *cp; 982 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 983 pcireg_t csr; 984 int channel; 985 #if NATA_DMA 986 int drive; 987 u_int8_t idedma_ctl; 988 #endif 989 const char *failreason; 990 struct wdc_regs *wdr; 991 992 if (pciide_chipen(sc, pa) == 0) 993 return; 994 995 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 996 #if NATA_DMA 997 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 998 "bus-master DMA support present"); 999 if (sc->sc_pp == &default_product_desc && 1000 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1001 PCIIDE_OPTIONS_DMA) == 0) { 1002 aprint_verbose(", but unused (no driver support)"); 1003 sc->sc_dma_ok = 0; 1004 } else { 1005 pciide_mapreg_dma(sc, pa); 1006 if (sc->sc_dma_ok != 0) 1007 aprint_verbose(", used without full driver " 1008 "support"); 1009 } 1010 #else 1011 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1012 "bus-master DMA support present, but unused (no driver " 1013 "support)"); 1014 #endif /* NATA_DMA */ 1015 } else { 1016 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1017 "hardware does not support DMA"); 1018 #if NATA_DMA 1019 sc->sc_dma_ok = 0; 1020 #endif 1021 } 1022 aprint_verbose("\n"); 1023 #if NATA_DMA 1024 if (sc->sc_dma_ok) { 1025 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 1026 sc->sc_wdcdev.irqack = pciide_irqack; 1027 } 1028 #endif 1029 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 1030 #if NATA_DMA 1031 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 1032 #endif 1033 1034 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1035 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 1036 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 1037 sc->sc_wdcdev.wdc_maxdrives = 2; 1038 1039 wdc_allocate_regs(&sc->sc_wdcdev); 1040 1041 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1042 channel++) { 1043 cp = &sc->pciide_channels[channel]; 1044 if (pciide_chansetup(sc, channel, interface) == 0) 1045 continue; 1046 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 1047 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1048 pciide_mapregs_native(pa, cp, pciide_pci_intr); 1049 else 1050 pciide_mapregs_compat(pa, cp, 1051 cp->ata_channel.ch_channel); 1052 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 1053 continue; 1054 /* 1055 * Check to see if something appears to be there. 1056 */ 1057 failreason = NULL; 1058 /* 1059 * In native mode, always enable the controller. It's 1060 * not possible to have an ISA board using the same address 1061 * anyway. 1062 */ 1063 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1064 wdcattach(&cp->ata_channel); 1065 continue; 1066 } 1067 if (!wdcprobe(CHAN_TO_WDC_REGS(&cp->ata_channel))) { 1068 failreason = "not responding; disabled or no drives?"; 1069 goto next; 1070 } 1071 /* 1072 * Now, make sure it's actually attributable to this PCI IDE 1073 * channel by trying to access the channel again while the 1074 * PCI IDE controller's I/O space is disabled. (If the 1075 * channel no longer appears to be there, it belongs to 1076 * this controller.) YUCK! 1077 */ 1078 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1079 PCI_COMMAND_STATUS_REG); 1080 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1081 csr & ~PCI_COMMAND_IO_ENABLE); 1082 if (wdcprobe(CHAN_TO_WDC_REGS(&cp->ata_channel))) 1083 failreason = "other hardware responding at addresses"; 1084 pci_conf_write(sc->sc_pc, sc->sc_tag, 1085 PCI_COMMAND_STATUS_REG, csr); 1086 next: 1087 if (failreason) { 1088 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1089 "%s channel ignored (%s)\n", cp->name, failreason); 1090 cp->ata_channel.ch_flags |= ATACH_DISABLED; 1091 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 1092 wdr->cmd_ios); 1093 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, 1094 wdr->ctl_ios); 1095 } else { 1096 pciide_map_compat_intr(pa, cp, 1097 cp->ata_channel.ch_channel); 1098 wdcattach(&cp->ata_channel); 1099 } 1100 } 1101 1102 #if NATA_DMA 1103 if (sc->sc_dma_ok == 0) 1104 return; 1105 1106 /* Allocate DMA maps */ 1107 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1108 channel++) { 1109 idedma_ctl = 0; 1110 cp = &sc->pciide_channels[channel]; 1111 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) { 1112 /* 1113 * we have not probed the drives yet, allocate 1114 * resources for all of them. 1115 */ 1116 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1117 /* Abort DMA setup */ 1118 aprint_error( 1119 "%s:%d:%d: can't allocate DMA maps, " 1120 "using PIO transfers\n", 1121 device_xname( 1122 sc->sc_wdcdev.sc_atac.atac_dev), 1123 channel, drive); 1124 sc->sc_dma_ok = 0; 1125 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 1126 sc->sc_wdcdev.irqack = NULL; 1127 break; 1128 } 1129 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1130 } 1131 if (idedma_ctl != 0) { 1132 /* Add software bits in status register */ 1133 bus_space_write_1(sc->sc_dma_iot, 1134 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 1135 } 1136 } 1137 #endif /* NATA_DMA */ 1138 } 1139 1140 void 1141 sata_setup_channel(struct ata_channel *chp) 1142 { 1143 #if NATA_DMA 1144 struct ata_drive_datas *drvp; 1145 int drive; 1146 #if NATA_UDMA 1147 int s; 1148 #endif 1149 u_int32_t idedma_ctl; 1150 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 1151 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 1152 1153 /* setup DMA if needed */ 1154 pciide_channel_dma_setup(cp); 1155 1156 idedma_ctl = 0; 1157 1158 KASSERT(cp->ata_channel.ch_ndrives != 0); 1159 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) { 1160 drvp = &chp->ch_drive[drive]; 1161 /* If no drive, skip */ 1162 if (drvp->drive_type == ATA_DRIVET_NONE) 1163 continue; 1164 #if NATA_UDMA 1165 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 1166 /* use Ultra/DMA */ 1167 s = splbio(); 1168 drvp->drive_flags &= ~ATA_DRIVE_DMA; 1169 splx(s); 1170 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1171 } else 1172 #endif /* NATA_UDMA */ 1173 if (drvp->drive_flags & ATA_DRIVE_DMA) { 1174 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1175 } 1176 } 1177 1178 /* 1179 * Nothing to do to setup modes; it is meaningless in S-ATA 1180 * (but many S-ATA drives still want to get the SET_FEATURE 1181 * command). 1182 */ 1183 if (idedma_ctl != 0) { 1184 /* Add software bits in status register */ 1185 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1186 idedma_ctl); 1187 } 1188 #endif /* NATA_DMA */ 1189 } 1190
Indexes created Sun Oct 25 00:26:45 UTC 2026