1 /* $NetBSD: identcpu.c,v 1.143 2026/08/25 22:23:03 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.143 2026/08/25 22:23:03 andvar Exp $"); 34 35 #include "opt_xen.h" 36 37 #include <sys/param.h> 38 39 #include <sys/cpu.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 43 #include <crypto/aes/aes_impl.h> 44 #include <crypto/aes/arch/x86/aes_ni.h> 45 #include <crypto/aes/arch/x86/aes_sse2_4x32.h> 46 #include <crypto/aes/arch/x86/aes_ssse3.h> 47 #include <crypto/aes/arch/x86/aes_via.h> 48 #include <crypto/chacha/arch/x86/chacha_sse2.h> 49 #include <crypto/chacha/chacha_impl.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/cpu.h> 54 #include <machine/frame.h> 55 #include <machine/pio.h> 56 #include <machine/specialreg.h> 57 58 #include <x86/cacheinfo.h> 59 #include <x86/cputypes.h> 60 #include <x86/cpuvar.h> 61 #include <x86/fpu.h> 62 63 #include <dev/vmt/vmtreg.h> /* for vmt_hvcall() */ 64 #include <dev/vmt/vmtvar.h> /* for vmt_hvcall() */ 65 66 #ifndef XENPV 67 #include "hyperv.h" 68 #if NHYPERV > 0 69 #include <x86/x86/hypervvar.h> 70 #endif 71 #endif 72 73 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 74 75 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 76 AMD_L2L3CACHE_INFO; 77 78 int cpu_vendor; 79 char cpu_brand_string[49]; 80 81 int x86_fpu_save __read_mostly; 82 unsigned int x86_fpu_save_size __read_mostly = sizeof(struct save87); 83 uint64_t x86_xsave_features __read_mostly = 0; 84 size_t x86_xsave_offsets[XSAVE_MAX_COMPONENT+1] __read_mostly; 85 size_t x86_xsave_sizes[XSAVE_MAX_COMPONENT+1] __read_mostly; 86 u_int cpu_max_hypervisor_cpuid = 0; 87 88 /* 89 * Note: these are just the ones that may not have a cpuid instruction. 90 * We deal with the rest in a different way. 91 */ 92 const int i386_nocpuid_cpus[] = { 93 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386SX */ 94 CPUVENDOR_INTEL, CPUCLASS_386, /* CPU_386 */ 95 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486SX */ 96 CPUVENDOR_INTEL, CPUCLASS_486, /* CPU_486 */ 97 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_486DLC */ 98 CPUVENDOR_CYRIX, CPUCLASS_486, /* CPU_6x86 */ 99 CPUVENDOR_NEXGEN, CPUCLASS_386, /* CPU_NX586 */ 100 }; 101 102 static const char cpu_vendor_names[][10] = { 103 "Unknown", "Intel", "NS/Cyrix", "NexGen", "AMD", "IDT/VIA", "Transmeta", 104 "Vortex86" 105 }; 106 107 static void 108 cpu_probe_intel_cache(struct cpu_info *ci) 109 { 110 const struct x86_cache_info *cai; 111 u_int descs[4]; 112 int iterations, i, j; 113 uint8_t desc; 114 115 if (cpuid_level >= 2) { 116 /* Parse the cache info from `cpuid leaf 2', if we have it. */ 117 x86_cpuid(2, descs); 118 iterations = descs[0] & 0xff; 119 while (iterations-- > 0) { 120 for (i = 0; i < 4; i++) { 121 if (descs[i] & 0x80000000) 122 continue; 123 for (j = 0; j < 4; j++) { 124 if (i == 0 && j == 0) 125 continue; 126 desc = (descs[i] >> (j * 8)) & 0xff; 127 if (desc == 0) 128 continue; 129 cai = cpu_cacheinfo_lookup( 130 intel_cpuid_cache_info, desc); 131 if (cai != NULL) { 132 ci->ci_cinfo[cai->cai_index] = 133 *cai; 134 } 135 } 136 } 137 } 138 } 139 140 if (cpuid_level < 4) 141 return; 142 143 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 144 cpu_dcp_cacheinfo(ci, 4); 145 } 146 147 static void 148 cpu_probe_intel_errata(struct cpu_info *ci) 149 { 150 u_int family, model; 151 152 family = CPUID_TO_FAMILY(ci->ci_signature); 153 model = CPUID_TO_MODEL(ci->ci_signature); 154 155 /* 156 * For details, refer to the Intel Pentium and Celeron Processor 157 * N- and J- Series Specification Update (Document number: 334820-010), 158 * August 2022, Revision 010. See page 28, Section 5.30: "APL30 A Store 159 * Instruction May Not Wake Up MWAIT." 160 * https://cdrdv2-public.intel.com/334820/334820-APL_Spec_Update_rev010.pdf 161 * https://web.archive.org/web/20250114072355/https://cdrdv2-public.intel.com/334820/334820-APL_Spec_Update_rev010.pdf 162 * 163 * Disable MWAIT/MONITOR on Apollo Lake CPUs to address the 164 * APL30 erratum. When using the MONITOR/MWAIT instruction 165 * pair, stores to the armed address range may fail to trigger 166 * MWAIT to resume execution. When these instructions are used 167 * to hatch secondary CPUs, this erratum causes SMP boot 168 * failures. 169 */ 170 if (family == 0x6 && model == 0x5C) { 171 wrmsr(MSR_MISC_ENABLE, 172 rdmsr(MSR_MISC_ENABLE) & ~IA32_MISC_MWAIT_EN); 173 174 cpu_feature[1] &= ~CPUID2_MONITOR; 175 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 176 } 177 } 178 179 static void 180 cpu_probe_intel(struct cpu_info *ci) 181 { 182 183 if (cpu_vendor != CPUVENDOR_INTEL) 184 return; 185 186 cpu_probe_intel_cache(ci); 187 cpu_probe_intel_errata(ci); 188 } 189 190 static void 191 cpu_probe_amd_cache(struct cpu_info *ci) 192 { 193 const struct x86_cache_info *cp; 194 struct x86_cache_info *cai; 195 int family, model; 196 u_int descs[4]; 197 u_int lfunc; 198 199 family = CPUID_TO_FAMILY(ci->ci_signature); 200 model = CPUID_TO_MODEL(ci->ci_signature); 201 202 /* K5 model 0 has none of this info. */ 203 if (family == 5 && model == 0) 204 return; 205 206 /* Determine the largest extended function value. */ 207 x86_cpuid(0x80000000, descs); 208 lfunc = descs[0]; 209 210 if (lfunc < 0x80000005) 211 return; 212 213 /* Determine L1 cache/TLB info. */ 214 x86_cpuid(0x80000005, descs); 215 216 /* K6-III and higher have large page TLBs. */ 217 if ((family == 5 && model >= 9) || family >= 6) { 218 cai = &ci->ci_cinfo[CAI_ITLB2]; 219 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 220 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 221 cai->cai_linesize = (4 * 1024 * 1024); 222 223 cai = &ci->ci_cinfo[CAI_DTLB2]; 224 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 225 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 226 cai->cai_linesize = (4 * 1024 * 1024); 227 } 228 229 cai = &ci->ci_cinfo[CAI_ITLB]; 230 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 231 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 232 cai->cai_linesize = (4 * 1024); 233 234 cai = &ci->ci_cinfo[CAI_DTLB]; 235 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 236 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 237 cai->cai_linesize = (4 * 1024); 238 239 cai = &ci->ci_cinfo[CAI_DCACHE]; 240 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 241 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 242 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 243 244 cai = &ci->ci_cinfo[CAI_ICACHE]; 245 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 246 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 247 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 248 249 if (lfunc < 0x80000006) 250 return; 251 252 /* Determine L2 cache/TLB info. */ 253 x86_cpuid(0x80000006, descs); 254 255 cai = &ci->ci_cinfo[CAI_L2CACHE]; 256 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 257 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 258 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 259 260 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 261 cai->cai_associativity); 262 if (cp != NULL) 263 cai->cai_associativity = cp->cai_associativity; 264 else 265 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 266 267 if (family < 0xf) 268 return; 269 270 /* Determine L3 cache info on AMD Family 10h and newer processors */ 271 cai = &ci->ci_cinfo[CAI_L3CACHE]; 272 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 273 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 274 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 275 276 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 277 cai->cai_associativity); 278 if (cp != NULL) 279 cai->cai_associativity = cp->cai_associativity; 280 else 281 cai->cai_associativity = 0; /* XXX Unknown reserved */ 282 283 if (lfunc < 0x80000019) 284 return; 285 286 /* Determine 1GB TLB info. */ 287 x86_cpuid(0x80000019, descs); 288 289 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 290 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[1]); 291 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[1]); 292 cai->cai_linesize = (1 * 1024); 293 294 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 295 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 296 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 297 cai->cai_linesize = (1 * 1024); 298 299 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 300 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 301 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 302 cai->cai_linesize = (1 * 1024); 303 304 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 305 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[0]); 306 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[0]); 307 cai->cai_linesize = (1 * 1024); 308 309 if (lfunc < 0x8000001d) 310 return; 311 312 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 313 cpu_dcp_cacheinfo(ci, 0x8000001d); 314 } 315 316 static void 317 cpu_probe_amd_errata(struct cpu_info *ci) 318 { 319 u_int model; 320 uint64_t val; 321 int flag; 322 323 model = CPUID_TO_MODEL(ci->ci_signature); 324 325 switch (CPUID_TO_FAMILY(ci->ci_signature)) { 326 case 0x05: /* K5 */ 327 if (model == 0) { 328 /* 329 * According to the AMD Processor Recognition App Note, 330 * the AMD-K5 Model 0 uses the wrong bit to indicate 331 * support for global PTEs, instead using bit 9 (APIC) 332 * rather than bit 13 (i.e. "0x200" vs. 0x2000"). 333 */ 334 flag = ci->ci_feat_val[0]; 335 if ((flag & CPUID_APIC) != 0) 336 flag = (flag & ~CPUID_APIC) | CPUID_PGE; 337 ci->ci_feat_val[0] = flag; 338 } 339 break; 340 341 case 0x10: /* Family 10h */ 342 /* 343 * On Family 10h, certain BIOSes do not enable WC+ support. 344 * This causes WC+ to become CD, and degrades guest 345 * performance at the NPT level. 346 * 347 * Explicitly enable WC+ if we're not a guest. 348 */ 349 if (!ISSET(ci->ci_feat_val[1], CPUID2_RAZ)) { 350 val = rdmsr(MSR_BU_CFG2); 351 val &= ~BU_CFG2_CWPLUS_DIS; 352 wrmsr(MSR_BU_CFG2, val); 353 } 354 break; 355 356 case 0x17: 357 /* 358 * "Revision Guide for AMD Family 17h Models 00h-0Fh 359 * Processors" revision 1.12: 360 * 361 * 1057 MWAIT or MWAITX Instructions May Fail to Correctly 362 * Exit From the Monitor Event Pending State 363 * 364 * 1109 MWAIT Instruction May Hang a Thread 365 */ 366 if (model == 0x01) { 367 cpu_feature[1] &= ~CPUID2_MONITOR; 368 ci->ci_feat_val[1] &= ~CPUID2_MONITOR; 369 } 370 break; 371 } 372 } 373 374 static void 375 cpu_probe_amd(struct cpu_info *ci) 376 { 377 378 if (cpu_vendor != CPUVENDOR_AMD) 379 return; 380 381 cpu_probe_amd_cache(ci); 382 cpu_probe_amd_errata(ci); 383 } 384 385 static inline uint8_t 386 cyrix_read_reg(uint8_t reg) 387 { 388 389 outb(0x22, reg); 390 return inb(0x23); 391 } 392 393 static inline void 394 cyrix_write_reg(uint8_t reg, uint8_t data) 395 { 396 397 outb(0x22, reg); 398 outb(0x23, data); 399 } 400 401 static void 402 cpu_probe_cyrix_cmn(struct cpu_info *ci) 403 { 404 /* 405 * i8254 latch check routine: 406 * National Geode (formerly Cyrix MediaGX) has a serious bug in 407 * its built-in i8254-compatible clock module (cs5510 cs5520). 408 * Set the variable 'clock_broken_latch' to indicate it. 409 * 410 * This bug is not present in the cs5530, and the flag 411 * is disabled again in sys/arch/i386/pci/pcib.c if this later 412 * model device is detected. Ideally, this work-around should not 413 * even be in here, it should be in there. XXX 414 */ 415 uint8_t c3; 416 #ifndef XENPV 417 extern int clock_broken_latch; 418 419 switch (ci->ci_signature) { 420 case 0x440: /* Cyrix MediaGX */ 421 case 0x540: /* GXm */ 422 clock_broken_latch = 1; 423 break; 424 } 425 #endif 426 427 /* set up various cyrix registers */ 428 /* 429 * Enable suspend on halt (powersave mode). 430 * When powersave mode is enabled, the TSC stops counting 431 * while the CPU is halted in idle() waiting for an interrupt. 432 * This means we can't use the TSC for interval time in 433 * microtime(9), and thus it is disabled here. 434 * 435 * It still makes a perfectly good cycle counter 436 * for program profiling, so long as you remember you're 437 * counting cycles, and not time. Further, if you don't 438 * mind not using powersave mode, the TSC works just fine, 439 * so this should really be optional. XXX 440 */ 441 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 442 443 /* 444 * Do not disable the TSC on the Geode GX, it's reported to 445 * work fine. 446 */ 447 if (ci->ci_signature != 0x552) 448 ci->ci_feat_val[0] &= ~CPUID_TSC; 449 450 /* enable access to ccr4/ccr5 */ 451 c3 = cyrix_read_reg(0xC3); 452 cyrix_write_reg(0xC3, c3 | 0x10); 453 /* cyrix's workaround for the "coma bug" */ 454 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 455 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 456 cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xffu); 457 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 458 /* disable access to ccr4/ccr5 */ 459 cyrix_write_reg(0xC3, c3); 460 } 461 462 static void 463 cpu_probe_cyrix(struct cpu_info *ci) 464 { 465 466 if (cpu_vendor != CPUVENDOR_CYRIX || 467 CPUID_TO_FAMILY(ci->ci_signature) < 4 || 468 CPUID_TO_FAMILY(ci->ci_signature) > 6) 469 return; 470 471 cpu_probe_cyrix_cmn(ci); 472 } 473 474 static void 475 cpu_probe_winchip(struct cpu_info *ci) 476 { 477 478 if (cpu_vendor != CPUVENDOR_IDT || 479 CPUID_TO_FAMILY(ci->ci_signature) != 5) 480 return; 481 482 /* WinChip C6 */ 483 if (CPUID_TO_MODEL(ci->ci_signature) == 4) 484 ci->ci_feat_val[0] &= ~CPUID_TSC; 485 } 486 487 static void 488 cpu_probe_c3(struct cpu_info *ci) 489 { 490 const struct x86_cache_info *cp; 491 u_int family, model, stepping, descs[4], lfunc, msr; 492 struct x86_cache_info *cai; 493 494 if (cpu_vendor != CPUVENDOR_IDT || 495 CPUID_TO_FAMILY(ci->ci_signature) < 6) 496 return; 497 498 family = CPUID_TO_FAMILY(ci->ci_signature); 499 model = CPUID_TO_MODEL(ci->ci_signature); 500 stepping = CPUID_TO_STEPPING(ci->ci_signature); 501 502 if (family == 6) { 503 /* 504 * VIA Eden ESP. 505 * 506 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet" 507 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf 508 * 509 * 1. The CMPXCHG8B instruction is provided and always enabled, 510 * however, it appears disabled in the corresponding CPUID 511 * function bit 0 to avoid a bug in an early version of 512 * Windows NT. However, this default can be changed via a 513 * bit in the FCR MSR. 514 */ 515 ci->ci_feat_val[0] |= CPUID_CX8; 516 wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_FCR_CX8_REPORT); 517 518 /* 519 * For reference on VIA Alternate Instructions, see the VIA C3 520 * Processor Alternate Instruction Set Application Note, 2002. 521 * http://www.bitsavers.org/components/viaTechnologies/C3-ais-appnote.pdf 522 * 523 * Disable unsafe ALTINST mode for VIA C3 processors, if necessary. 524 * 525 * This is done for the security reasons, as some CPUs were 526 * found with ALTINST enabled by default. This functionality 527 * has ability to bypass many x86 architecture memory 528 * protections and privilege checks, exposing a possibility 529 * for backdoors and should not be enabled unintentionally. 530 */ 531 if (model > 0x5 && model < 0xA) { 532 int disable_ais = 0; 533 x86_cpuid(0xc0000000, descs); 534 lfunc = descs[0]; 535 /* Check AIS flags first if supported ("Nehemiah"). */ 536 if (lfunc >= 0xc0000001) { 537 x86_cpuid(0xc0000001, descs); 538 lfunc = descs[3]; 539 if ((lfunc & CPUID_VIA_HAS_AIS) 540 && (lfunc & CPUID_VIA_DO_AIS)) { 541 disable_ais = 1; 542 } 543 } else /* Explicitly disable AIS for pre-CX5L CPUs. */ 544 disable_ais = 1; 545 546 if (disable_ais) { 547 msr = rdmsr(MSR_VIA_FCR); 548 wrmsr(MSR_VIA_FCR, msr & ~VIA_FCR_ALTINST_ENABLE); 549 } 550 } 551 } 552 553 if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) { 554 /* VIA Nehemiah or later. */ 555 x86_cpuid(0xc0000000, descs); 556 lfunc = descs[0]; 557 if (lfunc >= 0xc0000001) { /* has ACE, RNG */ 558 int rng_enable = 0, ace_enable = 0; 559 x86_cpuid(0xc0000001, descs); 560 lfunc = descs[3]; 561 ci->ci_feat_val[4] = lfunc; 562 /* Check for and enable RNG */ 563 if (lfunc & CPUID_VIA_HAS_RNG) { 564 if (!(lfunc & CPUID_VIA_DO_RNG)) { 565 rng_enable++; 566 ci->ci_feat_val[4] |= CPUID_VIA_DO_RNG; 567 } 568 } 569 /* Check for and enable ACE (AES-CBC) */ 570 if (lfunc & CPUID_VIA_HAS_ACE) { 571 if (!(lfunc & CPUID_VIA_DO_ACE)) { 572 ace_enable++; 573 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE; 574 } 575 } 576 /* Check for and enable SHA */ 577 if (lfunc & CPUID_VIA_HAS_PHE) { 578 if (!(lfunc & CPUID_VIA_DO_PHE)) { 579 ace_enable++; 580 ci->ci_feat_val[4] |= CPUID_VIA_DO_PHE; 581 } 582 } 583 /* Check for and enable ACE2 (AES-CTR) */ 584 if (lfunc & CPUID_VIA_HAS_ACE2) { 585 if (!(lfunc & CPUID_VIA_DO_ACE2)) { 586 ace_enable++; 587 ci->ci_feat_val[4] |= CPUID_VIA_DO_ACE2; 588 } 589 } 590 /* Check for and enable PMM (modmult engine) */ 591 if (lfunc & CPUID_VIA_HAS_PMM) { 592 if (!(lfunc & CPUID_VIA_DO_PMM)) { 593 ace_enable++; 594 ci->ci_feat_val[4] |= CPUID_VIA_DO_PMM; 595 } 596 } 597 598 /* 599 * Actually do the enables. It's a little gross, 600 * but per the PadLock programming guide, "Enabling 601 * PadLock", condition 3, we must enable SSE too or 602 * else the first use of RNG or ACE instructions 603 * will generate a trap. 604 * 605 * We must do this early because of kernel RNG 606 * initialization but it is safe without the full 607 * FPU-detect as all these CPUs have SSE. 608 */ 609 lcr4(rcr4() | CR4_OSFXSR); 610 611 if (rng_enable) { 612 msr = rdmsr(MSR_VIA_RNG); 613 msr |= MSR_VIA_RNG_ENABLE; 614 /* C7 stepping 8 and subsequent CPUs have dual RNG */ 615 if (model > 0xA || (model == 0xA && stepping > 0x7)) { 616 msr |= MSR_VIA_RNG_2NOISE; 617 } 618 wrmsr(MSR_VIA_RNG, msr); 619 } 620 621 if (ace_enable) { 622 msr = rdmsr(MSR_VIA_FCR); 623 wrmsr(MSR_VIA_FCR, msr | VIA_FCR_ACE_ENABLE); 624 } 625 } 626 } 627 628 /* Determine the largest extended function value. */ 629 x86_cpuid(0x80000000, descs); 630 lfunc = descs[0]; 631 632 /* 633 * Determine L1 cache/TLB info. 634 */ 635 if (lfunc < 0x80000005) { 636 /* No L1 cache info available. */ 637 return; 638 } 639 640 x86_cpuid(0x80000005, descs); 641 642 cai = &ci->ci_cinfo[CAI_ITLB]; 643 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 644 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 645 cai->cai_linesize = (4 * 1024); 646 647 cai = &ci->ci_cinfo[CAI_DTLB]; 648 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 649 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 650 cai->cai_linesize = (4 * 1024); 651 652 cai = &ci->ci_cinfo[CAI_DCACHE]; 653 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 654 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 655 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 656 if (family == 6 && model == 9 && stepping == 8) { 657 /* Erratum: stepping 8 reports 4 when it should be 2 */ 658 cai->cai_associativity = 2; 659 } 660 661 cai = &ci->ci_cinfo[CAI_ICACHE]; 662 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 663 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 664 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 665 if (family == 6 && model == 9 && stepping == 8) { 666 /* Erratum: stepping 8 reports 4 when it should be 2 */ 667 cai->cai_associativity = 2; 668 } 669 670 /* 671 * Determine L2 cache/TLB info. 672 */ 673 if (lfunc < 0x80000006) { 674 /* No L2 cache info available. */ 675 return; 676 } 677 678 x86_cpuid(0x80000006, descs); 679 680 cai = &ci->ci_cinfo[CAI_L2CACHE]; 681 if (family == 6 && model < 9) { 682 // Pre-Nehemiah L2 cache mapping. 683 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 684 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 685 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 686 return; 687 } 688 689 // Nehemiah, Esther, and Isaiah before CNQ use AMD-style cache encoding. 690 // It will be overridden by `cpuid leaf 4` (including L1) if available. 691 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 692 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 693 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 694 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 695 cai->cai_associativity); 696 if (cp != NULL) 697 cai->cai_associativity = cp->cai_associativity; 698 else 699 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 700 701 // Late VIA models (CNQ and later) and Zhaoxin CPUs prefer `cpuid leaf 4'. 702 if (cpuid_level < 4) 703 return; 704 705 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 706 cpu_dcp_cacheinfo(ci, 4); 707 708 if (cpuid_level < 7) 709 return; 710 711 /* XXX: Disable SMAP for now, as it causes a page fault during boot. */ 712 cpu_feature[5] &= ~CPUID_SEF_SMAP; 713 ci->ci_feat_val[5] &= ~CPUID_SEF_SMAP; 714 } 715 716 static void 717 cpu_probe_geode(struct cpu_info *ci) 718 { 719 720 if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 || 721 CPUID_TO_FAMILY(ci->ci_signature) != 5) 722 return; 723 724 cpu_probe_cyrix_cmn(ci); 725 cpu_probe_amd_cache(ci); 726 } 727 728 static void 729 cpu_probe_vortex86(struct cpu_info *ci) 730 { 731 #define PCI_MODE1_ADDRESS_REG 0x0cf8 732 #define PCI_MODE1_DATA_REG 0x0cfc 733 #define PCI_MODE1_ENABLE 0x80000000UL 734 735 uint32_t reg, idx; 736 737 if (cpu_vendor != CPUVENDOR_VORTEX86) 738 return; 739 /* 740 * CPU model available from "Customer ID register" in 741 * North Bridge Function 0 PCI space 742 * we can't use pci_conf_read() because the PCI subsystem is not 743 * not initialised early enough 744 */ 745 746 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE | 0x90); 747 reg = inl(PCI_MODE1_DATA_REG); 748 749 if ((reg & 0xf0ffffff) != 0x30504d44) { 750 idx = 0; 751 } else { 752 idx = (reg >> 24) & 0xf; 753 } 754 755 static const char *cpu_vortex86_flavor[] = { 756 "??", "SX", "DX", "MX", "DX2", "MX+", "DX3", "EX", "EX2", 757 }; 758 idx = idx < __arraycount(cpu_vortex86_flavor) ? idx : 0; 759 snprintf(cpu_brand_string, sizeof(cpu_brand_string), "Vortex86%s", 760 cpu_vortex86_flavor[idx]); 761 762 #undef PCI_MODE1_ENABLE 763 #undef PCI_MODE1_ADDRESS_REG 764 #undef PCI_MODE1_DATA_REG 765 } 766 767 static void 768 cpu_probe_fpu_old(struct cpu_info *ci) 769 { 770 #if defined(__i386__) && !defined(XENPV) 771 772 clts(); 773 fninit(); 774 775 /* Check for 'FDIV' bug on the original Pentium */ 776 if (npx586bug1(4195835, 3145727) != 0) 777 /* NB 120+MHz cpus are not affected */ 778 i386_fpu_fdivbug = 1; 779 780 stts(); 781 #endif 782 } 783 784 static void 785 cpu_probe_fpu(struct cpu_info *ci) 786 { 787 u_int descs[4]; 788 int i; 789 790 x86_fpu_save = FPU_SAVE_FSAVE; 791 792 #ifdef i386 793 /* If we have FXSAVE/FXRESTOR, use them. */ 794 if ((ci->ci_feat_val[0] & CPUID_FXSR) == 0) { 795 i386_use_fxsave = 0; 796 cpu_probe_fpu_old(ci); 797 return; 798 } 799 800 i386_use_fxsave = 1; 801 /* 802 * If we have SSE/SSE2, enable XMM exceptions, and 803 * notify userland. 804 */ 805 if (ci->ci_feat_val[0] & CPUID_SSE) 806 i386_has_sse = 1; 807 if (ci->ci_feat_val[0] & CPUID_SSE2) 808 i386_has_sse2 = 1; 809 #else 810 /* 811 * For amd64 i386_use_fxsave, i386_has_sse and i386_has_sse2 are 812 * #defined to 1, because fxsave/sse/sse2 are always present. 813 */ 814 #endif 815 816 x86_fpu_save = FPU_SAVE_FXSAVE; 817 x86_fpu_save_size = sizeof(struct fxsave); 818 819 /* See if XSAVE is supported */ 820 if ((ci->ci_feat_val[1] & CPUID2_XSAVE) == 0) 821 return; 822 823 #ifdef XENPV 824 /* 825 * Xen kernel can disable XSAVE via "no-xsave" option, in that case 826 * the XSAVE/XRSTOR instructions become privileged and trigger 827 * supervisor trap. OSXSAVE flag seems to be reliably set according 828 * to whether XSAVE is actually available. 829 */ 830 if ((ci->ci_feat_val[1] & CPUID2_OSXSAVE) == 0) 831 return; 832 #endif 833 834 x86_fpu_save = FPU_SAVE_XSAVE; 835 836 x86_cpuid2(0x0d, 1, descs); 837 if (descs[0] & CPUID_PES1_XSAVEOPT) 838 x86_fpu_save = FPU_SAVE_XSAVEOPT; 839 840 /* 841 * Get the hardware-supported features with CPUID. 842 */ 843 x86_cpuid2(0x0d, 0, descs); 844 x86_xsave_features = (uint64_t)descs[3] << 32 | descs[0]; 845 846 /* 847 * Turn on XSAVE in CR4 so we can write to XCR0, and write to 848 * XCR0 enable only those features that NetBSD software 849 * supports. 850 * 851 * CR4_OSXSAVE support and and XCR0 access are both allowed 852 * because we tested ci->ci_feat_val[1] & CPUID2_XSAVE above. 853 * 854 * (This is redundant with cpu_init when it runs on the primary 855 * CPU, but it's harmless.) 856 */ 857 lcr4(rcr4() | CR4_OSXSAVE); 858 wrxcr(0, x86_xsave_features & XCR0_FPU); 859 860 /* 861 * Get the size of the save area with those features enabled 862 * with the second CPUID. 863 * 864 * Verify the save area requires no userland ABI change. If 865 * this panic fires, then either 866 * 867 * (a) the CPU is inconsistent with the architectural 868 * documentation of the XSAVE state sizes, or 869 * 870 * (b) NetBSD's requested features XCR0_FPU have been extended 871 * to require more state than will fit in the current value 872 * of MINSIGSTKSZ, which will need to be raised with a 873 * compatibility mechanism so that old programs compiled 874 * with the old value will continue to work (just without 875 * access to the new extended CPU state). 876 */ 877 x86_cpuid2(0x0d, 0, descs); 878 if (descs[1] > x86_fpu_save_size) { 879 if (descs[1] > XSAVE_MAX_BYTES) { 880 panic("XSAVE size >=%"PRIx32 881 " exceeds ABI maximum %zu", 882 descs[1], (size_t)XSAVE_MAX_BYTES); 883 } 884 x86_fpu_save_size = descs[1]; 885 } 886 887 /* Get component offsets and sizes for the save area */ 888 for (i = XSAVE_YMM_Hi128; i < __arraycount(x86_xsave_offsets); i++) { 889 if (x86_xsave_features & __BIT(i)) { 890 x86_cpuid2(0x0d, i, descs); 891 x86_xsave_offsets[i] = descs[1]; 892 x86_xsave_sizes[i] = descs[0]; 893 } 894 } 895 } 896 897 void 898 cpu_probe(struct cpu_info *ci) 899 { 900 u_int descs[4]; 901 int i; 902 uint32_t miscbytes; 903 uint32_t brand[12]; 904 905 if (ci == &cpu_info_primary) { 906 cpu_vendor = i386_nocpuid_cpus[cputype << 1]; 907 cpu_class = i386_nocpuid_cpus[(cputype << 1) + 1]; 908 } 909 910 if (cpuid_level < 0) { 911 /* cpuid instruction not supported */ 912 cpu_probe_fpu_old(ci); 913 return; 914 } 915 916 for (i = 0; i < __arraycount(ci->ci_feat_val); i++) { 917 ci->ci_feat_val[i] = 0; 918 } 919 920 x86_cpuid(0, descs); 921 cpuid_level = descs[0]; 922 ci->ci_max_cpuid = descs[0]; 923 924 ci->ci_vendor[0] = descs[1]; 925 ci->ci_vendor[2] = descs[2]; 926 ci->ci_vendor[1] = descs[3]; 927 ci->ci_vendor[3] = 0; 928 929 if (ci == &cpu_info_primary) { 930 if (memcmp(ci->ci_vendor, "GenuineIntel", 12) == 0) 931 cpu_vendor = CPUVENDOR_INTEL; 932 else if (memcmp(ci->ci_vendor, "AuthenticAMD", 12) == 0) 933 cpu_vendor = CPUVENDOR_AMD; 934 else if (memcmp(ci->ci_vendor, "CyrixInstead", 12) == 0) 935 cpu_vendor = CPUVENDOR_CYRIX; 936 else if (memcmp(ci->ci_vendor, "Geode by NSC", 12) == 0) 937 cpu_vendor = CPUVENDOR_CYRIX; 938 else if (memcmp(ci->ci_vendor, "CentaurHauls", 12) == 0) 939 cpu_vendor = CPUVENDOR_IDT; 940 else if (memcmp(ci->ci_vendor, "GenuineTMx86", 12) == 0) 941 cpu_vendor = CPUVENDOR_TRANSMETA; 942 else if (memcmp(ci->ci_vendor, "Vortex86 SoC", 12) == 0) 943 cpu_vendor = CPUVENDOR_VORTEX86; 944 else 945 cpu_vendor = CPUVENDOR_UNKNOWN; 946 } 947 948 if (cpuid_level >= 1) { 949 x86_cpuid(1, descs); 950 ci->ci_signature = descs[0]; 951 miscbytes = descs[1]; 952 ci->ci_feat_val[1] = descs[2]; 953 ci->ci_feat_val[0] = descs[3]; 954 955 if (ci == &cpu_info_primary) { 956 /* Determine family + class. */ 957 cpu_class = CPUID_TO_FAMILY(ci->ci_signature) 958 + (CPUCLASS_386 - 3); 959 if (cpu_class > CPUCLASS_686) 960 cpu_class = CPUCLASS_686; 961 } 962 963 /* CLFLUSH line size is next 8 bits */ 964 if (ci->ci_feat_val[0] & CPUID_CLFSH) 965 ci->ci_cflush_lsize 966 = __SHIFTOUT(miscbytes, CPUID_CLFLUSH_SIZE) << 3; 967 ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID); 968 } 969 970 /* 971 * Get the basic information from the extended cpuid leafs. 972 * These were first implemented by amd, but most of the values 973 * match with those generated by modern intel cpus. 974 */ 975 x86_cpuid(0x80000000, descs); 976 if (descs[0] >= 0x80000000) 977 ci->ci_max_ext_cpuid = descs[0]; 978 else 979 ci->ci_max_ext_cpuid = 0; 980 981 if (ci->ci_max_ext_cpuid >= 0x80000001) { 982 /* Determine the extended feature flags. */ 983 x86_cpuid(0x80000001, descs); 984 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 985 ci->ci_feat_val[2] = descs[3]; /* %edx */ 986 } 987 988 if (ci->ci_max_ext_cpuid >= 0x80000004) { 989 x86_cpuid(0x80000002, brand); 990 x86_cpuid(0x80000003, brand + 4); 991 x86_cpuid(0x80000004, brand + 8); 992 /* Skip leading spaces on brand */ 993 for (i = 0; i < 48; i++) { 994 if (((char *) brand)[i] != ' ') 995 break; 996 } 997 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 998 } 999 1000 /* 1001 * Get the structured extended features. 1002 */ 1003 if (cpuid_level >= 7) { 1004 x86_cpuid(7, descs); 1005 ci->ci_feat_val[5] = descs[1]; /* %ebx */ 1006 ci->ci_feat_val[6] = descs[2]; /* %ecx */ 1007 ci->ci_feat_val[7] = descs[3]; /* %edx */ 1008 } 1009 1010 cpu_probe_intel(ci); 1011 cpu_probe_amd(ci); 1012 cpu_probe_cyrix(ci); 1013 cpu_probe_winchip(ci); 1014 cpu_probe_c3(ci); 1015 cpu_probe_geode(ci); 1016 cpu_probe_vortex86(ci); 1017 1018 if (ci == &cpu_info_primary) { 1019 cpu_probe_fpu(ci); 1020 } 1021 1022 #ifndef XENPV 1023 x86_cpu_topology(ci); 1024 #endif 1025 1026 if (cpu_vendor != CPUVENDOR_AMD && (ci->ci_feat_val[0] & CPUID_TM) && 1027 (rdmsr(MSR_MISC_ENABLE) & (1 << 3)) == 0) { 1028 /* Enable thermal monitor 1. */ 1029 wrmsr(MSR_MISC_ENABLE, rdmsr(MSR_MISC_ENABLE) | (1<<3)); 1030 } 1031 1032 ci->ci_feat_val[0] &= ~CPUID_FEAT_BLACKLIST; 1033 if (ci == &cpu_info_primary) { 1034 /* If first. Boot Processor is the cpu_feature reference. */ 1035 for (i = 0; i < __arraycount(cpu_feature); i++) { 1036 cpu_feature[i] = ci->ci_feat_val[i]; 1037 } 1038 identify_hypervisor(); 1039 #ifndef XENPV 1040 /* Early patch of text segment. */ 1041 x86_patch(true); 1042 #endif 1043 1044 /* AES */ 1045 #ifdef __x86_64__ /* not yet implemented on i386 */ 1046 if (cpu_feature[1] & CPUID2_AESNI) 1047 aes_md_init(&aes_ni_impl); 1048 else 1049 #endif 1050 if (cpu_feature[4] & CPUID_VIA_HAS_ACE) 1051 aes_md_init(&aes_via_impl); 1052 else if (i386_has_sse && i386_has_sse2 && 1053 (cpu_feature[1] & CPUID2_SSE3) && 1054 (cpu_feature[1] & CPUID2_SSSE3)) 1055 aes_md_init(&aes_ssse3_impl); 1056 else if (i386_has_sse && i386_has_sse2) 1057 aes_md_init(&aes_sse2_4x32_impl); 1058 1059 /* ChaCha */ 1060 if (i386_has_sse && i386_has_sse2) 1061 chacha_md_init(&chacha_sse2_impl); 1062 } else { 1063 /* 1064 * If not first. Warn about cpu_feature mismatch for 1065 * secondary CPUs. 1066 */ 1067 for (i = 0; i < __arraycount(cpu_feature); i++) { 1068 if (cpu_feature[i] != ci->ci_feat_val[i]) 1069 aprint_error_dev(ci->ci_dev, 1070 "feature mismatch: cpu_feature[%d] is " 1071 "%#x, but CPU reported %#x\n", 1072 i, cpu_feature[i], ci->ci_feat_val[i]); 1073 } 1074 } 1075 } 1076 1077 /* Write what we know about the cpu to the console... */ 1078 void 1079 cpu_identify(struct cpu_info *ci) 1080 { 1081 1082 cpu_setmodel("%s %d86-class", 1083 cpu_vendor_names[cpu_vendor], cpu_class + 3); 1084 if (cpu_brand_string[0] != '\0') { 1085 aprint_normal_dev(ci->ci_dev, "%s", cpu_brand_string); 1086 } else { 1087 aprint_normal_dev(ci->ci_dev, "%s", cpu_getmodel()); 1088 if (ci->ci_data.cpu_cc_freq != 0) 1089 aprint_normal(", %dMHz", 1090 (int)(ci->ci_data.cpu_cc_freq / 1000000)); 1091 } 1092 if (ci->ci_signature != 0) 1093 aprint_normal(", id 0x%x", ci->ci_signature); 1094 aprint_normal("\n"); 1095 aprint_normal_dev(ci->ci_dev, "node %u, package %u, core %u, smt %u\n", 1096 ci->ci_numa_id, ci->ci_package_id, ci->ci_core_id, ci->ci_smt_id); 1097 if (cpu_brand_string[0] == '\0') { 1098 strlcpy(cpu_brand_string, cpu_getmodel(), 1099 sizeof(cpu_brand_string)); 1100 } 1101 if (cpu_class == CPUCLASS_386) { 1102 panic("NetBSD requires an 80486DX or later processor"); 1103 } 1104 if (cputype == CPU_486DLC) { 1105 aprint_error("WARNING: BUGGY CYRIX CACHE\n"); 1106 } 1107 1108 #if !defined(XENPV) || defined(DOM0OPS) /* on Xen PV rdmsr is for Dom0 only */ 1109 if (cpu_vendor == CPUVENDOR_AMD /* check enablement of an */ 1110 && device_unit(ci->ci_dev) == 0 /* AMD feature only once */ 1111 && ((cpu_feature[3] & CPUID_SVM) == CPUID_SVM)) { 1112 uint64_t val; 1113 1114 val = rdmsr(MSR_VMCR); 1115 if (((val & VMCR_SVMED) == VMCR_SVMED) 1116 && ((val & VMCR_LOCK) == VMCR_LOCK)) { 1117 aprint_normal_dev(ci->ci_dev, 1118 "SVM disabled by the BIOS\n"); 1119 } 1120 } 1121 #endif 1122 1123 #ifdef i386 1124 if (i386_fpu_fdivbug == 1) 1125 aprint_normal_dev(ci->ci_dev, 1126 "WARNING: Pentium FDIV bug detected!\n"); 1127 1128 if (cpu_vendor == CPUVENDOR_TRANSMETA) { 1129 u_int descs[4]; 1130 x86_cpuid(0x80860000, descs); 1131 if (descs[0] >= 0x80860007) 1132 /* Create longrun sysctls */ 1133 tmx86_init_longrun(); 1134 } 1135 #endif /* i386 */ 1136 1137 } 1138 1139 /* 1140 * Hypervisor 1141 */ 1142 vm_guest_t vm_guest = VM_GUEST_NO; 1143 1144 struct vm_name_guest { 1145 const char *name; 1146 vm_guest_t guest; 1147 }; 1148 1149 static const struct vm_name_guest vm_bios_vendors[] = { 1150 { "QEMU", VM_GUEST_VM }, /* QEMU */ 1151 { "Plex86", VM_GUEST_VM }, /* Plex86 */ 1152 { "Bochs", VM_GUEST_VM }, /* Bochs */ 1153 { "Xen", VM_GUEST_VM }, /* Xen */ 1154 { "BHYVE", VM_GUEST_VM }, /* bhyve */ 1155 { "Seabios", VM_GUEST_VM }, /* KVM */ 1156 { "innotek GmbH", VM_GUEST_VIRTUALBOX }, /* Oracle VirtualBox */ 1157 { "Generic PVH", VM_GUEST_GENPVH}, /* Generic PVH */ 1158 }; 1159 1160 static const struct vm_name_guest vm_system_products[] = { 1161 { "VMware Virtual Platform", VM_GUEST_VM }, /* VMWare VM */ 1162 { "Virtual Machine", VM_GUEST_VM }, /* Microsoft VirtualPC */ 1163 { "VirtualBox", VM_GUEST_VIRTUALBOX }, /* Sun xVM VirtualBox */ 1164 { "Parallels Virtual Platform", VM_GUEST_VM }, /* Parallels VM */ 1165 { "KVM", VM_GUEST_KVM }, /* KVM */ 1166 { "NVMM", VM_GUEST_NVMM }, /* NVMM */ 1167 }; 1168 1169 void 1170 identify_hypervisor(void) 1171 { 1172 u_int regs[6]; 1173 char hv_vendor[12]; 1174 const char *p; 1175 int i; 1176 1177 switch (vm_guest) { 1178 /* guest type already known, no bios info */ 1179 case VM_GUEST_XENPV: 1180 case VM_GUEST_XENPVH: 1181 /* The following are known from first pass */ 1182 case VM_GUEST_VMWARE: 1183 case VM_GUEST_HV: 1184 case VM_GUEST_XENHVM: 1185 case VM_GUEST_KVM: 1186 case VM_GUEST_NVMM: 1187 return; 1188 default: 1189 break; 1190 } 1191 1192 /* 1193 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1194 * http://lkml.org/lkml/2008/10/1/246 1195 * 1196 * KB1009458: Mechanisms to determine if software is running in 1197 * a VMware virtual machine 1198 * http://kb.vmware.com/kb/1009458 1199 */ 1200 if (ISSET(cpu_feature[1], CPUID2_RAZ)) { 1201 /* 1202 * don't override if vm_guest is unknown but has booted in PVH 1203 * mode, so it can attach to pv(4) in (amd64|i386)_mainbus.c 1204 */ 1205 if (vm_guest != VM_GUEST_GENPVH) 1206 vm_guest = VM_GUEST_VM; 1207 x86_cpuid(0x40000000, regs); 1208 if (regs[0] >= 0x40000000) { 1209 cpu_max_hypervisor_cpuid = regs[0]; 1210 memcpy(&hv_vendor[0], ®s[1], sizeof(*regs)); 1211 memcpy(&hv_vendor[4], ®s[2], sizeof(*regs)); 1212 memcpy(&hv_vendor[8], ®s[3], sizeof(*regs)); 1213 if (memcmp(hv_vendor, "VMwareVMware", 12) == 0) 1214 vm_guest = VM_GUEST_VMWARE; 1215 else if (memcmp(hv_vendor, "Microsoft Hv", 12) == 0) { 1216 vm_guest = VM_GUEST_HV; 1217 #if NHYPERV > 0 1218 hyperv_early_init(); 1219 #endif 1220 } else if (memcmp(hv_vendor, "KVMKVMKVM\0\0\0", 12) == 0) 1221 vm_guest = VM_GUEST_KVM; 1222 else if (memcmp(hv_vendor, "XenVMMXenVMM", 12) == 0) 1223 vm_guest = VM_GUEST_XENHVM; 1224 else if (memcmp(hv_vendor, "___ NVMM ___", 12) == 0) 1225 vm_guest = VM_GUEST_NVMM; 1226 /* FreeBSD bhyve: "bhyve bhyve " */ 1227 /* OpenBSD vmm: "OpenBSDVMM58" */ 1228 } 1229 // VirtualBox returns KVM, so keep going. 1230 if (vm_guest != VM_GUEST_KVM) 1231 return; 1232 } 1233 1234 /* 1235 * Examine SMBIOS strings for older hypervisors. 1236 */ 1237 p = pmf_get_platform("system-serial"); 1238 if (p != NULL) { 1239 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1240 vmt_hvcall(VM_CMD_GET_VERSION, regs); 1241 if (regs[1] == VM_MAGIC) { 1242 vm_guest = VM_GUEST_VMWARE; 1243 return; 1244 } 1245 } 1246 } 1247 p = pmf_get_platform("bios-vendor"); 1248 if (p != NULL) { 1249 for (i = 0; i < __arraycount(vm_bios_vendors); i++) { 1250 if (strcmp(p, vm_bios_vendors[i].name) == 0) { 1251 vm_guest = vm_bios_vendors[i].guest; 1252 return; 1253 } 1254 } 1255 } 1256 p = pmf_get_platform("system-product"); 1257 if (p != NULL) { 1258 for (i = 0; i < __arraycount(vm_system_products); i++) { 1259 if (strcmp(p, vm_system_products[i].name) == 0) { 1260 vm_guest = vm_system_products[i].guest; 1261 return; 1262 } 1263 } 1264 } 1265 } 1266
Indexes created Sun Oct 25 00:26:45 UTC 2026