1 /* $NetBSD: i386.c,v 1.152 2026/10/05 06:28:24 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.152 2026/10/05 06:28:24 andvar Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Mobile Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Mobile Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Dual-Core, Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom Z3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8a] = "Core i3/i5 L1xGx (Lakefield)", 352 [0x8c] = "11th gen Core (Tiger Lake)", 353 [0x8d] = "11th gen Core (Tiger Lake)", 354 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 355 [0x8f] = "4th gen Xeon Scalable (Sapphire Rapids)", 356 [0x96] = "Atom x6000E (Elkhart Lake)", 357 [0x97] = "12th gen Core (Alder Lake)", 358 [0x9a] = "12th gen Core (Alder Lake)", 359 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 360 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 361 [0xa5] = "10th gen Core (Comet Lake)", 362 [0xa6] = "10th gen Core (Comet Lake)", 363 [0xa7] = "11th gen Core (Rocket Lake)", 364 [0xa8] = "11th gen Core (Rocket Lake)", 365 [0xaa] = "Core Ultra 7 (Meteor Lake)", 366 [0xad] = "6th gen Intel Xeon Scalable (Granite Rapids)", 367 [0xae] = "Intel Xeon 6 SoC for Networking and Edge (Granite Rapids-D)", 368 [0xaf] = "6th gen Intel Xeon Scalable (Sierra Forest)", 369 [0xb5] = "Core Ultra 200U (Arrow Lake-U)", 370 [0xb7] = "13th gen Core (Raptor Lake)", 371 [0xba] = "13th gen Core (Raptor Lake)", 372 [0xbd] = "Core Ultra 200V (Lunar Lake-MX)", 373 [0xbe] = "Core i3-N3xx N[12]xx Nxx Atom x7xxxE (Alder Lake-N)", 374 [0xbf] = "13th gen Core (Raptor Lake)", 375 [0xc5] = "Core Ultra 200H (Arrow Lake-H)", 376 [0xc6] = "Core Ultra 200HX (Arrow Lake-HX)", 377 [0xcc] = "Core Ultra Series 3 (Panther Lake)", 378 [0xcf] = "5th gen Xeon Scalable (Emerald Rapids)", 379 [0xd5] = "Core Series 3 (Wildcat Lake)", 380 [0xdd] = "Xeon 6900E+ (Clearwater Forest)", 381 }, 382 "Pentium Pro, II or III", /* Default */ 383 NULL, 384 intel_family_new_probe, 385 intel_cpu_cacheinfo, 386 }, 387 /* Family > 6 */ 388 { 389 CPUCLASS_686, 390 { 391 0, 0, 0, 0, 0, 0, 0, 0, 392 0, 0, 0, 0, 0, 0, 0, 0, 393 }, 394 "Pentium 4", /* Default */ 395 NULL, 396 intel_family_new_probe, 397 intel_cpu_cacheinfo, 398 } } 399 }, 400 { 401 "AuthenticAMD", 402 CPUVENDOR_AMD, 403 "AMD", 404 /* Family 4 */ 405 { { 406 CPUCLASS_486, 407 { 408 0, 0, 0, "Am486DX2 W/T", 409 0, 0, 0, "Am486DX2 W/B", 410 "Am486DX4 W/T or Am5x86 W/T 150", 411 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 412 0, 0, "Am5x86 W/T 133/160", 413 "Am5x86 W/B 133/160", 414 }, 415 "Am486 or Am5x86", /* Default */ 416 NULL, 417 NULL, 418 NULL, 419 }, 420 /* Family 5 */ 421 { 422 CPUCLASS_586, 423 { 424 "K5", "K5", "K5", "K5", 0, 0, "K6", 425 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 426 "K6-2+/III+", 0, 0, 427 }, 428 "K5 or K6", /* Default */ 429 amd_family5_setup, 430 NULL, 431 amd_cpu_cacheinfo, 432 }, 433 /* Family 6 */ 434 { 435 CPUCLASS_686, 436 { 437 0, "Athlon Model 1", "Athlon Model 2", 438 "Duron", "Athlon Model 4 (Thunderbird)", 439 0, "Athlon", "Duron", "Athlon", 0, 440 "Athlon", 0, 0, 0, 0, 0, 441 }, 442 "K7 (Athlon)", /* Default */ 443 NULL, 444 amd_family6_probe, 445 amd_cpu_cacheinfo, 446 }, 447 /* Family > 6 */ 448 { 449 CPUCLASS_686, 450 { 451 0, 0, 0, 0, 0, 0, 0, 0, 452 0, 0, 0, 0, 0, 0, 0, 0, 453 }, 454 "Unknown K8 (Athlon)", /* Default */ 455 NULL, 456 amd_family6_probe, 457 amd_cpu_cacheinfo, 458 } } 459 }, 460 { 461 "CyrixInstead", 462 CPUVENDOR_CYRIX, 463 "Cyrix", 464 /* Family 4 */ 465 { { 466 CPUCLASS_486, 467 { 468 0, 0, 0, 469 "MediaGX", 470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 471 }, 472 "486", /* Default */ 473 cyrix6x86_cpu_setup, /* XXX ?? */ 474 NULL, 475 NULL, 476 }, 477 /* Family 5 */ 478 { 479 CPUCLASS_586, 480 { 481 0, 0, "6x86", "6x86", 482 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 484 }, 485 "6x86", /* Default */ 486 cyrix6x86_cpu_setup, 487 NULL, 488 NULL, 489 }, 490 /* Family 6 */ 491 { 492 CPUCLASS_686, 493 { 494 "6x86MX/MII", "MII/MIIv", 0, 0, 0, "III (Joshua)", 0, 0, 495 0, 0, 0, 0, 0, 0, 0, 0, 496 }, 497 "6x86MX", /* Default */ 498 cyrix6x86_cpu_setup, 499 NULL, 500 NULL, 501 }, 502 /* Family > 6 */ 503 { 504 CPUCLASS_686, 505 { 506 0, 0, 0, 0, 0, 0, 0, 0, 507 0, 0, 0, 0, 0, 0, 0, 0, 508 }, 509 "Unknown 6x86MX", /* Default */ 510 NULL, 511 NULL, 512 NULL, 513 } } 514 }, 515 { /* MediaGX is now owned by National Semiconductor */ 516 "Geode by NSC", 517 CPUVENDOR_CYRIX, /* XXX */ 518 "National Semiconductor", 519 /* Family 4, NSC never had any of these */ 520 { { 521 CPUCLASS_486, 522 { 523 0, 0, 0, 0, 0, 0, 0, 0, 524 0, 0, 0, 0, 0, 0, 0, 0, 525 }, 526 "486 compatible", /* Default */ 527 NULL, 528 NULL, 529 NULL, 530 }, 531 /* Family 5: Geode family, formerly MediaGX */ 532 { 533 CPUCLASS_586, 534 { 535 0, 0, 0, 0, 536 "Geode GX1", 537 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 538 }, 539 "Geode", /* Default */ 540 cyrix6x86_cpu_setup, 541 NULL, 542 amd_cpu_cacheinfo, 543 }, 544 /* Family 6, not yet available from NSC */ 545 { 546 CPUCLASS_686, 547 { 548 0, 0, 0, 0, 0, 0, 0, 0, 549 0, 0, 0, 0, 0, 0, 0, 0, 550 }, 551 "Pentium Pro compatible", /* Default */ 552 NULL, 553 NULL, 554 NULL, 555 }, 556 /* Family > 6, not yet available from NSC */ 557 { 558 CPUCLASS_686, 559 { 560 0, 0, 0, 0, 0, 0, 0, 0, 561 0, 0, 0, 0, 0, 0, 0, 0, 562 }, 563 "Pentium Pro compatible", /* Default */ 564 NULL, 565 NULL, 566 NULL, 567 } } 568 }, 569 { 570 "CentaurHauls", 571 CPUVENDOR_IDT, 572 "IDT", 573 /* Family 4, IDT never had any of these */ 574 { { 575 CPUCLASS_486, 576 { 577 0, 0, 0, 0, 0, 0, 0, 0, 578 0, 0, 0, 0, 0, 0, 0, 0, 579 }, 580 "486 compatible", /* Default */ 581 NULL, 582 NULL, 583 NULL, 584 }, 585 /* Family 5 */ 586 { 587 CPUCLASS_586, 588 { 589 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 590 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 591 }, 592 "WinChip", /* Default */ 593 winchip_cpu_setup, 594 NULL, 595 NULL, 596 }, 597 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 598 { 599 CPUCLASS_686, 600 { 601 0, 0, 0, 0, 0, 0, "C3 Samuel", 602 "C3 Samuel 2/Ezra", "C3 Ezra-T", 603 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 604 0, "VIA Nano", 605 }, 606 "Unknown VIA/IDT", /* Default */ 607 NULL, 608 via_cpu_probe, 609 via_cpu_cacheinfo, 610 }, 611 /* Family > 6, Zhaoxin CPUs */ 612 { 613 CPUCLASS_686, 614 { 615 0, 0, 0, 0, 0, 0, 0, 0, 616 0, 0, 0, 0, 0, 0, 0, 0, 617 }, 618 "KaiXian/KaiSheng", /* Default */ 619 NULL, 620 via_cpu_probe, 621 via_cpu_cacheinfo, 622 } } 623 }, 624 { 625 "GenuineTMx86", 626 CPUVENDOR_TRANSMETA, 627 "Transmeta", 628 /* Family 4, Transmeta never had any of these */ 629 { { 630 CPUCLASS_486, 631 { 632 0, 0, 0, 0, 0, 0, 0, 0, 633 0, 0, 0, 0, 0, 0, 0, 0, 634 }, 635 "486 compatible", /* Default */ 636 NULL, 637 NULL, 638 NULL, 639 }, 640 /* Family 5 */ 641 { 642 CPUCLASS_586, 643 { 644 0, 0, 0, 0, 0, 0, 0, 0, 645 0, 0, 0, 0, 0, 0, 0, 0, 646 }, 647 "Crusoe", /* Default */ 648 NULL, 649 NULL, 650 transmeta_cpu_info, 651 }, 652 /* Family 6, not yet available from Transmeta */ 653 { 654 CPUCLASS_686, 655 { 656 0, 0, 0, 0, 0, 0, 0, 0, 657 0, 0, 0, 0, 0, 0, 0, 0, 658 }, 659 "Pentium Pro compatible", /* Default */ 660 NULL, 661 NULL, 662 NULL, 663 }, 664 /* Family > 6 */ 665 { 666 CPUCLASS_686, 667 { 668 0, 0, 0, 0, 0, 0, 0, 0, 669 0, 0, 0, 0, 0, 0, 0, 0, 670 }, 671 "Efficeon", /* Default */ 672 NULL, 673 NULL, 674 transmeta_cpu_info, 675 } } 676 } 677 }; 678 679 /* 680 * disable the TSC such that we don't use the TSC in microtime(9) 681 * because some CPUs got the implementation wrong. 682 */ 683 static void 684 disable_tsc(struct cpu_info *ci) 685 { 686 if (ci->ci_feat_val[0] & CPUID_TSC) { 687 ci->ci_feat_val[0] &= ~CPUID_TSC; 688 aprint_error("WARNING: broken TSC disabled\n"); 689 } 690 } 691 692 static void 693 amd_family5_setup(struct cpu_info *ci) 694 { 695 696 switch (ci->ci_model) { 697 case 0: /* AMD-K5 Model 0 */ 698 /* 699 * According to the AMD Processor Recognition App Note, 700 * the AMD-K5 Model 0 uses the wrong bit to indicate 701 * support for global PTEs, instead using bit 9 (APIC) 702 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 703 */ 704 if (ci->ci_feat_val[0] & CPUID_APIC) 705 ci->ci_feat_val[0] = 706 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 707 /* 708 * XXX But pmap_pg_g is already initialized -- need to kick 709 * XXX the pmap somehow. How does the MP branch do this? 710 */ 711 break; 712 } 713 } 714 715 static void 716 cyrix6x86_cpu_setup(struct cpu_info *ci) 717 { 718 719 /* 720 * Do not disable the TSC on the Geode GX, it's reported to 721 * work fine. 722 */ 723 if (ci->ci_signature != 0x552) 724 disable_tsc(ci); 725 } 726 727 static void 728 winchip_cpu_setup(struct cpu_info *ci) 729 { 730 switch (ci->ci_model) { 731 case 4: /* WinChip C6 */ 732 disable_tsc(ci); 733 } 734 } 735 736 737 static const char * 738 intel_family6_name(struct cpu_info *ci) 739 { 740 const char *ret = NULL; 741 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 742 743 if (ci->ci_model == 5) { 744 switch (l2cache) { 745 case 0: 746 case 128 * 1024: 747 ret = "Celeron (Covington)"; 748 break; 749 case 256 * 1024: 750 ret = "Mobile Pentium II (Dixon)"; 751 break; 752 case 512 * 1024: 753 ret = "Pentium II"; 754 break; 755 case 1 * 1024 * 1024: 756 case 2 * 1024 * 1024: 757 ret = "Pentium II Xeon"; 758 break; 759 } 760 } else if (ci->ci_model == 6) { 761 switch (l2cache) { 762 case 256 * 1024: 763 case 512 * 1024: 764 ret = "Mobile Pentium II"; 765 break; 766 } 767 } else if (ci->ci_model == 7) { 768 switch (l2cache) { 769 case 512 * 1024: 770 ret = "Pentium III"; 771 break; 772 case 1 * 1024 * 1024: 773 case 2 * 1024 * 1024: 774 ret = "Pentium III Xeon"; 775 break; 776 } 777 } else if (ci->ci_model >= 8) { 778 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 779 switch (ci->ci_brand_id) { 780 case 0x3: 781 if (ci->ci_signature == 0x6B1) 782 ret = "Celeron"; 783 break; 784 case 0x8: 785 if (ci->ci_signature >= 0xF13) 786 ret = "genuine processor"; 787 break; 788 case 0xB: 789 if (ci->ci_signature >= 0xF13) 790 ret = "Xeon MP"; 791 break; 792 case 0xE: 793 if (ci->ci_signature < 0xF13) 794 ret = "Xeon"; 795 break; 796 } 797 if (ret == NULL) 798 ret = i386_intel_brand[ci->ci_brand_id]; 799 } 800 } 801 802 return ret; 803 } 804 805 /* 806 * Identify AMD64 CPU names from cpuid. 807 * 808 * Based on: 809 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 810 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 811 * "Revision Guide for AMD NPT Family 0Fh Processors" 812 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 813 * and other miscellaneous reports. 814 * 815 * This is all rather pointless, these are cross 'brand' since the raw 816 * silicon is shared. 817 */ 818 static const char * 819 amd_amd64_name(struct cpu_info *ci) 820 { 821 static char family_str[32]; 822 823 /* Only called if family >= 15 */ 824 825 switch (ci->ci_family) { 826 case 15: 827 switch (ci->ci_model) { 828 case 0x21: /* rev JH-E1/E6 */ 829 case 0x41: /* rev JH-F2 */ 830 return "Dual-Core Opteron"; 831 case 0x23: /* rev JH-E6 (Toledo) */ 832 return "Dual-Core Opteron or Athlon 64 X2"; 833 case 0x43: /* rev JH-F2 (Windsor) */ 834 return "Athlon 64 FX or Athlon 64 X2"; 835 case 0x24: /* rev SH-E5 (Lancaster?) */ 836 return "Mobile Athlon 64 or Turion 64"; 837 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 838 return "Opteron or Athlon 64 FX"; 839 case 0x15: /* rev SH-D0 */ 840 case 0x25: /* rev SH-E4 */ 841 return "Opteron"; 842 case 0x27: /* rev DH-E4, SH-E4 */ 843 return "Athlon 64 or Athlon 64 FX or Opteron"; 844 case 0x48: /* rev BH-F2 */ 845 case 0x68: /* rev BH-G1 (Tyler) */ 846 return "Turion 64 X2 or Athlon 64 X2"; 847 case 0x4c: /* rev DH-F2 (Richmond) */ 848 return "Mobile Athlon 64 or Mobile Sempron"; 849 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 850 case 0x07: /* rev SH-CG (ClawHammer) */ 851 case 0x0b: /* rev CH-CG */ 852 case 0x14: /* rev SH-D0 */ 853 case 0x17: /* rev SH-D0 */ 854 case 0x1b: /* rev CH-D0 */ 855 return "Athlon 64"; 856 case 0x2b: /* rev BH-E4 (Manchester) */ 857 case 0x4b: /* rev BH-F2 (Windsor) */ 858 return "Athlon 64 X2"; 859 case 0x6b: /* rev BH-G1 (Brisbane) */ 860 return "Athlon X2 or Athlon 64 X2"; 861 case 0x08: /* rev CH-CG */ 862 case 0x0c: /* rev DH-CG (Newcastle) */ 863 case 0x0e: /* rev DH-CG (Newcastle?) */ 864 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 865 case 0x18: /* rev CH-D0 */ 866 case 0x1c: /* rev DH-D0 (Winchester) */ 867 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 868 case 0x2c: /* rev DH-E3/E6 */ 869 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 870 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 871 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 872 case 0x6f: /* rev DH-G1 (Lima) */ 873 case 0x7f: /* rev DH-G2 (Lima) */ 874 return "Athlon 64 or Sempron"; 875 case 0x7c: /* rev DH-G2 (Sherman) */ 876 return "Athlon 64 or Mobile Sempron"; 877 case 0xc1: /* rev JH-F3 (Windsor FX) */ 878 return "Athlon 64 FX"; 879 default: 880 break; 881 } 882 return "Unknown AMD64 CPU"; 883 884 #if 0 885 case 16: 886 return "Family 10h"; 887 case 17: 888 return "Family 11h"; 889 case 18: 890 return "Family 12h"; 891 case 19: 892 return "Family 14h"; 893 case 20: 894 return "Family 15h"; 895 #endif 896 897 default: 898 break; 899 } 900 901 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 902 return family_str; 903 } 904 905 static void 906 intel_family_new_probe(struct cpu_info *ci) 907 { 908 uint32_t descs[4]; 909 910 x86_cpuid(0x80000000, descs); 911 912 /* 913 * Determine extended feature flags. 914 */ 915 if (descs[0] >= 0x80000001) { 916 x86_cpuid(0x80000001, descs); 917 ci->ci_feat_val[2] |= descs[3]; 918 ci->ci_feat_val[3] |= descs[2]; 919 } 920 } 921 922 static void 923 via_cpu_probe(struct cpu_info *ci) 924 { 925 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 926 u_int descs[4]; 927 u_int lfunc; 928 929 /* 930 * Determine the largest extended function value. 931 */ 932 x86_cpuid(0x80000000, descs); 933 lfunc = descs[0]; 934 935 /* 936 * Determine the extended feature flags. 937 */ 938 if (lfunc >= 0x80000001) { 939 x86_cpuid(0x80000001, descs); 940 ci->ci_feat_val[2] |= descs[3]; 941 } 942 943 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 944 return; 945 946 /* Nehemiah or Esther */ 947 x86_cpuid(0xc0000000, descs); 948 lfunc = descs[0]; 949 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 950 return; 951 952 x86_cpuid(0xc0000001, descs); 953 lfunc = descs[3]; 954 ci->ci_feat_val[4] = lfunc; 955 } 956 957 static void 958 amd_family6_probe(struct cpu_info *ci) 959 { 960 uint32_t descs[4]; 961 char *p; 962 size_t i; 963 964 x86_cpuid(0x80000000, descs); 965 966 /* 967 * Determine the extended feature flags. 968 */ 969 if (descs[0] >= 0x80000001) { 970 x86_cpuid(0x80000001, descs); 971 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 972 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 973 } 974 975 if (*cpu_brand_string == '\0') 976 return; 977 978 for (i = 1; i < __arraycount(amd_brand); i++) 979 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 980 ci->ci_brand_id = i; 981 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 982 break; 983 } 984 } 985 986 static void 987 intel_cpu_cacheinfo(struct cpu_info *ci) 988 { 989 const struct x86_cache_info *cai; 990 u_int descs[4]; 991 int iterations, i, j; 992 int type, level, ways, linesize, sets; 993 int caitype = -1; 994 uint8_t desc; 995 996 /* Return if the cpu is old pre-cpuid instruction cpu */ 997 if (ci->ci_cpu_type >= 0) 998 return; 999 1000 if (ci->ci_max_cpuid < 2) 1001 return; 1002 1003 /* 1004 * Parse the cache info from `cpuid leaf 2', if we have it. 1005 * XXX This is kinda ugly, but hey, so is the architecture... 1006 */ 1007 x86_cpuid(2, descs); 1008 iterations = descs[0] & 0xff; 1009 while (iterations-- > 0) { 1010 for (i = 0; i < 4; i++) { 1011 if (descs[i] & 0x80000000) 1012 continue; 1013 for (j = 0; j < 4; j++) { 1014 /* 1015 * The least significant byte in EAX 1016 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1017 * it should be ignored. 1018 */ 1019 if (i == 0 && j == 0) 1020 continue; 1021 desc = (descs[i] >> (j * 8)) & 0xff; 1022 if (desc == 0) 1023 continue; 1024 cai = cpu_cacheinfo_lookup( 1025 intel_cpuid_cache_info, desc); 1026 if (cai != NULL) 1027 ci->ci_cinfo[cai->cai_index] = *cai; 1028 else if ((verbose != 0) && (desc != 0xff) 1029 && (desc != 0xfe)) 1030 aprint_error_dev(ci->ci_dev, "error:" 1031 " Unknown cacheinfo desc %02x\n", 1032 desc); 1033 } 1034 } 1035 x86_cpuid(2, descs); 1036 } 1037 1038 if (ci->ci_max_cpuid < 4) 1039 return; 1040 1041 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1042 cpu_dcp_cacheinfo(ci, 4); 1043 1044 if (ci->ci_max_cpuid < 0x18) 1045 return; 1046 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1047 x86_cpuid(0x18, descs); 1048 iterations = descs[0]; 1049 for (i = 0; i <= iterations; i++) { 1050 uint32_t pgsize; 1051 bool full; 1052 1053 x86_cpuid2(0x18, i, descs); 1054 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1055 if (type == CPUID_DATP_TCTYPE_N) 1056 continue; 1057 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1058 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1059 switch (level) { 1060 case 1: 1061 if (type == CPUID_DATP_TCTYPE_I) { 1062 switch (pgsize) { 1063 case CPUID_DATP_PGSIZE_4KB: 1064 caitype = CAI_ITLB; 1065 break; 1066 case CPUID_DATP_PGSIZE_2MB 1067 | CPUID_DATP_PGSIZE_4MB: 1068 caitype = CAI_ITLB2; 1069 break; 1070 case CPUID_DATP_PGSIZE_1GB: 1071 caitype = CAI_L1_1GBITLB; 1072 break; 1073 default: 1074 aprint_error_dev(ci->ci_dev, 1075 "error: unknown ITLB size (%d)\n", 1076 pgsize); 1077 caitype = CAI_ITLB; 1078 break; 1079 } 1080 } else if (type == CPUID_DATP_TCTYPE_D) { 1081 switch (pgsize) { 1082 case CPUID_DATP_PGSIZE_4KB: 1083 caitype = CAI_DTLB; 1084 break; 1085 case CPUID_DATP_PGSIZE_2MB 1086 | CPUID_DATP_PGSIZE_4MB: 1087 caitype = CAI_DTLB2; 1088 break; 1089 case CPUID_DATP_PGSIZE_1GB: 1090 caitype = CAI_L1_1GBDTLB; 1091 break; 1092 default: 1093 aprint_error_dev(ci->ci_dev, 1094 "error: unknown DTLB size (%d)\n", 1095 pgsize); 1096 caitype = CAI_DTLB; 1097 break; 1098 } 1099 } else if (type == CPUID_DATP_TCTYPE_L) 1100 caitype = CAI_L1_LD_TLB; 1101 else if (type == CPUID_DATP_TCTYPE_S) 1102 caitype = CAI_L1_ST_TLB; 1103 else 1104 caitype = -1; 1105 break; 1106 case 2: 1107 if (type == CPUID_DATP_TCTYPE_I) 1108 caitype = CAI_L2_ITLB; 1109 else if (type == CPUID_DATP_TCTYPE_D) 1110 caitype = CAI_L2_DTLB; 1111 else if (type == CPUID_DATP_TCTYPE_U) { 1112 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1113 caitype = CAI_L2_STLB; 1114 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1115 | CPUID_DATP_PGSIZE_2MB)) 1116 caitype = CAI_L2_STLB2; 1117 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1118 | CPUID_DATP_PGSIZE_4MB)) 1119 caitype = CAI_L2_STLB3; 1120 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1121 != 0) { 1122 /* FIXME: 1GB max TLB */ 1123 caitype = CAI_L2_STLB3; 1124 linesize = 1024 * 1024 * 1024; 1125 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1126 != 0) { 1127 /* FIXME: 4MB max TLB */ 1128 caitype = CAI_L2_STLB3; 1129 linesize = 4 * 1024 * 1024; 1130 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1131 != 0) { 1132 /* FIXME: 2MB max TLB */ 1133 caitype = CAI_L2_STLB2; 1134 linesize = 2 * 1024 * 1024; 1135 } else { 1136 aprint_error_dev(ci->ci_dev, "error: " 1137 "unknown L2 STLB size (%d)\n", 1138 pgsize); 1139 caitype = CAI_L2_STLB; 1140 linesize = 4 * 1024; 1141 } 1142 } else 1143 caitype = -1; 1144 break; 1145 case 3: 1146 /* XXX need work for L3 TLB */ 1147 caitype = CAI_L3CACHE; 1148 break; 1149 default: 1150 caitype = -1; 1151 break; 1152 } 1153 if (caitype == -1) { 1154 aprint_error_dev(ci->ci_dev, 1155 "error: unknown TLB level&type (%d & %d)\n", 1156 level, type); 1157 continue; 1158 } 1159 switch (pgsize) { 1160 case CPUID_DATP_PGSIZE_4KB: 1161 linesize = 4 * 1024; 1162 break; 1163 case CPUID_DATP_PGSIZE_2MB: 1164 linesize = 2 * 1024 * 1024; 1165 break; 1166 case CPUID_DATP_PGSIZE_4MB: 1167 linesize = 4 * 1024 * 1024; 1168 break; 1169 case CPUID_DATP_PGSIZE_1GB: 1170 linesize = 1024 * 1024 * 1024; 1171 break; 1172 default: 1173 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1174 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1175 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1176 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1177 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1178 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1179 else 1180 linesize = 4 * 1024; /* XXX default to 4K */ 1181 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1182 "this info can't print correctly " 1183 "(level = %d, pgsize = %d)\n", 1184 level, pgsize); 1185 break; 1186 } 1187 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1188 sets = descs[2]; 1189 full = descs[3] & CPUID_DATP_FULLASSOC; 1190 ci->ci_cinfo[caitype].cai_totalsize 1191 = ways * sets; /* entries */ 1192 ci->ci_cinfo[caitype].cai_associativity 1193 = full ? 0xff : ways; 1194 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1195 } 1196 } 1197 1198 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1199 AMD_L2L3CACHE_INFO; 1200 1201 static void 1202 amd_cpu_cacheinfo(struct cpu_info *ci) 1203 { 1204 const struct x86_cache_info *cp; 1205 struct x86_cache_info *cai; 1206 u_int descs[4]; 1207 u_int lfunc; 1208 bool l2tlbx32 = false; 1209 1210 /* K5 model 0 has none of this info. */ 1211 if (ci->ci_family == 5 && ci->ci_model == 0) 1212 return; 1213 1214 /* Determine the largest extended function value. */ 1215 x86_cpuid(0x80000000, descs); 1216 lfunc = descs[0]; 1217 1218 if (lfunc < 0x80000005) 1219 return; 1220 1221 /* Determine L1 cache/TLB info. */ 1222 x86_cpuid(0x80000005, descs); 1223 1224 /* K6-III and higher have large page TLBs. */ 1225 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1226 cai = &ci->ci_cinfo[CAI_ITLB2]; 1227 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1228 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1229 cai->cai_linesize = largepagesize; 1230 1231 cai = &ci->ci_cinfo[CAI_DTLB2]; 1232 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1233 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1234 cai->cai_linesize = largepagesize; 1235 } 1236 1237 cai = &ci->ci_cinfo[CAI_ITLB]; 1238 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1239 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1240 cai->cai_linesize = (4 * 1024); 1241 1242 cai = &ci->ci_cinfo[CAI_DTLB]; 1243 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1244 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1245 cai->cai_linesize = (4 * 1024); 1246 1247 cai = &ci->ci_cinfo[CAI_DCACHE]; 1248 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1249 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1250 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1251 1252 cai = &ci->ci_cinfo[CAI_ICACHE]; 1253 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1254 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1255 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1256 1257 if (lfunc < 0x80000006) 1258 return; 1259 1260 /* Determine L2 cache/TLB info. */ 1261 if (lfunc >= 0x80000021) { 1262 x86_cpuid(0x80000021, descs); 1263 l2tlbx32 = descs[0] & CPUID_AMDEXT2_L2TLBSIZEX32; 1264 } 1265 x86_cpuid(0x80000006, descs); 1266 1267 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1268 cai->cai_totalsize = 1269 AMD_L2_EBX_IUTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1); 1270 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1271 cai->cai_linesize = (4 * 1024); 1272 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1273 cai->cai_associativity); 1274 if (cp != NULL) 1275 cai->cai_associativity = cp->cai_associativity; 1276 else 1277 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1278 1279 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1280 cai->cai_totalsize = 1281 AMD_L2_EAX_IUTLB_ENTRIES(descs[0]) * (l2tlbx32 ? 32 : 1); 1282 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1283 cai->cai_linesize = largepagesize; 1284 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1285 cai->cai_associativity); 1286 if (cp != NULL) 1287 cai->cai_associativity = cp->cai_associativity; 1288 else 1289 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1290 1291 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1292 cai->cai_totalsize = 1293 AMD_L2_EBX_DTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1); 1294 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1295 cai->cai_linesize = (4 * 1024); 1296 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1297 cai->cai_associativity); 1298 if (cp != NULL) 1299 cai->cai_associativity = cp->cai_associativity; 1300 else 1301 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1302 1303 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1304 cai->cai_totalsize = 1305 AMD_L2_EAX_DTLB_ENTRIES(descs[0]) * (l2tlbx32 ? 32 : 1); 1306 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1307 cai->cai_linesize = largepagesize; 1308 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1309 cai->cai_associativity); 1310 if (cp != NULL) 1311 cai->cai_associativity = cp->cai_associativity; 1312 else 1313 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1314 1315 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1316 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1317 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1318 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1319 1320 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1321 cai->cai_associativity); 1322 if (cp != NULL) 1323 cai->cai_associativity = cp->cai_associativity; 1324 else 1325 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1326 1327 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1328 if (ci->ci_family >= 0x10) { 1329 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1330 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1331 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1332 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1333 1334 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1335 cai->cai_associativity); 1336 if (cp != NULL) 1337 cai->cai_associativity = cp->cai_associativity; 1338 else 1339 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1340 } 1341 1342 if (lfunc < 0x80000019) 1343 return; 1344 1345 /* Determine 1GB TLB info. */ 1346 x86_cpuid(0x80000019, descs); 1347 1348 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1349 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1350 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1351 cai->cai_linesize = (1024 * 1024 * 1024); 1352 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1353 cai->cai_associativity); 1354 if (cp != NULL) 1355 cai->cai_associativity = cp->cai_associativity; 1356 else 1357 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1358 1359 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1360 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1361 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1362 cai->cai_linesize = (1024 * 1024 * 1024); 1363 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1364 cai->cai_associativity); 1365 if (cp != NULL) 1366 cai->cai_associativity = cp->cai_associativity; 1367 else 1368 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1369 1370 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1371 cai->cai_totalsize = 1372 AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1); 1373 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1374 cai->cai_linesize = (1024 * 1024 * 1024); 1375 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1376 cai->cai_associativity); 1377 if (cp != NULL) 1378 cai->cai_associativity = cp->cai_associativity; 1379 else 1380 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1381 1382 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1383 cai->cai_totalsize = 1384 AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1); 1385 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1386 cai->cai_linesize = (1024 * 1024 * 1024); 1387 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1388 cai->cai_associativity); 1389 if (cp != NULL) 1390 cai->cai_associativity = cp->cai_associativity; 1391 else 1392 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1393 1394 if (lfunc < 0x8000001d) 1395 return; 1396 1397 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1398 cpu_dcp_cacheinfo(ci, 0x8000001d); 1399 } 1400 1401 static void 1402 via_cpu_cacheinfo(struct cpu_info *ci) 1403 { 1404 const struct x86_cache_info *cp; 1405 struct x86_cache_info *cai; 1406 int stepping; 1407 u_int descs[4]; 1408 u_int lfunc; 1409 1410 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1411 1412 /* 1413 * Determine the largest extended function value. 1414 */ 1415 x86_cpuid(0x80000000, descs); 1416 lfunc = descs[0]; 1417 1418 /* 1419 * Determine L1 cache/TLB info. 1420 */ 1421 if (lfunc < 0x80000005) { 1422 /* No L1 cache info available. */ 1423 return; 1424 } 1425 1426 x86_cpuid(0x80000005, descs); 1427 1428 cai = &ci->ci_cinfo[CAI_ITLB]; 1429 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1430 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1431 cai->cai_linesize = (4 * 1024); 1432 1433 cai = &ci->ci_cinfo[CAI_DTLB]; 1434 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1435 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1436 cai->cai_linesize = (4 * 1024); 1437 1438 cai = &ci->ci_cinfo[CAI_DCACHE]; 1439 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1440 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1441 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1442 if (ci->ci_model == 9 && stepping == 8) { 1443 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1444 cai->cai_associativity = 2; 1445 } 1446 1447 cai = &ci->ci_cinfo[CAI_ICACHE]; 1448 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1449 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1450 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1451 if (ci->ci_model == 9 && stepping == 8) { 1452 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1453 cai->cai_associativity = 2; 1454 } 1455 1456 /* 1457 * Determine L2 cache/TLB info. 1458 */ 1459 if (lfunc < 0x80000006) { 1460 /* No L2 cache info available. */ 1461 return; 1462 } 1463 1464 x86_cpuid(0x80000006, descs); 1465 1466 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1467 if (ci->ci_model < 9) { 1468 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1469 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1470 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1471 return; 1472 } 1473 1474 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1475 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1476 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1477 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1478 cai->cai_associativity); 1479 if (cp != NULL) 1480 cai->cai_associativity = cp->cai_associativity; 1481 else 1482 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1483 1484 if (ci->ci_max_cpuid < 4) 1485 return; 1486 1487 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1488 cpu_dcp_cacheinfo(ci, 4); 1489 } 1490 1491 static void 1492 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1493 { 1494 u_int descs[4]; 1495 1496 x86_cpuid(0x80860007, descs); 1497 *frequency = descs[0]; 1498 *voltage = descs[1]; 1499 *percentage = descs[2]; 1500 } 1501 1502 static void 1503 transmeta_cpu_info(struct cpu_info *ci) 1504 { 1505 u_int descs[4], nreg; 1506 u_int frequency, voltage, percentage, revision; 1507 1508 x86_cpuid(0x80860000, descs); 1509 nreg = descs[0]; 1510 if (nreg >= 0x80860001) { 1511 x86_cpuid(0x80860001, descs); 1512 revision = descs[1]; 1513 1514 /* 1515 * On Efficeon the hardware revision is in cpuid leaf 0x80860002 1516 * register EAX, indicated by the value 0x02000000 here. 1517 */ 1518 if (revision != 0x02000000) 1519 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1520 (revision >> 24) & 0xff, 1521 (revision >> 16) & 0xff, 1522 (revision >> 8) & 0xff, 1523 revision & 0xff); 1524 } 1525 if (nreg >= 0x80860002) { 1526 x86_cpuid(0x80860002, descs); 1527 1528 /* 1529 * Efficeon hardware revision format is described in 1530 * https://www.sandpile.org/x86/cpuid.htm#leaf_8086_0002h 1531 * https://web.archive.org/web/20260925233921/https://www.sandpile.org/x86/cpuid.htm#leaf_8086_0002h 1532 * Major revision is bits 31..29, minor is bits 28..25. 1533 * Bits 11..8 encode the package type. 1534 * All other bits are reserved. 1535 */ 1536 if (revision == 0x02000000) 1537 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u (0x%08x)\n", 1538 descs[0] >> 29, (descs[0] >> 25) & 0xf, descs[0]); 1539 1540 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1541 (descs[1] >> 24) & 0xff, 1542 (descs[1] >> 16) & 0xff, 1543 (descs[1] >> 8) & 0xff, 1544 descs[1] & 0xff, 1545 descs[2]); 1546 } 1547 if (nreg >= 0x80860006) { 1548 union { 1549 char text[65]; 1550 u_int descs[4][4]; 1551 } info; 1552 int i; 1553 1554 for (i=0; i<4; i++) { 1555 x86_cpuid(0x80860003 + i, info.descs[i]); 1556 } 1557 info.text[64] = '\0'; 1558 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1559 } 1560 1561 if (nreg >= 0x80860007) { 1562 tmx86_get_longrun_status(&frequency, 1563 &voltage, &percentage); 1564 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1565 frequency, voltage, percentage); 1566 } 1567 } 1568 1569 static void 1570 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1571 { 1572 u_int descs[4]; 1573 int i; 1574 uint32_t brand[12]; 1575 1576 memset(ci, 0, sizeof(*ci)); 1577 ci->ci_dev = cpuname; 1578 1579 ci->ci_cpu_type = x86_identify(); 1580 if (ci->ci_cpu_type >= 0) { 1581 /* Old pre-cpuid instruction cpu */ 1582 ci->ci_max_cpuid = -1; 1583 return; 1584 } 1585 1586 /* 1587 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1588 * function. 1589 */ 1590 1591 /* 1592 * Fn0000_0000: 1593 * - Save cpuid max level. 1594 * - Save vendor string. 1595 */ 1596 x86_cpuid(0, descs); 1597 ci->ci_max_cpuid = descs[0]; 1598 /* Save vendor string */ 1599 ci->ci_vendor[0] = descs[1]; 1600 ci->ci_vendor[2] = descs[2]; 1601 ci->ci_vendor[1] = descs[3]; 1602 ci->ci_vendor[3] = 0; 1603 1604 /* 1605 * Fn8000_0000: 1606 * - Get cpuid extended function's max level. 1607 */ 1608 x86_cpuid(0x80000000, descs); 1609 if (descs[0] >= 0x80000000) 1610 ci->ci_max_ext_cpuid = descs[0]; 1611 else { 1612 /* Set lower value than 0x80000000 */ 1613 ci->ci_max_ext_cpuid = 0; 1614 } 1615 1616 /* 1617 * Fn8000_000[2-4]: 1618 * - Save brand string. 1619 */ 1620 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1621 x86_cpuid(0x80000002, brand); 1622 x86_cpuid(0x80000003, brand + 4); 1623 x86_cpuid(0x80000004, brand + 8); 1624 for (i = 0; i < 48; i++) 1625 if (((char *) brand)[i] != ' ') 1626 break; 1627 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1628 } 1629 1630 if (ci->ci_max_cpuid < 1) 1631 return; 1632 1633 /* 1634 * Fn0000_0001: 1635 * - Get CPU family, model and stepping (from eax). 1636 * - Initial local APIC ID and brand ID (from ebx) 1637 * - CPUID2 (from ecx) 1638 * - CPUID (from edx) 1639 */ 1640 x86_cpuid(1, descs); 1641 ci->ci_signature = descs[0]; 1642 1643 /* Extract full family/model values */ 1644 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1645 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1646 1647 /* Brand is low order 8 bits of ebx */ 1648 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1649 /* Initial local APIC ID */ 1650 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1651 1652 ci->ci_feat_val[1] = descs[2]; 1653 ci->ci_feat_val[0] = descs[3]; 1654 1655 if (ci->ci_max_cpuid < 3) 1656 return; 1657 1658 /* 1659 * If the processor serial number misfeature is present and supported, 1660 * extract it here. 1661 */ 1662 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1663 ci->ci_cpu_serial[0] = ci->ci_signature; 1664 x86_cpuid(3, descs); 1665 ci->ci_cpu_serial[2] = descs[2]; 1666 ci->ci_cpu_serial[1] = descs[3]; 1667 } 1668 1669 if (ci->ci_max_cpuid < 0x7) 1670 return; 1671 1672 x86_cpuid(7, descs); 1673 ci->ci_feat_val[5] = descs[1]; 1674 ci->ci_feat_val[6] = descs[2]; 1675 ci->ci_feat_val[7] = descs[3]; 1676 1677 if (ci->ci_max_cpuid < 0xd) 1678 return; 1679 1680 /* Get support XCR0 bits */ 1681 x86_cpuid2(0xd, 0, descs); 1682 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1683 ci->ci_cur_xsave = descs[1]; 1684 ci->ci_max_xsave = descs[2]; 1685 1686 /* Additional flags (eg xsaveopt support) */ 1687 x86_cpuid2(0xd, 1, descs); 1688 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1689 } 1690 1691 static void 1692 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1693 { 1694 uint32_t descs[4]; 1695 char hv_sig[13]; 1696 char *p; 1697 const char *hv_name; 1698 int i; 1699 1700 /* 1701 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1702 * http://lkml.org/lkml/2008/10/1/246 1703 * 1704 * KB1009458: Mechanisms to determine if software is running in 1705 * a VMware virtual machine 1706 * http://kb.vmware.com/kb/1009458 1707 */ 1708 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1709 x86_cpuid(0x40000000, descs); 1710 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1711 memcpy(p, &descs[i], sizeof(descs[i])); 1712 *p = '\0'; 1713 /* 1714 * HV vendor ID string 1715 * ------------+-------------- 1716 * HAXM "HAXMHAXMHAXM" 1717 * KVM "KVMKVMKVM" 1718 * Microsoft "Microsoft Hv" 1719 * QEMU(TCG) "TCGTCGTCGTCG" 1720 * VMware "VMwareVMware" 1721 * Xen "XenVMMXenVMM" 1722 * NetBSD "___ NVMM ___" 1723 */ 1724 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1725 hv_name = "HAXM"; 1726 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1727 hv_name = "KVM"; 1728 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1729 hv_name = "Hyper-V"; 1730 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1731 hv_name = "QEMU(TCG)"; 1732 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1733 hv_name = "VMware"; 1734 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1735 hv_name = "Xen"; 1736 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1737 hv_name = "NVMM"; 1738 else 1739 hv_name = "unknown"; 1740 1741 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1742 } 1743 } 1744 1745 static void 1746 cpu_probe_features(struct cpu_info *ci) 1747 { 1748 const struct cpu_cpuid_nameclass *cpup = NULL; 1749 unsigned int i; 1750 1751 if (ci->ci_max_cpuid < 1) 1752 return; 1753 1754 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1755 if (!strncmp((char *)ci->ci_vendor, 1756 i386_cpuid_cpus[i].cpu_id, 12)) { 1757 cpup = &i386_cpuid_cpus[i]; 1758 break; 1759 } 1760 } 1761 1762 if (cpup == NULL) 1763 return; 1764 1765 i = ci->ci_family - CPU_MINFAMILY; 1766 1767 if (i >= __arraycount(cpup->cpu_family)) 1768 i = __arraycount(cpup->cpu_family) - 1; 1769 1770 if (cpup->cpu_family[i].cpu_probe == NULL) 1771 return; 1772 1773 (*cpup->cpu_family[i].cpu_probe)(ci); 1774 } 1775 1776 static void 1777 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1778 { 1779 char buf[32 * 16]; 1780 char *bp; 1781 1782 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1783 1784 if (val == 0 || fmt == NULL) 1785 return; 1786 1787 snprintb_m(buf, sizeof(buf), fmt, val, 1788 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1789 bp = buf; 1790 while (*bp != '\0') { 1791 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1792 bp += strlen(bp) + 1; 1793 } 1794 } 1795 #ifdef lint 1796 #define print_bits(cpuname, hdr, fmt, val) \ 1797 do { \ 1798 print_bits(cpuname, hdr, fmt, val); \ 1799 snprintb(NULL, 0, fmt, val); \ 1800 } while (0) 1801 #endif 1802 1803 static void 1804 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1805 const char *blockname) 1806 { 1807 uint32_t descs[4]; 1808 uint32_t leaf; 1809 1810 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1811 leafend); 1812 1813 if (verbose) { 1814 for (leaf = leafstart; leaf <= leafend; leaf++) { 1815 x86_cpuid(leaf, descs); 1816 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1817 leaf, descs[0], descs[1], descs[2], descs[3]); 1818 } 1819 } 1820 } 1821 1822 static void 1823 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1824 { 1825 u_int lp_max = 1; /* logical processors per package */ 1826 u_int smt_max; /* smt per core */ 1827 u_int core_max = 1; /* core per package */ 1828 u_int smt_bits, core_bits; 1829 uint32_t descs[4]; 1830 1831 /* 1832 * 253668.pdf 7.10.2 1833 */ 1834 1835 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1836 x86_cpuid(1, descs); 1837 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1838 } 1839 x86_cpuid2(4, 0, descs); 1840 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1841 1842 assert(lp_max >= core_max); 1843 smt_max = lp_max / core_max; 1844 smt_bits = ilog2(smt_max - 1) + 1; 1845 core_bits = ilog2(core_max - 1) + 1; 1846 1847 if (smt_bits + core_bits) 1848 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1849 1850 if (core_bits) 1851 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1852 __BITS(smt_bits, smt_bits + core_bits - 1)); 1853 1854 if (smt_bits) 1855 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1856 __BITS((int)0, (int)(smt_bits - 1))); 1857 } 1858 1859 static void 1860 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1861 { 1862 const char *cpuname = ci->ci_dev; 1863 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1864 uint32_t descs[4]; 1865 int i; 1866 1867 x86_cpuid(0x0b, descs); 1868 if (descs[1] == 0) { 1869 identifycpu_cpuids_intel_0x04(ci); 1870 return; 1871 } 1872 1873 for (i = 0; ; i++) { 1874 unsigned int shiftnum, lvltype; 1875 x86_cpuid2(0x0b, i, descs); 1876 1877 /* On invalid level, (EAX and) EBX return 0 */ 1878 if (descs[1] == 0) 1879 break; 1880 1881 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1882 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1883 switch (lvltype) { 1884 case CPUID_TOP_LVLTYPE_SMT: 1885 core_shift = shiftnum; 1886 break; 1887 case CPUID_TOP_LVLTYPE_CORE: 1888 pkg_shift = shiftnum; 1889 break; 1890 case CPUID_TOP_LVLTYPE_INVAL: 1891 aprint_verbose("%s: Invalid level type\n", cpuname); 1892 break; 1893 default: 1894 aprint_verbose("%s: Unknown level type(%d) \n", 1895 cpuname, lvltype); 1896 break; 1897 } 1898 } 1899 1900 assert(pkg_shift >= core_shift); 1901 smt_bits = core_shift; 1902 core_bits = pkg_shift - core_shift; 1903 1904 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1905 1906 if (core_bits) 1907 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1908 __BITS(core_shift, pkg_shift - 1)); 1909 1910 if (smt_bits) 1911 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1912 __BITS((int)0, core_shift - 1)); 1913 } 1914 1915 static void 1916 identifycpu_cpuids_intel(struct cpu_info *ci) 1917 { 1918 const char *cpuname = ci->ci_dev; 1919 1920 if (ci->ci_max_cpuid >= 0x0b) 1921 identifycpu_cpuids_intel_0x0b(ci); 1922 else if (ci->ci_max_cpuid >= 4) 1923 identifycpu_cpuids_intel_0x04(ci); 1924 1925 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1926 ci->ci_packageid); 1927 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1928 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1929 } 1930 1931 static void 1932 identifycpu_cpuids_amd(struct cpu_info *ci) 1933 { 1934 const char *cpuname = ci->ci_dev; 1935 u_int lp_max, core_max; 1936 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1937 uint32_t descs[4]; 1938 1939 apic_id = ci->ci_initapicid; 1940 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1941 1942 if (cpu_family < 0xf) 1943 return; 1944 1945 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1946 x86_cpuid(1, descs); 1947 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1948 1949 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1950 x86_cpuid(0x8000008, descs); 1951 core_max = (descs[2] & 0xff) + 1; 1952 n = (descs[2] >> 12) & 0x0f; 1953 if (n != 0) 1954 core_bits = n; 1955 } 1956 } else { 1957 lp_max = 1; 1958 } 1959 core_max = lp_max; 1960 1961 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1962 if (core_bits == 0) 1963 core_bits = ilog2(core_max - 1) + 1; 1964 1965 #if 0 /* MSRs need kernel mode */ 1966 if (cpu_family < 0x11) { 1967 const uint64_t reg = rdmsr(MSR_NB_CFG); 1968 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1969 const u_int node_id = apic_id & __BITS(0, 2); 1970 apic_id = (cpu_family == 0xf) ? 1971 (apic_id >> core_bits) | (node_id << core_bits) : 1972 (apic_id >> 5) | (node_id << 2); 1973 } 1974 } 1975 #endif 1976 1977 if (cpu_family >= 0x17) { 1978 x86_cpuid(0x8000001e, descs); 1979 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1980 smt_bits = ilog2(threads); 1981 core_bits -= smt_bits; 1982 } 1983 1984 if (smt_bits + core_bits) { 1985 if (smt_bits + core_bits < 32) 1986 ci->ci_packageid = 0; 1987 } 1988 if (core_bits) { 1989 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1990 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1991 } 1992 if (smt_bits) { 1993 u_int smt_mask = __BITS(0, smt_bits - 1); 1994 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1995 } 1996 1997 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1998 ci->ci_packageid); 1999 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 2000 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 2001 } 2002 2003 static void 2004 identifycpu_cpuids(struct cpu_info *ci) 2005 { 2006 const char *cpuname = ci->ci_dev; 2007 2008 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 2009 ci->ci_packageid = ci->ci_initapicid; 2010 ci->ci_coreid = 0; 2011 ci->ci_smtid = 0; 2012 2013 if (cpu_vendor == CPUVENDOR_INTEL) 2014 identifycpu_cpuids_intel(ci); 2015 else if (cpu_vendor == CPUVENDOR_AMD) 2016 identifycpu_cpuids_amd(ci); 2017 } 2018 2019 void 2020 identifycpu(int fd, const char *cpuname) 2021 { 2022 const char *name = "", *modifier, *vendorname, *brand = ""; 2023 int class = CPUCLASS_386; 2024 unsigned int i; 2025 int modif, family; 2026 const struct cpu_cpuid_nameclass *cpup = NULL; 2027 const struct cpu_cpuid_family *cpufam; 2028 struct cpu_info *ci, cistore; 2029 u_int descs[4]; 2030 size_t sz; 2031 struct cpu_ucode_version ucode; 2032 union { 2033 struct cpu_ucode_version_amd amd; 2034 struct cpu_ucode_version_intel1 intel1; 2035 } ucvers; 2036 2037 ci = &cistore; 2038 cpu_probe_base_features(ci, cpuname); 2039 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 2040 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2041 x86_cpuid(0x40000000, descs); 2042 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2043 } 2044 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 2045 2046 cpu_probe_hv_features(ci, cpuname); 2047 cpu_probe_features(ci); 2048 2049 if (ci->ci_cpu_type >= 0) { 2050 /* Old pre-cpuid instruction cpu */ 2051 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2052 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2053 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2054 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2055 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2056 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2057 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2058 modifier = ""; 2059 } else { 2060 /* CPU which support cpuid instruction */ 2061 modif = (ci->ci_signature >> 12) & 0x3; 2062 family = ci->ci_family; 2063 if (family < CPU_MINFAMILY) 2064 errx(1, "identifycpu: strange family value"); 2065 if (family > CPU_MAXFAMILY) 2066 family = CPU_MAXFAMILY; 2067 2068 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2069 if (!strncmp((char *)ci->ci_vendor, 2070 i386_cpuid_cpus[i].cpu_id, 12)) { 2071 cpup = &i386_cpuid_cpus[i]; 2072 break; 2073 } 2074 } 2075 2076 if (cpup == NULL) { 2077 cpu_vendor = CPUVENDOR_UNKNOWN; 2078 if (ci->ci_vendor[0] != '\0') 2079 vendorname = (char *)&ci->ci_vendor[0]; 2080 else 2081 vendorname = "Unknown"; 2082 class = family - 3; 2083 modifier = ""; 2084 name = ""; 2085 ci->ci_info = NULL; 2086 } else { 2087 cpu_vendor = cpup->cpu_vendor; 2088 vendorname = cpup->cpu_vendorname; 2089 modifier = modifiers[modif]; 2090 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2091 name = cpufam->cpu_models[ci->ci_model]; 2092 if (name == NULL || *name == '\0') 2093 name = cpufam->cpu_model_default; 2094 class = cpufam->cpu_class; 2095 ci->ci_info = cpufam->cpu_info; 2096 2097 if (cpu_vendor == CPUVENDOR_INTEL) { 2098 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2099 const char *tmp; 2100 tmp = intel_family6_name(ci); 2101 if (tmp != NULL) 2102 name = tmp; 2103 } 2104 if (ci->ci_family == 15 && 2105 ci->ci_brand_id < 2106 __arraycount(i386_intel_brand) && 2107 i386_intel_brand[ci->ci_brand_id]) 2108 name = 2109 i386_intel_brand[ci->ci_brand_id]; 2110 } 2111 2112 if (cpu_vendor == CPUVENDOR_AMD) { 2113 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2114 if (ci->ci_brand_id == 1) 2115 /* 2116 * It's Duron. We override the 2117 * name, since it might have 2118 * been misidentified as Athlon. 2119 */ 2120 name = 2121 amd_brand[ci->ci_brand_id]; 2122 else 2123 brand = amd_brand_name; 2124 } 2125 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2126 == 0xf) { 2127 /* Identify AMD64 CPU names. */ 2128 const char *tmp; 2129 tmp = amd_amd64_name(ci); 2130 if (tmp != NULL) 2131 name = tmp; 2132 } 2133 } 2134 2135 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family == 6) 2136 vendorname = "VIA"; 2137 2138 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 7) 2139 vendorname = "Zhaoxin"; 2140 } 2141 } 2142 2143 ci->ci_cpu_class = class; 2144 2145 sz = sizeof(ci->ci_tsc_freq); 2146 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2147 sz = sizeof(use_pae); 2148 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2149 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2150 2151 /* 2152 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2153 * we try to determine from the family/model values. 2154 */ 2155 if (*cpu_brand_string != '\0') 2156 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2157 2158 aprint_normal("%s: %s", cpuname, vendorname); 2159 if (*modifier) 2160 aprint_normal(" %s", modifier); 2161 if (*name) 2162 aprint_normal(" %s", name); 2163 if (*brand) 2164 aprint_normal(" %s", brand); 2165 aprint_normal(" (%s-class)", classnames[class]); 2166 2167 if (ci->ci_tsc_freq != 0) 2168 aprint_normal(", %ju.%02ju MHz", 2169 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2170 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2171 aprint_normal("\n"); 2172 2173 (void)cpu_tsc_freq_cpuid(ci); 2174 2175 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2176 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2177 if (ci->ci_signature != 0) 2178 aprint_normal(" (id %#x)", ci->ci_signature); 2179 aprint_normal("\n"); 2180 2181 if (ci->ci_info) 2182 (*ci->ci_info)(ci); 2183 2184 /* 2185 * display CPU feature flags 2186 */ 2187 2188 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2189 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2190 2191 /* These next two are actually common definitions! */ 2192 print_bits(cpuname, "features2", 2193 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2194 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2195 print_bits(cpuname, "features3", 2196 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2197 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2198 2199 print_bits(cpuname, "padlock features", CPUID_FLAGS_PADLOCK, 2200 ci->ci_feat_val[4]); 2201 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD) || 2202 (cpu_vendor == CPUVENDOR_IDT)) 2203 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2204 ci->ci_feat_val[5]); 2205 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD) || 2206 (cpu_vendor == CPUVENDOR_IDT)) 2207 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2208 ci->ci_feat_val[6]); 2209 2210 if (cpu_vendor == CPUVENDOR_INTEL || (cpu_vendor == CPUVENDOR_IDT)) 2211 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2212 ci->ci_feat_val[7]); 2213 2214 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2215 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2216 ci->ci_feat_val[9]); 2217 2218 if (ci->ci_max_xsave != 0) { 2219 aprint_normal("%s: xsave area size: current %d, maximum %d", 2220 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2221 aprint_normal(", xgetbv %sabled\n", 2222 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2223 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2224 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2225 x86_xgetbv()); 2226 } 2227 2228 x86_print_cache_and_tlb_info(ci); 2229 2230 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2231 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2232 cpuname, 2233 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2234 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2235 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2236 } 2237 2238 if (ci->ci_cpu_class == CPUCLASS_386) 2239 errx(1, "NetBSD requires an 80486 or later processor"); 2240 2241 if (ci->ci_cpu_type == CPU_486DLC) { 2242 #ifndef CYRIX_CACHE_WORKS 2243 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2244 #else 2245 #ifndef CYRIX_CACHE_REALLY_WORKS 2246 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2247 #else 2248 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2249 #endif 2250 #endif 2251 } 2252 2253 /* 2254 * Everything past this point requires a Pentium or later. 2255 */ 2256 if (ci->ci_max_cpuid < 0) 2257 return; 2258 2259 identifycpu_cpuids(ci); 2260 2261 if ((ci->ci_max_cpuid >= 5) 2262 && ((cpu_vendor == CPUVENDOR_INTEL) 2263 || (cpu_vendor == CPUVENDOR_AMD))) { 2264 uint16_t lmin, lmax; 2265 x86_cpuid(5, descs); 2266 2267 print_bits(cpuname, "MONITOR/MWAIT extensions", 2268 CPUID_MON_FLAGS, descs[2]); 2269 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2270 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2271 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2272 if (lmin != lmax) 2273 aprint_normal("-%hu", lmax); 2274 aprint_normal("\n"); 2275 2276 for (i = 0; i <= 7; i++) { 2277 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2278 2279 if (num != 0) 2280 aprint_normal("%s: C%u substates %u\n", 2281 cpuname, i, num); 2282 } 2283 } 2284 if ((ci->ci_max_cpuid >= 6) 2285 && ((cpu_vendor == CPUVENDOR_INTEL) 2286 || (cpu_vendor == CPUVENDOR_AMD))) { 2287 x86_cpuid(6, descs); 2288 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2289 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2290 } 2291 if ((ci->ci_max_cpuid >= 7) 2292 && ((cpu_vendor == CPUVENDOR_INTEL) 2293 || (cpu_vendor == CPUVENDOR_AMD))) { 2294 unsigned int maxsubleaf; 2295 2296 x86_cpuid(7, descs); 2297 maxsubleaf = descs[0]; 2298 aprint_verbose("%s: SEF highest subleaf %08x\n", 2299 cpuname, maxsubleaf); 2300 if (maxsubleaf >= 1) { 2301 x86_cpuid2(7, 1, descs); 2302 print_bits(cpuname, "SEF-subleaf1-eax", 2303 CPUID_SEF1_FLAGS_A, descs[0]); 2304 print_bits(cpuname, "SEF-subleaf1-ebx", 2305 CPUID_SEF1_FLAGS_B, descs[1]); 2306 print_bits(cpuname, "SEF-subleaf1-edx", 2307 CPUID_SEF1_FLAGS_D, descs[3]); 2308 } 2309 if (maxsubleaf >= 2) { 2310 x86_cpuid2(7, 2, descs); 2311 print_bits(cpuname, "SEF-subleaf2-edx", 2312 CPUID_SEF2_FLAGS_D, descs[3]); 2313 } 2314 } 2315 2316 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2317 if (ci->ci_max_ext_cpuid >= 0x80000007) 2318 powernow_probe(ci); 2319 2320 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2321 x86_cpuid(0x80000008, descs); 2322 print_bits(cpuname, "AMD Extended features", 2323 CPUID_CAPEX_FLAGS, descs[1]); 2324 } 2325 } 2326 2327 if (cpu_vendor == CPUVENDOR_AMD) { 2328 if (ci->ci_max_ext_cpuid >= 0x80000021) { 2329 x86_cpuid(0x80000021, descs); 2330 print_bits(cpuname, "AMD Extended features2", 2331 CPUID_AMDEXT2_FLAGS, descs[0]); 2332 } 2333 2334 if (ci->ci_max_ext_cpuid >= 0x80000007) { 2335 x86_cpuid(0x80000007, descs); 2336 print_bits(cpuname, "RAS features", 2337 CPUID_RAS_FLAGS, descs[1]); 2338 } 2339 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2340 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2341 x86_cpuid(0x8000000a, descs); 2342 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2343 descs[0] & 0xf); 2344 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2345 descs[1]); 2346 print_bits(cpuname, "SVM features", 2347 CPUID_AMD_SVM_FLAGS, descs[3]); 2348 } 2349 if (ci->ci_max_ext_cpuid >= 0x8000001b) { 2350 x86_cpuid(0x8000001b, descs); 2351 print_bits(cpuname, "IBS features", 2352 CPUID_IBS_FLAGS, descs[0]); 2353 } 2354 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2355 x86_cpuid(0x8000001f, descs); 2356 print_bits(cpuname, "Encrypted Memory features", 2357 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2358 } 2359 if (ci->ci_max_ext_cpuid >= 0x80000022) { 2360 uint8_t ncore, nnb, numc, nlbrs; 2361 2362 x86_cpuid(0x80000022, descs); 2363 print_bits(cpuname, "Perfmon:", 2364 CPUID_AXPERF_FLAGS, descs[0]); 2365 2366 ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC); 2367 nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC); 2368 numc = __SHIFTOUT(descs[1], CPUID_AXPERF_NUMCPC); 2369 nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK); 2370 aprint_verbose("%s: Perfmon: counters: " 2371 "Core %hhu, Northbridge %hhu, UMC %hhu\n", cpuname, 2372 ncore, nnb, numc); 2373 aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n", 2374 cpuname, nlbrs); 2375 } 2376 if (ci->ci_max_ext_cpuid >= 0x80000027) { 2377 uint8_t classes; 2378 2379 x86_cpuid(0x80000027, descs); 2380 classes = __SHIFTOUT(descs[0], CPUID_HWC_NWC); 2381 aprint_verbose("%s: Hetero workload class: " 2382 "%hhu classes\n", cpuname, classes); 2383 } 2384 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2385 if (ci->ci_max_cpuid >= 0x0a) { 2386 unsigned int pmcver, ncounter, veclen; 2387 2388 x86_cpuid(0x0a, descs); 2389 pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION); 2390 ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC); 2391 veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN); 2392 aprint_verbose("%s: Perfmon: Ver. %u", 2393 cpuname, pmcver); 2394 if (((pmcver >= 3) && (pmcver <= 4)) || 2395 ((pmcver >= 5) && 2396 (descs[3] & CPUID_PERF_ANYTHREADDEPR) == 0)) 2397 aprint_verbose(" <ANYTHREAD>\n"); 2398 else 2399 aprint_verbose("\n"); 2400 2401 aprint_verbose("%s: Perfmon: General: " 2402 "bitwidth %u, %u counters\n", cpuname, 2403 (uint32_t)__SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC), 2404 ncounter); 2405 /* Invert logic for the output */ 2406 descs[1] ^= __BITS(veclen - 1, 0); 2407 /* 2408 * Mask unrelated bits. An hypervisor reduces the 2409 * vector and set bit(s) out of the vector. 2410 */ 2411 descs[1] &= __BITS(veclen - 1, 0); 2412 print_bits(cpuname, "Perfmon: General: avail", 2413 CPUID_PERF_FLAGS1, descs[1]); 2414 2415 if (pmcver >= 2) { 2416 ncounter = __SHIFTOUT(descs[3], 2417 CPUID_PERF_NFFPC); 2418 aprint_verbose("%s: Perfmon: Fixed: " 2419 "bitwidth %u, %u counters\n", cpuname, 2420 (uint32_t)__SHIFTOUT(descs[3], 2421 CPUID_PERF_NBWFFPC), 2422 ncounter); 2423 if (pmcver <= 4) 2424 descs[2] = __BITS(ncounter - 1, 0); 2425 print_bits(cpuname, "Perfmon: Fixed: avail", 2426 CPUID_PERF_FLAGS2, descs[2]); 2427 } 2428 } 2429 if (ci->ci_max_cpuid >= 0x1a) { 2430 x86_cpuid(0x1a, descs); 2431 if (descs[0] != 0) { 2432 aprint_verbose("%s: Hybrid: Core type %02x, " 2433 "Native Model ID %07x\n", 2434 cpuname, 2435 (uint8_t)__SHIFTOUT(descs[0], 2436 CPUID_HYBRID_CORETYPE), 2437 (uint32_t)__SHIFTOUT(descs[0], 2438 CPUID_HYBRID_NATIVEID)); 2439 } 2440 } 2441 } 2442 2443 #ifdef INTEL_ONDEMAND_CLOCKMOD 2444 clockmod_init(); 2445 #endif 2446 2447 if (cpu_vendor == CPUVENDOR_AMD) 2448 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2449 else if (cpu_vendor == CPUVENDOR_INTEL) 2450 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2451 else 2452 return; 2453 2454 ucode.data = &ucvers; 2455 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2456 #ifdef __i386__ 2457 struct cpu_ucode_version_64 ucode_64; 2458 if (errno != ENOTTY) 2459 return; 2460 /* Try the 64 bit ioctl */ 2461 memset(&ucode_64, 0, sizeof ucode_64); 2462 ucode_64.data = &ucvers; 2463 ucode_64.loader_version = ucode.loader_version; 2464 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2465 return; 2466 #else 2467 return; 2468 #endif 2469 } 2470 2471 if (cpu_vendor == CPUVENDOR_AMD) 2472 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2473 else if (cpu_vendor == CPUVENDOR_INTEL) 2474 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2475 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2476 } 2477 2478 static const char * 2479 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2480 const char *sep) 2481 { 2482 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2483 char human_num[HUMAN_BUFSIZE]; 2484 2485 if (cai->cai_totalsize == 0) 2486 return sep; 2487 2488 if (sep == NULL) 2489 aprint_verbose_dev(ci->ci_dev, ""); 2490 else 2491 aprint_verbose("%s", sep); 2492 if (name != NULL) 2493 aprint_verbose("%s ", name); 2494 2495 if (cai->cai_string != NULL) { 2496 aprint_verbose("%s ", cai->cai_string); 2497 } else { 2498 (void)humanize_number(human_num, sizeof(human_num), 2499 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2500 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2501 } 2502 switch (cai->cai_associativity) { 2503 case 0: 2504 aprint_verbose("disabled"); 2505 break; 2506 case 1: 2507 aprint_verbose("direct-mapped"); 2508 break; 2509 case 0xff: 2510 aprint_verbose("fully associative"); 2511 break; 2512 default: 2513 aprint_verbose("%d-way", cai->cai_associativity); 2514 break; 2515 } 2516 return ", "; 2517 } 2518 2519 static const char * 2520 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2521 const char *sep) 2522 { 2523 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2524 char human_num[HUMAN_BUFSIZE]; 2525 2526 if (cai->cai_totalsize == 0) 2527 return sep; 2528 2529 if (sep == NULL) 2530 aprint_verbose_dev(ci->ci_dev, ""); 2531 else 2532 aprint_verbose("%s", sep); 2533 if ((name != NULL) && (sep == NULL)) 2534 aprint_verbose("%s ", name); 2535 2536 if (cai->cai_string != NULL) { 2537 aprint_verbose("%s", cai->cai_string); 2538 } else { 2539 (void)humanize_number(human_num, sizeof(human_num), 2540 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2541 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2542 human_num); 2543 switch (cai->cai_associativity) { 2544 case 0: 2545 aprint_verbose("disabled"); 2546 break; 2547 case 1: 2548 aprint_verbose("direct-mapped"); 2549 break; 2550 case 0xff: 2551 aprint_verbose("fully associative"); 2552 break; 2553 default: 2554 aprint_verbose("%d-way", cai->cai_associativity); 2555 break; 2556 } 2557 } 2558 return ", "; 2559 } 2560 2561 static void 2562 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2563 { 2564 const char *sep = NULL; 2565 2566 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2567 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2568 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2569 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2570 if (sep != NULL) 2571 aprint_verbose("\n"); 2572 } 2573 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2574 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2575 if (sep != NULL) 2576 aprint_verbose("\n"); 2577 } 2578 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2579 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2580 if (sep != NULL) 2581 aprint_verbose("\n"); 2582 } 2583 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2584 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2585 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2586 if (sep != NULL) 2587 aprint_verbose("\n"); 2588 } 2589 2590 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2591 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2592 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep); 2593 if (sep != NULL) 2594 aprint_verbose("\n"); 2595 2596 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2597 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2598 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep); 2599 if (sep != NULL) 2600 aprint_verbose("\n"); 2601 2602 sep = print_tlb_config(ci, CAI_L1_LD_TLB, "Load only TLB:", NULL); 2603 if (sep != NULL) 2604 aprint_verbose("\n"); 2605 2606 sep = print_tlb_config(ci, CAI_L1_ST_TLB, "Store only TLB:", NULL); 2607 if (sep != NULL) 2608 aprint_verbose("\n"); 2609 2610 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2611 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2612 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep); 2613 if (sep != NULL) 2614 aprint_verbose("\n"); 2615 2616 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2617 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2618 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep); 2619 if (sep != NULL) 2620 aprint_verbose("\n"); 2621 2622 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2623 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2624 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2625 if (sep != NULL) 2626 aprint_verbose("\n"); 2627 } 2628 2629 static void 2630 powernow_probe(struct cpu_info *ci) 2631 { 2632 uint32_t regs[4]; 2633 char buf[256]; 2634 2635 x86_cpuid(0x80000007, regs); 2636 2637 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2638 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2639 } 2640 2641 bool 2642 identifycpu_bind(void) 2643 { 2644 2645 return true; 2646 } 2647 2648 int 2649 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2650 { 2651 struct cpu_info ci; 2652 int loader_version, res; 2653 struct cpu_ucode_version versreq; 2654 2655 cpu_probe_base_features(&ci, "unknown"); 2656 2657 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2658 loader_version = CPU_UCODE_LOADER_AMD; 2659 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2660 loader_version = CPU_UCODE_LOADER_INTEL1; 2661 else 2662 return -1; 2663 2664 /* check whether the kernel understands this loader version */ 2665 versreq.loader_version = loader_version; 2666 versreq.data = 0; 2667 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2668 if (res) 2669 return -1; 2670 2671 switch (loader_version) { 2672 case CPU_UCODE_LOADER_AMD: 2673 if (uc->cpu_nr != -1) { 2674 warnx("ucode updates on AMD can only be done on all CPUs at once"); 2675 return -1; 2676 } 2677 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2678 break; 2679 case CPU_UCODE_LOADER_INTEL1: 2680 if (uc->cpu_nr == -1) 2681 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2682 else 2683 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2684 break; 2685 default: /* can't happen */ 2686 return -1; 2687 } 2688 uc->loader_version = loader_version; 2689 return 0; 2690 } 2691
Indexes created Sun Oct 25 00:26:45 UTC 2026