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    Searched refs:dr7 (Results 1 - 7 of 7) sorted by relevancy

  /src/tests/lib/libc/sys/
t_ptrace_x86_wait.h 388 union u dr7; local
398 dr7.raw = 0;
401 dr7.bits.global_dr0_breakpoint = 1;
402 dr7.bits.condition_dr0 = cond;
403 dr7.bits.len_dr0 = len;
406 dr7.bits.global_dr1_breakpoint = 1;
407 dr7.bits.condition_dr1 = cond;
408 dr7.bits.len_dr1 = len;
411 dr7.bits.global_dr2_breakpoint = 1;
412 dr7.bits.condition_dr2 = cond
1108 union u dr7; local
1240 union u dr7; local
1372 union u dr7; local
1504 union u dr7; local
4374 union u dr7; local
4409 union u dr7; local
    [all...]
  /src/sys/arch/x86/x86/
dbregs.c 65 /* DR6 and DR7 contain predefined nonzero bits */
85 * It's sufficient to just disable Debug Control Register (DR7).
201 register_t dr7, dr6; local
204 dr7 = rdr7();
205 if ((dr7 & X86_GLOBAL_BREAKPOINT) == 0) {
  /src/sys/external/mit/xen-include-public/dist/xen/include/public/
vm_event.h 182 uint64_t dr7; member in struct:vm_event_regs_x86
  /src/external/gpl3/gdb/dist/gdb/nat/
x86-dregs.c 60 /* Can we update the inferior's DR7 control register? */
68 /* Update the inferior's DR7 debug control register from STATE. */
76 /* Return the value of the inferior's DR7 debug control register. */
103 /* DR7 Debug Control register fields. */
105 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
107 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
110 /* Watchpoint/breakpoint read/write fields in DR7. */
122 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
129 /* Local and Global Enable flags in DR7.
161 /* A value that masks all fields in DR7 that are reserved by Intel. *
    [all...]
  /src/external/gpl3/gdb.old/dist/gdb/nat/
x86-dregs.c 60 /* Can we update the inferior's DR7 control register? */
68 /* Update the inferior's DR7 debug control register from STATE. */
76 /* Return the value of the inferior's DR7 debug control register. */
103 /* DR7 Debug Control register fields. */
105 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
107 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
110 /* Watchpoint/breakpoint read/write fields in DR7. */
122 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
129 /* Local and Global Enable flags in DR7.
161 /* A value that masks all fields in DR7 that are reserved by Intel. *
    [all...]
  /src/sys/external/mit/xen-include-public/dist/xen/include/public/arch-x86/hvm/
save.h 88 uint64_t dr7; member in struct:hvm_hw_cpu
202 uint64_t dr7; member in struct:hvm_hw_cpu_compat
  /src/sys/dev/nvmm/x86/
nvmm_x86_svm.c 448 uint64_t dr7; member in struct:vmcb_state
1941 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7];
2069 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7;

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