| /src/sys/arch/aarch64/aarch64/ |
| disasm.c | 677 ValidBitMasks(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
684 len = fls64((n << 6) + (~imms & 0x3f)) - 1;
689 imms &= (esize - 1);
690 if (imms == (uint64_t)(esize - 1))
697 DecodeBitMasks(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
703 len = fls64((n << 6) + (~imms & 0x3f)) - 1;
705 imms &= (esize - 1);
707 result = rotate(esize, (1ULL << (imms + 1)) - 1, immr);
718 MoveWidePreferred(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
721 uint64_t x = DecodeBitMasks(sf, n, imms, immr)
[all...] |
| db_trace.c | 218 DecodeBitMasks(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
224 len = fls64((n << 6) + (~imms & 0x3f)) - 1;
226 imms &= (esize - 1);
228 result = rotate(esize, (1ULL << (imms + 1)) - 1, immr);
350 uint64_t imms = (insn >> 10) & 0x3f; local
351 uint64_t v = DecodeBitMasks(1, n, imms, immr);
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-i386.c | 237 expressionS *imms; member in union:i386_op
3829 pe (x->op[j].imms);
4945 i.op[i.operands].imms = exp;
5127 if (!i.op[0].imms)
5129 i.op[0].imms = &im_expressions[0];
5130 i.op[0].imms->X_op = O_absent;
5246 i.op[0].imms = &im_expressions[0];
5282 && i.op[0].imms->X_op == O_constant
5283 && fits_in_imm7 (i.op[0].imms->X_add_number))
5323 && i.op[0].imms->X_op == O_constan
[all...] |
| tc-i386-ginsn.c | 255 && i.op[0].imms->X_op != O_constant)
270 src_imm = i.op[0].imms->X_add_number;
540 if (i.op[0].imms->X_op != O_constant || i.op[0].imms->X_add_symbol != 0
541 || i.op[1].imms->X_op != O_constant || i.op[1].imms->X_add_symbol != 0)
|
| tc-i386-intel.c | 963 i.op[this_operand].imms = expP;
1056 if (i386_finalize_immediate (exp_seg, i.op[0].imms,
1062 i.op[this_operand].imms = expP;
1206 i.op[this_operand].imms = expP;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64InstPrinter.cpp | 122 int64_t imms = Op3.getImm(); local
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
125 shift = 31 - imms;
126 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
127 ((imms + 1 == immr))) {
129 shift = 63 - imms;
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
133 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
136 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
[all...] |
| AArch64AddressingModes.h | 212 /// the form N:immr:imms.
291 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
294 // Extract the N, imms, and immr fields.
297 unsigned imms = val & 0x3f; local
300 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
304 unsigned S = imms & (size - 1);
319 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
323 // Extract the N and imms fields needed for checking
325 unsigned imms = val & 0x3f; local
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-i386.c | 237 expressionS *imms; member in union:i386_op
3775 pe (x->op[j].imms);
4871 i.op[i.operands].imms = exp;
5058 if (!i.op[0].imms)
5060 i.op[0].imms = &im_expressions[0];
5061 i.op[0].imms->X_op = O_absent;
5120 && i.op[0].imms->X_op == O_constant
5121 && fits_in_imm7 (i.op[0].imms->X_add_number))
5161 && i.op[0].imms->X_op == O_constant
5164 && fits_in_unsigned_long (i.op[0].imms->X_add_number)
[all...] |
| tc-i386-ginsn.c | 255 && i.op[0].imms->X_op != O_constant)
270 src_imm = i.op[0].imms->X_add_number;
540 if (i.op[0].imms->X_op != O_constant || i.op[0].imms->X_add_symbol != 0
541 || i.op[1].imms->X_op != O_constant || i.op[1].imms->X_add_symbol != 0)
|
| tc-i386-intel.c | 963 i.op[this_operand].imms = expP;
1056 if (i386_finalize_immediate (exp_seg, i.op[0].imms,
1062 i.op[this_operand].imms = expP;
1206 i.op[this_operand].imms = expP;
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| aarch64-dis.c | 747 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
945 /* value is N:immr:imms. */
3006 int64_t imms, val;
3008 imms = inst->operands[3].imm.value;
3010 if (imms == val)
3034 /* When <imms> >= <immr>, the instruction written:
3042 int64_t immr, imms;
3045 imms = inst->operands[3].imm.value;
3046 if (imms >= immr)
3050 inst->operands[3].imm.value = imms + 1 - lsb
3004 int64_t imms, val; local
3040 int64_t immr, imms; local
3067 int64_t immr, imms, val; local
3094 int64_t immr, imms, val; local
3134 int64_t imms = inst->operands[3].imm.value; local
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| aarch64-dis.c | 746 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
944 /* value is N:immr:imms. */
2983 int64_t imms, val;
2985 imms = inst->operands[3].imm.value;
2987 if (imms == val)
3011 /* When <imms> >= <immr>, the instruction written:
3019 int64_t immr, imms;
3022 imms = inst->operands[3].imm.value;
3023 if (imms >= immr)
3027 inst->operands[3].imm.value = imms + 1 - lsb
2980 int64_t imms, val; local
3016 int64_t immr, imms; local
3043 int64_t immr, imms, val; local
3070 int64_t immr, imms, val; local
3110 int64_t imms = inst->operands[3].imm.value; local
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| aarch64-dis.c | 746 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
944 /* value is N:immr:imms. */
2957 int64_t imms, val;
2959 imms = inst->operands[3].imm.value;
2961 if (imms == val)
2985 /* When <imms> >= <immr>, the instruction written:
2993 int64_t immr, imms;
2996 imms = inst->operands[3].imm.value;
2997 if (imms >= immr)
3001 inst->operands[3].imm.value = imms + 1 - lsb
2954 int64_t imms, val; local
2990 int64_t immr, imms; local
3017 int64_t immr, imms, val; local
3044 int64_t immr, imms, val; local
3084 int64_t imms = inst->operands[3].imm.value; local
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| aarch64-dis.c | 744 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
942 /* value is N:immr:imms. */
2982 int64_t imms, val;
2984 imms = inst->operands[3].imm.value;
2986 if (imms == val)
3010 /* When <imms> >= <immr>, the instruction written:
3018 int64_t immr, imms;
3021 imms = inst->operands[3].imm.value;
3022 if (imms >= immr)
3026 inst->operands[3].imm.value = imms + 1 - lsb
2979 int64_t imms, val; local
3015 int64_t immr, imms; local
3042 int64_t immr, imms, val; local
3069 int64_t immr, imms, val; local
3109 int64_t imms = inst->operands[3].imm.value; local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| simulator.c | 144 /* Instr[22,10] encodes N immr and imms. we want a lookup table
158 uint32_t imms = uimm (index, 5, 0); local
160 LITable [index] = expand_logical_immediate (imms, immr, n);
9922 instr[15,10] = imms
9930 /* uint32_t imms = INSTR (15, 10);. */
10333 instr[15,10] = imms : 0xxxxx for 32 bit, xxxxxx for 64 bit
10339 uint32_t imms; local
10342 /* 32 bit operations must have immr[5] = 0 and imms[5] = 0. */
10352 imms = INSTR (15, 10);
10353 if (!size && uimm (imms, 5, 5)
10379 unsigned imms = INSTR (15, 10) & 31; local
10386 val1 >>= imms; local
10403 unsigned imms = INSTR (15, 10) & 63; local
10409 val >>= imms; local
10435 uint32_t imms = INSTR (15, 10); local
[all...] |
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| simulator.c | 144 /* Instr[22,10] encodes N immr and imms. we want a lookup table
158 uint32_t imms = uimm (index, 5, 0); local
160 LITable [index] = expand_logical_immediate (imms, immr, n);
9922 instr[15,10] = imms
9930 /* uint32_t imms = INSTR (15, 10);. */
10333 instr[15,10] = imms : 0xxxxx for 32 bit, xxxxxx for 64 bit
10339 uint32_t imms; local
10342 /* 32 bit operations must have immr[5] = 0 and imms[5] = 0. */
10352 imms = INSTR (15, 10);
10353 if (!size && uimm (imms, 5, 5)
10379 unsigned imms = INSTR (15, 10) & 31; local
10386 val1 >>= imms; local
10403 unsigned imms = INSTR (15, 10) & 63; local
10409 val >>= imms; local
10435 uint32_t imms = INSTR (15, 10); local
[all...] |
| /src/external/gpl3/gdb.old/dist/gdbserver/ |
| linux-aarch64-low.cc | 1842 SBFM rd, rn, #immr, #imms
1844 This instruction moves the bits from #immr to #imms into the
1850 IMMS is the bit number to stop at (most significant bit). */
1854 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1860 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
1887 UBFM rd, rn, #immr, #imms
1889 This instruction moves the bits from #immr to #imms into the
1895 IMMS is the bit number to stop at (most significant bit). */
1899 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1905 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5
[all...] |
| /src/external/gpl3/gdb/dist/gdbserver/ |
| linux-aarch64-low.cc | 1888 SBFM rd, rn, #immr, #imms
1890 This instruction moves the bits from #immr to #imms into the
1896 IMMS is the bit number to stop at (most significant bit). */
1900 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1906 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5)
1933 UBFM rd, rn, #immr, #imms
1935 This instruction moves the bits from #immr to #imms into the
1941 IMMS is the bit number to stop at (most significant bit). */
1945 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1951 | ENCODE (imms, 6, 10) | ENCODE (rn.num, 5, 5
[all...] |
