1 #ifndef A6XX_XML 2 #define A6XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-05-03 18:24:29) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2019-05-03 18:24:29) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 148461 bytes, from 2019-05-03 18:24:37) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23 Copyright (C) 2013-2019 by the following authors: 24 - Rob Clark <robdclark (at) gmail.com> (robclark) 25 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 26 27 Permission is hereby granted, free of charge, to any person obtaining 28 a copy of this software and associated documentation files (the 29 "Software"), to deal in the Software without restriction, including 30 without limitation the rights to use, copy, modify, merge, publish, 31 distribute, sublicense, and/or sell copies of the Software, and to 32 permit persons to whom the Software is furnished to do so, subject to 33 the following conditions: 34 35 The above copyright notice and this permission notice (including the 36 next paragraph) shall be included in all copies or substantial 37 portions of the Software. 38 39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 49 enum a6xx_color_fmt { 50 RB6_A8_UNORM = 2, 51 RB6_R8_UNORM = 3, 52 RB6_R8_SNORM = 4, 53 RB6_R8_UINT = 5, 54 RB6_R8_SINT = 6, 55 RB6_R4G4B4A4_UNORM = 8, 56 RB6_R5G5B5A1_UNORM = 10, 57 RB6_R5G6B5_UNORM = 14, 58 RB6_R8G8_UNORM = 15, 59 RB6_R8G8_SNORM = 16, 60 RB6_R8G8_UINT = 17, 61 RB6_R8G8_SINT = 18, 62 RB6_R16_UNORM = 21, 63 RB6_R16_SNORM = 22, 64 RB6_R16_FLOAT = 23, 65 RB6_R16_UINT = 24, 66 RB6_R16_SINT = 25, 67 RB6_R8G8B8A8_UNORM = 48, 68 RB6_R8G8B8_UNORM = 49, 69 RB6_R8G8B8A8_SNORM = 50, 70 RB6_R8G8B8A8_UINT = 51, 71 RB6_R8G8B8A8_SINT = 52, 72 RB6_R10G10B10A2_UNORM = 55, 73 RB6_R10G10B10A2_UINT = 58, 74 RB6_R11G11B10_FLOAT = 66, 75 RB6_R16G16_UNORM = 67, 76 RB6_R16G16_SNORM = 68, 77 RB6_R16G16_FLOAT = 69, 78 RB6_R16G16_UINT = 70, 79 RB6_R16G16_SINT = 71, 80 RB6_R32_FLOAT = 74, 81 RB6_R32_UINT = 75, 82 RB6_R32_SINT = 76, 83 RB6_R16G16B16A16_UNORM = 96, 84 RB6_R16G16B16A16_SNORM = 97, 85 RB6_R16G16B16A16_FLOAT = 98, 86 RB6_R16G16B16A16_UINT = 99, 87 RB6_R16G16B16A16_SINT = 100, 88 RB6_R32G32_FLOAT = 103, 89 RB6_R32G32_UINT = 104, 90 RB6_R32G32_SINT = 105, 91 RB6_R32G32B32A32_FLOAT = 130, 92 RB6_R32G32B32A32_UINT = 131, 93 RB6_R32G32B32A32_SINT = 132, 94 RB6_X8Z24_UNORM = 160, 95 }; 96 97 enum a6xx_tile_mode { 98 TILE6_LINEAR = 0, 99 TILE6_2 = 2, 100 TILE6_3 = 3, 101 }; 102 103 enum a6xx_vtx_fmt { 104 VFMT6_8_UNORM = 3, 105 VFMT6_8_SNORM = 4, 106 VFMT6_8_UINT = 5, 107 VFMT6_8_SINT = 6, 108 VFMT6_8_8_UNORM = 15, 109 VFMT6_8_8_SNORM = 16, 110 VFMT6_8_8_UINT = 17, 111 VFMT6_8_8_SINT = 18, 112 VFMT6_16_UNORM = 21, 113 VFMT6_16_SNORM = 22, 114 VFMT6_16_FLOAT = 23, 115 VFMT6_16_UINT = 24, 116 VFMT6_16_SINT = 25, 117 VFMT6_8_8_8_UNORM = 33, 118 VFMT6_8_8_8_SNORM = 34, 119 VFMT6_8_8_8_UINT = 35, 120 VFMT6_8_8_8_SINT = 36, 121 VFMT6_8_8_8_8_UNORM = 48, 122 VFMT6_8_8_8_8_SNORM = 50, 123 VFMT6_8_8_8_8_UINT = 51, 124 VFMT6_8_8_8_8_SINT = 52, 125 VFMT6_10_10_10_2_UNORM = 54, 126 VFMT6_10_10_10_2_SNORM = 57, 127 VFMT6_10_10_10_2_UINT = 58, 128 VFMT6_10_10_10_2_SINT = 59, 129 VFMT6_11_11_10_FLOAT = 66, 130 VFMT6_16_16_UNORM = 67, 131 VFMT6_16_16_SNORM = 68, 132 VFMT6_16_16_FLOAT = 69, 133 VFMT6_16_16_UINT = 70, 134 VFMT6_16_16_SINT = 71, 135 VFMT6_32_UNORM = 72, 136 VFMT6_32_SNORM = 73, 137 VFMT6_32_FLOAT = 74, 138 VFMT6_32_UINT = 75, 139 VFMT6_32_SINT = 76, 140 VFMT6_32_FIXED = 77, 141 VFMT6_16_16_16_UNORM = 88, 142 VFMT6_16_16_16_SNORM = 89, 143 VFMT6_16_16_16_FLOAT = 90, 144 VFMT6_16_16_16_UINT = 91, 145 VFMT6_16_16_16_SINT = 92, 146 VFMT6_16_16_16_16_UNORM = 96, 147 VFMT6_16_16_16_16_SNORM = 97, 148 VFMT6_16_16_16_16_FLOAT = 98, 149 VFMT6_16_16_16_16_UINT = 99, 150 VFMT6_16_16_16_16_SINT = 100, 151 VFMT6_32_32_UNORM = 101, 152 VFMT6_32_32_SNORM = 102, 153 VFMT6_32_32_FLOAT = 103, 154 VFMT6_32_32_UINT = 104, 155 VFMT6_32_32_SINT = 105, 156 VFMT6_32_32_FIXED = 106, 157 VFMT6_32_32_32_UNORM = 112, 158 VFMT6_32_32_32_SNORM = 113, 159 VFMT6_32_32_32_UINT = 114, 160 VFMT6_32_32_32_SINT = 115, 161 VFMT6_32_32_32_FLOAT = 116, 162 VFMT6_32_32_32_FIXED = 117, 163 VFMT6_32_32_32_32_UNORM = 128, 164 VFMT6_32_32_32_32_SNORM = 129, 165 VFMT6_32_32_32_32_FLOAT = 130, 166 VFMT6_32_32_32_32_UINT = 131, 167 VFMT6_32_32_32_32_SINT = 132, 168 VFMT6_32_32_32_32_FIXED = 133, 169 }; 170 171 enum a6xx_tex_fmt { 172 TFMT6_A8_UNORM = 2, 173 TFMT6_8_UNORM = 3, 174 TFMT6_8_SNORM = 4, 175 TFMT6_8_UINT = 5, 176 TFMT6_8_SINT = 6, 177 TFMT6_4_4_4_4_UNORM = 8, 178 TFMT6_5_5_5_1_UNORM = 10, 179 TFMT6_5_6_5_UNORM = 14, 180 TFMT6_8_8_UNORM = 15, 181 TFMT6_8_8_SNORM = 16, 182 TFMT6_8_8_UINT = 17, 183 TFMT6_8_8_SINT = 18, 184 TFMT6_L8_A8_UNORM = 19, 185 TFMT6_16_UNORM = 21, 186 TFMT6_16_SNORM = 22, 187 TFMT6_16_FLOAT = 23, 188 TFMT6_16_UINT = 24, 189 TFMT6_16_SINT = 25, 190 TFMT6_8_8_8_8_UNORM = 48, 191 TFMT6_8_8_8_UNORM = 49, 192 TFMT6_8_8_8_8_SNORM = 50, 193 TFMT6_8_8_8_8_UINT = 51, 194 TFMT6_8_8_8_8_SINT = 52, 195 TFMT6_9_9_9_E5_FLOAT = 53, 196 TFMT6_10_10_10_2_UNORM = 54, 197 TFMT6_10_10_10_2_UINT = 58, 198 TFMT6_11_11_10_FLOAT = 66, 199 TFMT6_16_16_UNORM = 67, 200 TFMT6_16_16_SNORM = 68, 201 TFMT6_16_16_FLOAT = 69, 202 TFMT6_16_16_UINT = 70, 203 TFMT6_16_16_SINT = 71, 204 TFMT6_32_FLOAT = 74, 205 TFMT6_32_UINT = 75, 206 TFMT6_32_SINT = 76, 207 TFMT6_16_16_16_16_UNORM = 96, 208 TFMT6_16_16_16_16_SNORM = 97, 209 TFMT6_16_16_16_16_FLOAT = 98, 210 TFMT6_16_16_16_16_UINT = 99, 211 TFMT6_16_16_16_16_SINT = 100, 212 TFMT6_32_32_FLOAT = 103, 213 TFMT6_32_32_UINT = 104, 214 TFMT6_32_32_SINT = 105, 215 TFMT6_32_32_32_UINT = 114, 216 TFMT6_32_32_32_SINT = 115, 217 TFMT6_32_32_32_FLOAT = 116, 218 TFMT6_32_32_32_32_FLOAT = 130, 219 TFMT6_32_32_32_32_UINT = 131, 220 TFMT6_32_32_32_32_SINT = 132, 221 TFMT6_X8Z24_UNORM = 160, 222 TFMT6_ETC2_RG11_UNORM = 171, 223 TFMT6_ETC2_RG11_SNORM = 172, 224 TFMT6_ETC2_R11_UNORM = 173, 225 TFMT6_ETC2_R11_SNORM = 174, 226 TFMT6_ETC1 = 175, 227 TFMT6_ETC2_RGB8 = 176, 228 TFMT6_ETC2_RGBA8 = 177, 229 TFMT6_ETC2_RGB8A1 = 178, 230 TFMT6_DXT1 = 179, 231 TFMT6_DXT3 = 180, 232 TFMT6_DXT5 = 181, 233 TFMT6_RGTC1_UNORM = 183, 234 TFMT6_RGTC1_SNORM = 184, 235 TFMT6_RGTC2_UNORM = 187, 236 TFMT6_RGTC2_SNORM = 188, 237 TFMT6_BPTC_UFLOAT = 190, 238 TFMT6_BPTC_FLOAT = 191, 239 TFMT6_BPTC = 192, 240 TFMT6_ASTC_4x4 = 193, 241 TFMT6_ASTC_5x4 = 194, 242 TFMT6_ASTC_5x5 = 195, 243 TFMT6_ASTC_6x5 = 196, 244 TFMT6_ASTC_6x6 = 197, 245 TFMT6_ASTC_8x5 = 198, 246 TFMT6_ASTC_8x6 = 199, 247 TFMT6_ASTC_8x8 = 200, 248 TFMT6_ASTC_10x5 = 201, 249 TFMT6_ASTC_10x6 = 202, 250 TFMT6_ASTC_10x8 = 203, 251 TFMT6_ASTC_10x10 = 204, 252 TFMT6_ASTC_12x10 = 205, 253 TFMT6_ASTC_12x12 = 206, 254 }; 255 256 enum a6xx_tex_fetchsize { 257 TFETCH6_1_BYTE = 0, 258 TFETCH6_2_BYTE = 1, 259 TFETCH6_4_BYTE = 2, 260 TFETCH6_8_BYTE = 3, 261 TFETCH6_16_BYTE = 4, 262 }; 263 264 enum a6xx_depth_format { 265 DEPTH6_NONE = 0, 266 DEPTH6_16 = 1, 267 DEPTH6_24_8 = 2, 268 DEPTH6_32 = 4, 269 }; 270 271 enum a6xx_shader_id { 272 A6XX_TP0_TMO_DATA = 9, 273 A6XX_TP0_SMO_DATA = 10, 274 A6XX_TP0_MIPMAP_BASE_DATA = 11, 275 A6XX_TP1_TMO_DATA = 25, 276 A6XX_TP1_SMO_DATA = 26, 277 A6XX_TP1_MIPMAP_BASE_DATA = 27, 278 A6XX_SP_INST_DATA = 41, 279 A6XX_SP_LB_0_DATA = 42, 280 A6XX_SP_LB_1_DATA = 43, 281 A6XX_SP_LB_2_DATA = 44, 282 A6XX_SP_LB_3_DATA = 45, 283 A6XX_SP_LB_4_DATA = 46, 284 A6XX_SP_LB_5_DATA = 47, 285 A6XX_SP_CB_BINDLESS_DATA = 48, 286 A6XX_SP_CB_LEGACY_DATA = 49, 287 A6XX_SP_UAV_DATA = 50, 288 A6XX_SP_INST_TAG = 51, 289 A6XX_SP_CB_BINDLESS_TAG = 52, 290 A6XX_SP_TMO_UMO_TAG = 53, 291 A6XX_SP_SMO_TAG = 54, 292 A6XX_SP_STATE_DATA = 55, 293 A6XX_HLSQ_CHUNK_CVS_RAM = 73, 294 A6XX_HLSQ_CHUNK_CPS_RAM = 74, 295 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 296 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 297 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 298 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 299 A6XX_HLSQ_CVS_MISC_RAM = 80, 300 A6XX_HLSQ_CPS_MISC_RAM = 81, 301 A6XX_HLSQ_INST_RAM = 82, 302 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 303 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 304 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 305 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 306 A6XX_HLSQ_INST_RAM_TAG = 87, 307 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 308 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 309 A6XX_HLSQ_PWR_REST_RAM = 90, 310 A6XX_HLSQ_PWR_REST_TAG = 91, 311 A6XX_HLSQ_DATAPATH_META = 96, 312 A6XX_HLSQ_FRONTEND_META = 97, 313 A6XX_HLSQ_INDIRECT_META = 98, 314 A6XX_HLSQ_BACKEND_META = 99, 315 }; 316 317 enum a6xx_debugbus_id { 318 A6XX_DBGBUS_CP = 1, 319 A6XX_DBGBUS_RBBM = 2, 320 A6XX_DBGBUS_VBIF = 3, 321 A6XX_DBGBUS_HLSQ = 4, 322 A6XX_DBGBUS_UCHE = 5, 323 A6XX_DBGBUS_DPM = 6, 324 A6XX_DBGBUS_TESS = 7, 325 A6XX_DBGBUS_PC = 8, 326 A6XX_DBGBUS_VFDP = 9, 327 A6XX_DBGBUS_VPC = 10, 328 A6XX_DBGBUS_TSE = 11, 329 A6XX_DBGBUS_RAS = 12, 330 A6XX_DBGBUS_VSC = 13, 331 A6XX_DBGBUS_COM = 14, 332 A6XX_DBGBUS_LRZ = 16, 333 A6XX_DBGBUS_A2D = 17, 334 A6XX_DBGBUS_CCUFCHE = 18, 335 A6XX_DBGBUS_GMU_CX = 19, 336 A6XX_DBGBUS_RBP = 20, 337 A6XX_DBGBUS_DCS = 21, 338 A6XX_DBGBUS_DBGC = 22, 339 A6XX_DBGBUS_CX = 23, 340 A6XX_DBGBUS_GMU_GX = 24, 341 A6XX_DBGBUS_TPFCHE = 25, 342 A6XX_DBGBUS_GBIF_GX = 26, 343 A6XX_DBGBUS_GPC = 29, 344 A6XX_DBGBUS_LARC = 30, 345 A6XX_DBGBUS_HLSQ_SPTP = 31, 346 A6XX_DBGBUS_RB_0 = 32, 347 A6XX_DBGBUS_RB_1 = 33, 348 A6XX_DBGBUS_UCHE_WRAPPER = 36, 349 A6XX_DBGBUS_CCU_0 = 40, 350 A6XX_DBGBUS_CCU_1 = 41, 351 A6XX_DBGBUS_VFD_0 = 56, 352 A6XX_DBGBUS_VFD_1 = 57, 353 A6XX_DBGBUS_VFD_2 = 58, 354 A6XX_DBGBUS_VFD_3 = 59, 355 A6XX_DBGBUS_SP_0 = 64, 356 A6XX_DBGBUS_SP_1 = 65, 357 A6XX_DBGBUS_TPL1_0 = 72, 358 A6XX_DBGBUS_TPL1_1 = 73, 359 A6XX_DBGBUS_TPL1_2 = 74, 360 A6XX_DBGBUS_TPL1_3 = 75, 361 }; 362 363 enum a6xx_cp_perfcounter_select { 364 PERF_CP_ALWAYS_COUNT = 0, 365 PERF_CP_BUSY_GFX_CORE_IDLE = 1, 366 PERF_CP_BUSY_CYCLES = 2, 367 PERF_CP_NUM_PREEMPTIONS = 3, 368 PERF_CP_PREEMPTION_REACTION_DELAY = 4, 369 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 370 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 371 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 372 PERF_CP_PREDICATED_DRAWS_KILLED = 8, 373 PERF_CP_MODE_SWITCH = 9, 374 PERF_CP_ZPASS_DONE = 10, 375 PERF_CP_CONTEXT_DONE = 11, 376 PERF_CP_CACHE_FLUSH = 12, 377 PERF_CP_LONG_PREEMPTIONS = 13, 378 PERF_CP_SQE_I_CACHE_STARVE = 14, 379 PERF_CP_SQE_IDLE = 15, 380 PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 381 PERF_CP_SQE_PM4_STARVE_SDS = 17, 382 PERF_CP_SQE_MRB_STARVE = 18, 383 PERF_CP_SQE_RRB_STARVE = 19, 384 PERF_CP_SQE_VSD_STARVE = 20, 385 PERF_CP_VSD_DECODE_STARVE = 21, 386 PERF_CP_SQE_PIPE_OUT_STALL = 22, 387 PERF_CP_SQE_SYNC_STALL = 23, 388 PERF_CP_SQE_PM4_WFI_STALL = 24, 389 PERF_CP_SQE_SYS_WFI_STALL = 25, 390 PERF_CP_SQE_T4_EXEC = 26, 391 PERF_CP_SQE_LOAD_STATE_EXEC = 27, 392 PERF_CP_SQE_SAVE_SDS_STATE = 28, 393 PERF_CP_SQE_DRAW_EXEC = 29, 394 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 395 PERF_CP_SQE_EXEC_PROFILED = 31, 396 PERF_CP_MEMORY_POOL_EMPTY = 32, 397 PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 398 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 399 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 400 PERF_CP_AHB_STALL_SQE_GMU = 36, 401 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 402 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 403 PERF_CP_CLUSTER0_EMPTY = 39, 404 PERF_CP_CLUSTER1_EMPTY = 40, 405 PERF_CP_CLUSTER2_EMPTY = 41, 406 PERF_CP_CLUSTER3_EMPTY = 42, 407 PERF_CP_CLUSTER4_EMPTY = 43, 408 PERF_CP_CLUSTER5_EMPTY = 44, 409 PERF_CP_PM4_DATA = 45, 410 PERF_CP_PM4_HEADERS = 46, 411 PERF_CP_VBIF_READ_BEATS = 47, 412 PERF_CP_VBIF_WRITE_BEATS = 48, 413 PERF_CP_SQE_INSTR_COUNTER = 49, 414 }; 415 416 enum a6xx_rbbm_perfcounter_select { 417 PERF_RBBM_ALWAYS_COUNT = 0, 418 PERF_RBBM_ALWAYS_ON = 1, 419 PERF_RBBM_TSE_BUSY = 2, 420 PERF_RBBM_RAS_BUSY = 3, 421 PERF_RBBM_PC_DCALL_BUSY = 4, 422 PERF_RBBM_PC_VSD_BUSY = 5, 423 PERF_RBBM_STATUS_MASKED = 6, 424 PERF_RBBM_COM_BUSY = 7, 425 PERF_RBBM_DCOM_BUSY = 8, 426 PERF_RBBM_VBIF_BUSY = 9, 427 PERF_RBBM_VSC_BUSY = 10, 428 PERF_RBBM_TESS_BUSY = 11, 429 PERF_RBBM_UCHE_BUSY = 12, 430 PERF_RBBM_HLSQ_BUSY = 13, 431 }; 432 433 enum a6xx_pc_perfcounter_select { 434 PERF_PC_BUSY_CYCLES = 0, 435 PERF_PC_WORKING_CYCLES = 1, 436 PERF_PC_STALL_CYCLES_VFD = 2, 437 PERF_PC_STALL_CYCLES_TSE = 3, 438 PERF_PC_STALL_CYCLES_VPC = 4, 439 PERF_PC_STALL_CYCLES_UCHE = 5, 440 PERF_PC_STALL_CYCLES_TESS = 6, 441 PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 442 PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 443 PERF_PC_PASS1_TF_STALL_CYCLES = 9, 444 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 445 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 446 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 447 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 448 PERF_PC_STARVE_CYCLES_DI = 14, 449 PERF_PC_VIS_STREAMS_LOADED = 15, 450 PERF_PC_INSTANCES = 16, 451 PERF_PC_VPC_PRIMITIVES = 17, 452 PERF_PC_DEAD_PRIM = 18, 453 PERF_PC_LIVE_PRIM = 19, 454 PERF_PC_VERTEX_HITS = 20, 455 PERF_PC_IA_VERTICES = 21, 456 PERF_PC_IA_PRIMITIVES = 22, 457 PERF_PC_GS_PRIMITIVES = 23, 458 PERF_PC_HS_INVOCATIONS = 24, 459 PERF_PC_DS_INVOCATIONS = 25, 460 PERF_PC_VS_INVOCATIONS = 26, 461 PERF_PC_GS_INVOCATIONS = 27, 462 PERF_PC_DS_PRIMITIVES = 28, 463 PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 464 PERF_PC_3D_DRAWCALLS = 30, 465 PERF_PC_2D_DRAWCALLS = 31, 466 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 467 PERF_TESS_BUSY_CYCLES = 33, 468 PERF_TESS_WORKING_CYCLES = 34, 469 PERF_TESS_STALL_CYCLES_PC = 35, 470 PERF_TESS_STARVE_CYCLES_PC = 36, 471 PERF_PC_TSE_TRANSACTION = 37, 472 PERF_PC_TSE_VERTEX = 38, 473 PERF_PC_TESS_PC_UV_TRANS = 39, 474 PERF_PC_TESS_PC_UV_PATCHES = 40, 475 PERF_PC_TESS_FACTOR_TRANS = 41, 476 }; 477 478 enum a6xx_vfd_perfcounter_select { 479 PERF_VFD_BUSY_CYCLES = 0, 480 PERF_VFD_STALL_CYCLES_UCHE = 1, 481 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 482 PERF_VFD_STALL_CYCLES_SP_INFO = 3, 483 PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 484 PERF_VFD_STARVE_CYCLES_UCHE = 5, 485 PERF_VFD_RBUFFER_FULL = 6, 486 PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 487 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 488 PERF_VFD_NUM_ATTRIBUTES = 9, 489 PERF_VFD_UPPER_SHADER_FIBERS = 10, 490 PERF_VFD_LOWER_SHADER_FIBERS = 11, 491 PERF_VFD_MODE_0_FIBERS = 12, 492 PERF_VFD_MODE_1_FIBERS = 13, 493 PERF_VFD_MODE_2_FIBERS = 14, 494 PERF_VFD_MODE_3_FIBERS = 15, 495 PERF_VFD_MODE_4_FIBERS = 16, 496 PERF_VFD_TOTAL_VERTICES = 17, 497 PERF_VFDP_STALL_CYCLES_VFD = 18, 498 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 499 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 500 PERF_VFDP_STARVE_CYCLES_PC = 21, 501 PERF_VFDP_VS_STAGE_WAVES = 22, 502 }; 503 504 enum a6xx_hlsq_perfcounter_select { 505 PERF_HLSQ_BUSY_CYCLES = 0, 506 PERF_HLSQ_STALL_CYCLES_UCHE = 1, 507 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 508 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 509 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 510 PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 511 PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 512 PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 513 PERF_HLSQ_QUADS = 8, 514 PERF_HLSQ_CS_INVOCATIONS = 9, 515 PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 516 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 517 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 518 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 519 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 520 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 521 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 522 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 523 PERF_HLSQ_STALL_CYCLES_VPC = 18, 524 PERF_HLSQ_PIXELS = 19, 525 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 526 }; 527 528 enum a6xx_vpc_perfcounter_select { 529 PERF_VPC_BUSY_CYCLES = 0, 530 PERF_VPC_WORKING_CYCLES = 1, 531 PERF_VPC_STALL_CYCLES_UCHE = 2, 532 PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 533 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 534 PERF_VPC_STALL_CYCLES_PC = 5, 535 PERF_VPC_STALL_CYCLES_SP_LM = 6, 536 PERF_VPC_STARVE_CYCLES_SP = 7, 537 PERF_VPC_STARVE_CYCLES_LRZ = 8, 538 PERF_VPC_PC_PRIMITIVES = 9, 539 PERF_VPC_SP_COMPONENTS = 10, 540 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 541 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 542 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 543 PERF_VPC_LM_TRANSACTION = 14, 544 PERF_VPC_STREAMOUT_TRANSACTION = 15, 545 PERF_VPC_VS_BUSY_CYCLES = 16, 546 PERF_VPC_PS_BUSY_CYCLES = 17, 547 PERF_VPC_VS_WORKING_CYCLES = 18, 548 PERF_VPC_PS_WORKING_CYCLES = 19, 549 PERF_VPC_STARVE_CYCLES_RB = 20, 550 PERF_VPC_NUM_VPCRAM_READ_POS = 21, 551 PERF_VPC_WIT_FULL_CYCLES = 22, 552 PERF_VPC_VPCRAM_FULL_CYCLES = 23, 553 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 554 PERF_VPC_NUM_VPCRAM_WRITE = 25, 555 PERF_VPC_NUM_VPCRAM_READ_SO = 26, 556 PERF_VPC_NUM_ATTR_REQ_LM = 27, 557 }; 558 559 enum a6xx_tse_perfcounter_select { 560 PERF_TSE_BUSY_CYCLES = 0, 561 PERF_TSE_CLIPPING_CYCLES = 1, 562 PERF_TSE_STALL_CYCLES_RAS = 2, 563 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 564 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 565 PERF_TSE_STARVE_CYCLES_PC = 5, 566 PERF_TSE_INPUT_PRIM = 6, 567 PERF_TSE_INPUT_NULL_PRIM = 7, 568 PERF_TSE_TRIVAL_REJ_PRIM = 8, 569 PERF_TSE_CLIPPED_PRIM = 9, 570 PERF_TSE_ZERO_AREA_PRIM = 10, 571 PERF_TSE_FACENESS_CULLED_PRIM = 11, 572 PERF_TSE_ZERO_PIXEL_PRIM = 12, 573 PERF_TSE_OUTPUT_NULL_PRIM = 13, 574 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 575 PERF_TSE_CINVOCATION = 15, 576 PERF_TSE_CPRIMITIVES = 16, 577 PERF_TSE_2D_INPUT_PRIM = 17, 578 PERF_TSE_2D_ALIVE_CYCLES = 18, 579 PERF_TSE_CLIP_PLANES = 19, 580 }; 581 582 enum a6xx_ras_perfcounter_select { 583 PERF_RAS_BUSY_CYCLES = 0, 584 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 585 PERF_RAS_STALL_CYCLES_LRZ = 2, 586 PERF_RAS_STARVE_CYCLES_TSE = 3, 587 PERF_RAS_SUPER_TILES = 4, 588 PERF_RAS_8X4_TILES = 5, 589 PERF_RAS_MASKGEN_ACTIVE = 6, 590 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 591 PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 592 PERF_RAS_PRIM_KILLED_INVISILBE = 9, 593 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 594 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 595 PERF_RAS_BLOCKS = 12, 596 }; 597 598 enum a6xx_uche_perfcounter_select { 599 PERF_UCHE_BUSY_CYCLES = 0, 600 PERF_UCHE_STALL_CYCLES_ARBITER = 1, 601 PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 602 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 603 PERF_UCHE_VBIF_READ_BEATS_TP = 4, 604 PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 605 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 606 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 607 PERF_UCHE_VBIF_READ_BEATS_SP = 8, 608 PERF_UCHE_READ_REQUESTS_TP = 9, 609 PERF_UCHE_READ_REQUESTS_VFD = 10, 610 PERF_UCHE_READ_REQUESTS_HLSQ = 11, 611 PERF_UCHE_READ_REQUESTS_LRZ = 12, 612 PERF_UCHE_READ_REQUESTS_SP = 13, 613 PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 614 PERF_UCHE_WRITE_REQUESTS_SP = 15, 615 PERF_UCHE_WRITE_REQUESTS_VPC = 16, 616 PERF_UCHE_WRITE_REQUESTS_VSC = 17, 617 PERF_UCHE_EVICTS = 18, 618 PERF_UCHE_BANK_REQ0 = 19, 619 PERF_UCHE_BANK_REQ1 = 20, 620 PERF_UCHE_BANK_REQ2 = 21, 621 PERF_UCHE_BANK_REQ3 = 22, 622 PERF_UCHE_BANK_REQ4 = 23, 623 PERF_UCHE_BANK_REQ5 = 24, 624 PERF_UCHE_BANK_REQ6 = 25, 625 PERF_UCHE_BANK_REQ7 = 26, 626 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 627 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 628 PERF_UCHE_GMEM_READ_BEATS = 29, 629 PERF_UCHE_TPH_REF_FULL = 30, 630 PERF_UCHE_TPH_VICTIM_FULL = 31, 631 PERF_UCHE_TPH_EXT_FULL = 32, 632 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 633 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 634 PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 635 PERF_UCHE_VBIF_READ_BEATS_PC = 36, 636 PERF_UCHE_READ_REQUESTS_PC = 37, 637 PERF_UCHE_RAM_READ_REQ = 38, 638 PERF_UCHE_RAM_WRITE_REQ = 39, 639 }; 640 641 enum a6xx_tp_perfcounter_select { 642 PERF_TP_BUSY_CYCLES = 0, 643 PERF_TP_STALL_CYCLES_UCHE = 1, 644 PERF_TP_LATENCY_CYCLES = 2, 645 PERF_TP_LATENCY_TRANS = 3, 646 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 647 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 648 PERF_TP_L1_CACHELINE_REQUESTS = 6, 649 PERF_TP_L1_CACHELINE_MISSES = 7, 650 PERF_TP_SP_TP_TRANS = 8, 651 PERF_TP_TP_SP_TRANS = 9, 652 PERF_TP_OUTPUT_PIXELS = 10, 653 PERF_TP_FILTER_WORKLOAD_16BIT = 11, 654 PERF_TP_FILTER_WORKLOAD_32BIT = 12, 655 PERF_TP_QUADS_RECEIVED = 13, 656 PERF_TP_QUADS_OFFSET = 14, 657 PERF_TP_QUADS_SHADOW = 15, 658 PERF_TP_QUADS_ARRAY = 16, 659 PERF_TP_QUADS_GRADIENT = 17, 660 PERF_TP_QUADS_1D = 18, 661 PERF_TP_QUADS_2D = 19, 662 PERF_TP_QUADS_BUFFER = 20, 663 PERF_TP_QUADS_3D = 21, 664 PERF_TP_QUADS_CUBE = 22, 665 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 666 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 667 PERF_TP_OUTPUT_PIXELS_POINT = 25, 668 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 669 PERF_TP_OUTPUT_PIXELS_MIP = 27, 670 PERF_TP_OUTPUT_PIXELS_ANISO = 28, 671 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 672 PERF_TP_FLAG_CACHE_REQUESTS = 30, 673 PERF_TP_FLAG_CACHE_MISSES = 31, 674 PERF_TP_L1_5_L2_REQUESTS = 32, 675 PERF_TP_2D_OUTPUT_PIXELS = 33, 676 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 677 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 678 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 679 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 680 PERF_TP_TPA2TPC_TRANS = 38, 681 PERF_TP_L1_MISSES_ASTC_1TILE = 39, 682 PERF_TP_L1_MISSES_ASTC_2TILE = 40, 683 PERF_TP_L1_MISSES_ASTC_4TILE = 41, 684 PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 685 PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 686 PERF_TP_L1_BANK_CONFLICT = 44, 687 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 688 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 689 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 690 PERF_TP_FRONTEND_WORKING_CYCLES = 48, 691 PERF_TP_L1_TAG_WORKING_CYCLES = 49, 692 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 693 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 694 PERF_TP_BACKEND_WORKING_CYCLES = 52, 695 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 696 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 697 PERF_TP_STARVE_CYCLES_SP = 55, 698 PERF_TP_STARVE_CYCLES_UCHE = 56, 699 }; 700 701 enum a6xx_sp_perfcounter_select { 702 PERF_SP_BUSY_CYCLES = 0, 703 PERF_SP_ALU_WORKING_CYCLES = 1, 704 PERF_SP_EFU_WORKING_CYCLES = 2, 705 PERF_SP_STALL_CYCLES_VPC = 3, 706 PERF_SP_STALL_CYCLES_TP = 4, 707 PERF_SP_STALL_CYCLES_UCHE = 5, 708 PERF_SP_STALL_CYCLES_RB = 6, 709 PERF_SP_NON_EXECUTION_CYCLES = 7, 710 PERF_SP_WAVE_CONTEXTS = 8, 711 PERF_SP_WAVE_CONTEXT_CYCLES = 9, 712 PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 713 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 714 PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 715 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 716 PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 717 PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 718 PERF_SP_WAVE_CTRL_CYCLES = 16, 719 PERF_SP_WAVE_LOAD_CYCLES = 17, 720 PERF_SP_WAVE_EMIT_CYCLES = 18, 721 PERF_SP_WAVE_NOP_CYCLES = 19, 722 PERF_SP_WAVE_WAIT_CYCLES = 20, 723 PERF_SP_WAVE_FETCH_CYCLES = 21, 724 PERF_SP_WAVE_IDLE_CYCLES = 22, 725 PERF_SP_WAVE_END_CYCLES = 23, 726 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 727 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 728 PERF_SP_WAVE_JOIN_CYCLES = 26, 729 PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 730 PERF_SP_LM_STORE_INSTRUCTIONS = 28, 731 PERF_SP_LM_ATOMICS = 29, 732 PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 733 PERF_SP_GM_STORE_INSTRUCTIONS = 31, 734 PERF_SP_GM_ATOMICS = 32, 735 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 736 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 737 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 738 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 739 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 740 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 741 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 742 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 743 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 744 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 745 PERF_SP_VS_INSTRUCTIONS = 43, 746 PERF_SP_FS_INSTRUCTIONS = 44, 747 PERF_SP_ADDR_LOCK_COUNT = 45, 748 PERF_SP_UCHE_READ_TRANS = 46, 749 PERF_SP_UCHE_WRITE_TRANS = 47, 750 PERF_SP_EXPORT_VPC_TRANS = 48, 751 PERF_SP_EXPORT_RB_TRANS = 49, 752 PERF_SP_PIXELS_KILLED = 50, 753 PERF_SP_ICL1_REQUESTS = 51, 754 PERF_SP_ICL1_MISSES = 52, 755 PERF_SP_HS_INSTRUCTIONS = 53, 756 PERF_SP_DS_INSTRUCTIONS = 54, 757 PERF_SP_GS_INSTRUCTIONS = 55, 758 PERF_SP_CS_INSTRUCTIONS = 56, 759 PERF_SP_GPR_READ = 57, 760 PERF_SP_GPR_WRITE = 58, 761 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 762 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 763 PERF_SP_LM_BANK_CONFLICTS = 61, 764 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 765 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 766 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 767 PERF_SP_LM_WORKING_CYCLES = 65, 768 PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 769 PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 770 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 771 PERF_SP_STARVE_CYCLES_HLSQ = 69, 772 PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 773 PERF_SP_WORKING_EU = 71, 774 PERF_SP_ANY_EU_WORKING = 72, 775 PERF_SP_WORKING_EU_FS_STAGE = 73, 776 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 777 PERF_SP_WORKING_EU_VS_STAGE = 75, 778 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 779 PERF_SP_WORKING_EU_CS_STAGE = 77, 780 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 781 PERF_SP_GPR_READ_PREFETCH = 79, 782 PERF_SP_GPR_READ_CONFLICT = 80, 783 PERF_SP_GPR_WRITE_CONFLICT = 81, 784 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 785 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 786 PERF_SP_EXECUTABLE_WAVES = 84, 787 }; 788 789 enum a6xx_rb_perfcounter_select { 790 PERF_RB_BUSY_CYCLES = 0, 791 PERF_RB_STALL_CYCLES_HLSQ = 1, 792 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 793 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 794 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 795 PERF_RB_STARVE_CYCLES_SP = 5, 796 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 797 PERF_RB_STARVE_CYCLES_CCU = 7, 798 PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 799 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 800 PERF_RB_Z_WORKLOAD = 10, 801 PERF_RB_HLSQ_ACTIVE = 11, 802 PERF_RB_Z_READ = 12, 803 PERF_RB_Z_WRITE = 13, 804 PERF_RB_C_READ = 14, 805 PERF_RB_C_WRITE = 15, 806 PERF_RB_TOTAL_PASS = 16, 807 PERF_RB_Z_PASS = 17, 808 PERF_RB_Z_FAIL = 18, 809 PERF_RB_S_FAIL = 19, 810 PERF_RB_BLENDED_FXP_COMPONENTS = 20, 811 PERF_RB_BLENDED_FP16_COMPONENTS = 21, 812 PERF_RB_PS_INVOCATIONS = 22, 813 PERF_RB_2D_ALIVE_CYCLES = 23, 814 PERF_RB_2D_STALL_CYCLES_A2D = 24, 815 PERF_RB_2D_STARVE_CYCLES_SRC = 25, 816 PERF_RB_2D_STARVE_CYCLES_SP = 26, 817 PERF_RB_2D_STARVE_CYCLES_DST = 27, 818 PERF_RB_2D_VALID_PIXELS = 28, 819 PERF_RB_3D_PIXELS = 29, 820 PERF_RB_BLENDER_WORKING_CYCLES = 30, 821 PERF_RB_ZPROC_WORKING_CYCLES = 31, 822 PERF_RB_CPROC_WORKING_CYCLES = 32, 823 PERF_RB_SAMPLER_WORKING_CYCLES = 33, 824 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 825 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 826 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 827 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 828 PERF_RB_STALL_CYCLES_VPC = 38, 829 PERF_RB_2D_INPUT_TRANS = 39, 830 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 831 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 832 PERF_RB_BLENDED_FP32_COMPONENTS = 42, 833 PERF_RB_COLOR_PIX_TILES = 43, 834 PERF_RB_STALL_CYCLES_CCU = 44, 835 PERF_RB_EARLY_Z_ARB3_GRANT = 45, 836 PERF_RB_LATE_Z_ARB3_GRANT = 46, 837 PERF_RB_EARLY_Z_SKIP_GRANT = 47, 838 }; 839 840 enum a6xx_vsc_perfcounter_select { 841 PERF_VSC_BUSY_CYCLES = 0, 842 PERF_VSC_WORKING_CYCLES = 1, 843 PERF_VSC_STALL_CYCLES_UCHE = 2, 844 PERF_VSC_EOT_NUM = 3, 845 PERF_VSC_INPUT_TILES = 4, 846 }; 847 848 enum a6xx_ccu_perfcounter_select { 849 PERF_CCU_BUSY_CYCLES = 0, 850 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 851 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 852 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 853 PERF_CCU_DEPTH_BLOCKS = 4, 854 PERF_CCU_COLOR_BLOCKS = 5, 855 PERF_CCU_DEPTH_BLOCK_HIT = 6, 856 PERF_CCU_COLOR_BLOCK_HIT = 7, 857 PERF_CCU_PARTIAL_BLOCK_READ = 8, 858 PERF_CCU_GMEM_READ = 9, 859 PERF_CCU_GMEM_WRITE = 10, 860 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 861 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 862 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 863 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 864 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 865 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 866 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 867 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 868 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 869 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 870 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 871 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 872 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 873 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 874 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 875 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 876 PERF_CCU_2D_RD_REQ = 27, 877 PERF_CCU_2D_WR_REQ = 28, 878 }; 879 880 enum a6xx_lrz_perfcounter_select { 881 PERF_LRZ_BUSY_CYCLES = 0, 882 PERF_LRZ_STARVE_CYCLES_RAS = 1, 883 PERF_LRZ_STALL_CYCLES_RB = 2, 884 PERF_LRZ_STALL_CYCLES_VSC = 3, 885 PERF_LRZ_STALL_CYCLES_VPC = 4, 886 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 887 PERF_LRZ_STALL_CYCLES_UCHE = 6, 888 PERF_LRZ_LRZ_READ = 7, 889 PERF_LRZ_LRZ_WRITE = 8, 890 PERF_LRZ_READ_LATENCY = 9, 891 PERF_LRZ_MERGE_CACHE_UPDATING = 10, 892 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 893 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 894 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 895 PERF_LRZ_FULL_8X8_TILES = 14, 896 PERF_LRZ_PARTIAL_8X8_TILES = 15, 897 PERF_LRZ_TILE_KILLED = 16, 898 PERF_LRZ_TOTAL_PIXEL = 17, 899 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 900 PERF_LRZ_FULLY_COVERED_TILES = 19, 901 PERF_LRZ_PARTIAL_COVERED_TILES = 20, 902 PERF_LRZ_FEEDBACK_ACCEPT = 21, 903 PERF_LRZ_FEEDBACK_DISCARD = 22, 904 PERF_LRZ_FEEDBACK_STALL = 23, 905 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 906 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 907 PERF_LRZ_STALL_CYCLES_VC = 26, 908 PERF_LRZ_RAS_MASK_TRANS = 27, 909 }; 910 911 enum a6xx_cmp_perfcounter_select { 912 PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 913 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 914 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 915 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 916 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 917 PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 918 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 919 PERF_CMPDECMP_VBIF_READ_DATA = 7, 920 PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 921 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 922 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 923 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 924 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 925 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 926 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 927 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 928 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 929 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 930 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 931 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 932 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 933 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 934 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 935 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 936 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 937 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 938 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 939 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 940 PERF_CMPDECMP_2D_RD_DATA = 28, 941 PERF_CMPDECMP_2D_WR_DATA = 29, 942 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 943 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 944 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 945 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 946 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 947 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 948 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 949 PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 950 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 951 PERF_CMPDECMP_2D_PIXELS = 39, 952 }; 953 954 enum a6xx_2d_ifmt { 955 R2D_UNORM8 = 16, 956 R2D_INT32 = 7, 957 R2D_INT16 = 6, 958 R2D_INT8 = 5, 959 R2D_FLOAT32 = 4, 960 R2D_FLOAT16 = 3, 961 }; 962 963 enum a6xx_tex_filter { 964 A6XX_TEX_NEAREST = 0, 965 A6XX_TEX_LINEAR = 1, 966 A6XX_TEX_ANISO = 2, 967 }; 968 969 enum a6xx_tex_clamp { 970 A6XX_TEX_REPEAT = 0, 971 A6XX_TEX_CLAMP_TO_EDGE = 1, 972 A6XX_TEX_MIRROR_REPEAT = 2, 973 A6XX_TEX_CLAMP_TO_BORDER = 3, 974 A6XX_TEX_MIRROR_CLAMP = 4, 975 }; 976 977 enum a6xx_tex_aniso { 978 A6XX_TEX_ANISO_1 = 0, 979 A6XX_TEX_ANISO_2 = 1, 980 A6XX_TEX_ANISO_4 = 2, 981 A6XX_TEX_ANISO_8 = 3, 982 A6XX_TEX_ANISO_16 = 4, 983 }; 984 985 enum a6xx_tex_swiz { 986 A6XX_TEX_X = 0, 987 A6XX_TEX_Y = 1, 988 A6XX_TEX_Z = 2, 989 A6XX_TEX_W = 3, 990 A6XX_TEX_ZERO = 4, 991 A6XX_TEX_ONE = 5, 992 }; 993 994 enum a6xx_tex_type { 995 A6XX_TEX_1D = 0, 996 A6XX_TEX_2D = 1, 997 A6XX_TEX_CUBE = 2, 998 A6XX_TEX_3D = 3, 999 }; 1000 1001 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 1002 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 1003 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 1004 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 1005 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 1006 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 1007 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 1008 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 1009 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 1010 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 1011 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 1012 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 1013 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 1014 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 1015 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 1016 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 1017 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 1018 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 1019 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 1020 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 1021 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 1022 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 1023 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 1024 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 1025 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 1026 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 1027 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 1028 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 1029 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 1030 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 1031 #define REG_A6XX_CP_RB_BASE 0x00000800 1032 1033 #define REG_A6XX_CP_RB_BASE_HI 0x00000801 1034 1035 #define REG_A6XX_CP_RB_CNTL 0x00000802 1036 1037 #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 1038 1039 #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 1040 1041 #define REG_A6XX_CP_RB_RPTR 0x00000806 1042 1043 #define REG_A6XX_CP_RB_WPTR 0x00000807 1044 1045 #define REG_A6XX_CP_SQE_CNTL 0x00000808 1046 1047 #define REG_A6XX_CP_HW_FAULT 0x00000821 1048 1049 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 1050 1051 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 1052 1053 #define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830 1054 1055 #define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831 1056 1057 #define REG_A6XX_CP_MISC_CNTL 0x00000840 1058 1059 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1060 1061 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1062 1063 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 1064 1065 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 1066 1067 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 1068 1069 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 1070 1071 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 1072 1073 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 1074 1075 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 1076 1077 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 1078 1079 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 1080 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 1081 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 1082 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 1083 { 1084 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 1085 } 1086 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 1087 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 1088 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 1089 { 1090 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 1091 } 1092 #define A6XX_CP_PROTECT_REG_READ 0x80000000 1093 1094 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 1095 1096 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 1097 1098 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 1099 1100 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 1101 1102 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 1103 1104 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 1105 1106 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 1107 1108 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 1109 1110 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 1111 1112 #define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0 1113 1114 #define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1 1115 1116 #define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2 1117 1118 #define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3 1119 1120 #define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4 1121 1122 #define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5 1123 1124 #define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6 1125 1126 #define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7 1127 1128 #define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8 1129 1130 #define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9 1131 1132 #define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da 1133 1134 #define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db 1135 1136 #define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc 1137 1138 #define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd 1139 1140 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 1141 1142 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 1143 1144 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 1145 1146 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 1147 1148 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 1149 1150 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 1151 1152 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 1153 1154 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 1155 1156 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 1157 1158 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 1159 1160 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 1161 1162 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 1163 1164 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 1165 1166 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 1167 1168 #define REG_A6XX_CP_IB1_BASE 0x00000928 1169 1170 #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 1171 1172 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 1173 1174 #define REG_A6XX_CP_IB2_BASE 0x0000092b 1175 1176 #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 1177 1178 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 1179 1180 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 1181 1182 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 1183 1184 #define REG_A6XX_CP_AHB_CNTL 0x0000098d 1185 1186 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 1187 1188 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 1189 1190 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 1191 1192 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 1193 1194 #define REG_A6XX_RBBM_STATUS 0x00000210 1195 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 1196 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 1197 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 1198 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 1199 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 1200 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 1201 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 1202 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 1203 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 1204 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 1205 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 1206 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 1207 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 1208 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 1209 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 1210 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 1211 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 1212 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 1213 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 1214 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 1215 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 1216 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 1217 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 1218 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 1219 1220 #define REG_A6XX_RBBM_STATUS3 0x00000213 1221 1222 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 1223 1224 #define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400 1225 1226 #define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401 1227 1228 #define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402 1229 1230 #define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403 1231 1232 #define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404 1233 1234 #define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405 1235 1236 #define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406 1237 1238 #define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407 1239 1240 #define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408 1241 1242 #define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409 1243 1244 #define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a 1245 1246 #define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b 1247 1248 #define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c 1249 1250 #define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d 1251 1252 #define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e 1253 1254 #define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f 1255 1256 #define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410 1257 1258 #define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411 1259 1260 #define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412 1261 1262 #define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413 1263 1264 #define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414 1265 1266 #define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415 1267 1268 #define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416 1269 1270 #define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417 1271 1272 #define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418 1273 1274 #define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419 1275 1276 #define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a 1277 1278 #define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b 1279 1280 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c 1281 1282 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d 1283 1284 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e 1285 1286 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f 1287 1288 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420 1289 1290 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421 1291 1292 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422 1293 1294 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423 1295 1296 #define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424 1297 1298 #define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425 1299 1300 #define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426 1301 1302 #define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427 1303 1304 #define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428 1305 1306 #define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429 1307 1308 #define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a 1309 1310 #define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b 1311 1312 #define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c 1313 1314 #define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d 1315 1316 #define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e 1317 1318 #define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f 1319 1320 #define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430 1321 1322 #define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431 1323 1324 #define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432 1325 1326 #define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433 1327 1328 #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434 1329 1330 #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435 1331 1332 #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436 1333 1334 #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437 1335 1336 #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438 1337 1338 #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439 1339 1340 #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a 1341 1342 #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b 1343 1344 #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c 1345 1346 #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d 1347 1348 #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e 1349 1350 #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f 1351 1352 #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440 1353 1354 #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441 1355 1356 #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442 1357 1358 #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443 1359 1360 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444 1361 1362 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445 1363 1364 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446 1365 1366 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447 1367 1368 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448 1369 1370 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449 1371 1372 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a 1373 1374 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b 1375 1376 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c 1377 1378 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d 1379 1380 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e 1381 1382 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f 1383 1384 #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450 1385 1386 #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451 1387 1388 #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452 1389 1390 #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453 1391 1392 #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454 1393 1394 #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455 1395 1396 #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456 1397 1398 #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457 1399 1400 #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458 1401 1402 #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459 1403 1404 #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a 1405 1406 #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b 1407 1408 #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c 1409 1410 #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d 1411 1412 #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e 1413 1414 #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f 1415 1416 #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460 1417 1418 #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461 1419 1420 #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462 1421 1422 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463 1423 1424 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464 1425 1426 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 1427 1428 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 1429 1430 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 1431 1432 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 1433 1434 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 1435 1436 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a 1437 1438 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 1439 1440 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 1441 1442 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 1443 1444 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 1445 1446 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 1447 1448 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a 1449 1450 #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b 1451 1452 #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c 1453 1454 #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d 1455 1456 #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e 1457 1458 #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f 1459 1460 #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470 1461 1462 #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471 1463 1464 #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472 1465 1466 #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473 1467 1468 #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474 1469 1470 #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475 1471 1472 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476 1473 1474 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477 1475 1476 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478 1477 1478 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479 1479 1480 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a 1481 1482 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b 1483 1484 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c 1485 1486 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d 1487 1488 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e 1489 1490 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f 1491 1492 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480 1493 1494 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481 1495 1496 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482 1497 1498 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483 1499 1500 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484 1501 1502 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485 1503 1504 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486 1505 1506 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487 1507 1508 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488 1509 1510 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489 1511 1512 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a 1513 1514 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b 1515 1516 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c 1517 1518 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d 1519 1520 #define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e 1521 1522 #define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f 1523 1524 #define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490 1525 1526 #define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491 1527 1528 #define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492 1529 1530 #define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493 1531 1532 #define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494 1533 1534 #define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495 1535 1536 #define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496 1537 1538 #define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497 1539 1540 #define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498 1541 1542 #define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499 1543 1544 #define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a 1545 1546 #define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b 1547 1548 #define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c 1549 1550 #define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d 1551 1552 #define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e 1553 1554 #define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f 1555 1556 #define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0 1557 1558 #define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1 1559 1560 #define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2 1561 1562 #define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3 1563 1564 #define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4 1565 1566 #define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5 1567 1568 #define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6 1569 1570 #define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7 1571 1572 #define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8 1573 1574 #define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9 1575 1576 #define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa 1577 1578 #define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab 1579 1580 #define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac 1581 1582 #define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad 1583 1584 #define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae 1585 1586 #define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af 1587 1588 #define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0 1589 1590 #define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1 1591 1592 #define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2 1593 1594 #define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3 1595 1596 #define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4 1597 1598 #define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5 1599 1600 #define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6 1601 1602 #define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7 1603 1604 #define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8 1605 1606 #define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9 1607 1608 #define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba 1609 1610 #define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb 1611 1612 #define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc 1613 1614 #define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd 1615 1616 #define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be 1617 1618 #define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf 1619 1620 #define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0 1621 1622 #define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1 1623 1624 #define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2 1625 1626 #define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3 1627 1628 #define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4 1629 1630 #define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5 1631 1632 #define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6 1633 1634 #define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7 1635 1636 #define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8 1637 1638 #define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9 1639 1640 #define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca 1641 1642 #define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb 1643 1644 #define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc 1645 1646 #define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd 1647 1648 #define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce 1649 1650 #define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf 1651 1652 #define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0 1653 1654 #define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1 1655 1656 #define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2 1657 1658 #define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3 1659 1660 #define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4 1661 1662 #define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5 1663 1664 #define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6 1665 1666 #define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7 1667 1668 #define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8 1669 1670 #define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9 1671 1672 #define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da 1673 1674 #define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db 1675 1676 #define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc 1677 1678 #define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd 1679 1680 #define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de 1681 1682 #define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df 1683 1684 #define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0 1685 1686 #define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1 1687 1688 #define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2 1689 1690 #define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3 1691 1692 #define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4 1693 1694 #define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5 1695 1696 #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6 1697 1698 #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7 1699 1700 #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8 1701 1702 #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9 1703 1704 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea 1705 1706 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb 1707 1708 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec 1709 1710 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed 1711 1712 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee 1713 1714 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef 1715 1716 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0 1717 1718 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1 1719 1720 #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2 1721 1722 #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3 1723 1724 #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4 1725 1726 #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5 1727 1728 #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6 1729 1730 #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7 1731 1732 #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8 1733 1734 #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9 1735 1736 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 1737 1738 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 1739 1740 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 1741 1742 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 1743 1744 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 1745 1746 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 1747 1748 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 1749 1750 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507 1751 1752 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508 1753 1754 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509 1755 1756 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a 1757 1758 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 1759 1760 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 1761 1762 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 1763 1764 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 1765 1766 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 1767 1768 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 1769 1770 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 1771 1772 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 1773 1774 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 1775 1776 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 1777 1778 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 1779 1780 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 1781 1782 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 1783 1784 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 1785 1786 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 1787 1788 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1789 1790 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 1791 1792 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 1793 1794 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 1795 1796 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 1797 1798 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 1799 1800 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 1801 1802 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 1803 1804 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 1805 1806 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 1807 1808 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 1809 1810 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 1811 1812 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 1813 1814 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 1815 1816 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 1817 1818 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 1819 1820 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 1821 1822 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 1823 1824 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 1825 1826 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 1827 1828 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 1829 1830 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 1831 1832 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 1833 1834 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 1835 1836 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 1837 1838 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 1839 1840 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 1841 1842 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 1843 1844 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 1845 1846 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 1847 1848 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 1849 1850 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 1851 1852 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 1853 1854 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 1855 1856 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 1857 1858 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 1859 1860 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 1861 1862 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 1863 1864 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 1865 1866 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 1867 1868 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 1869 1870 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 1871 1872 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 1873 1874 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 1875 1876 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 1877 1878 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 1879 1880 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 1881 1882 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 1883 1884 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 1885 1886 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 1887 1888 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 1889 1890 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 1891 1892 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 1893 1894 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 1895 1896 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 1897 1898 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 1899 1900 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 1901 1902 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 1903 1904 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 1905 1906 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 1907 1908 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 1909 1910 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 1911 1912 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 1913 1914 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 1915 1916 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 1917 1918 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 1919 1920 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 1921 1922 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 1923 1924 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 1925 1926 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 1927 1928 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 1929 1930 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 1931 1932 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 1933 1934 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 1935 1936 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 1937 1938 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 1939 1940 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 1941 1942 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 1943 1944 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 1945 1946 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 1947 1948 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 1949 1950 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 1951 1952 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 1953 1954 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 1955 1956 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 1957 1958 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 1959 1960 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 1961 1962 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 1963 1964 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 1965 1966 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 1967 1968 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 1969 1970 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 1971 1972 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 1973 1974 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 1975 1976 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 1977 1978 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 1979 1980 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 1981 1982 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 1983 1984 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 1985 1986 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 1987 1988 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 1989 1990 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 1991 1992 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 1993 1994 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 1995 1996 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 1997 1998 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 1999 2000 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 2001 2002 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 2003 2004 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 2005 2006 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 2007 2008 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 2009 2010 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 2011 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 2012 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 2013 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 2014 { 2015 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 2016 } 2017 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 2018 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 2019 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 2020 { 2021 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 2022 } 2023 2024 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 2025 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 2026 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 2027 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 2028 { 2029 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 2030 } 2031 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 2032 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 2033 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 2034 { 2035 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 2036 } 2037 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 2038 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 2039 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 2040 { 2041 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 2042 } 2043 2044 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 2045 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 2046 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 2047 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 2048 { 2049 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 2050 } 2051 2052 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 2053 2054 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 2055 2056 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 2057 2058 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 2059 2060 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 2061 2062 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 2063 2064 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 2065 2066 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 2067 2068 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 2069 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 2070 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 2071 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 2072 { 2073 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 2074 } 2075 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 2076 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 2077 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 2078 { 2079 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 2080 } 2081 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 2082 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 2083 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 2084 { 2085 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 2086 } 2087 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 2088 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 2089 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 2090 { 2091 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 2092 } 2093 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 2094 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 2095 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 2096 { 2097 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 2098 } 2099 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 2100 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 2101 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 2102 { 2103 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 2104 } 2105 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 2106 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 2107 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 2108 { 2109 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 2110 } 2111 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 2112 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 2113 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 2114 { 2115 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 2116 } 2117 2118 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 2119 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 2120 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 2121 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 2122 { 2123 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 2124 } 2125 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 2126 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 2127 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 2128 { 2129 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 2130 } 2131 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 2132 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 2133 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 2134 { 2135 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 2136 } 2137 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 2138 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 2139 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 2140 { 2141 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 2142 } 2143 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 2144 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 2145 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 2146 { 2147 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 2148 } 2149 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 2150 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 2151 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 2152 { 2153 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 2154 } 2155 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 2156 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 2157 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 2158 { 2159 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 2160 } 2161 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 2162 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 2163 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 2164 { 2165 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 2166 } 2167 2168 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 2169 2170 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 2171 2172 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8 2173 2174 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9 2175 2176 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 2177 2178 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610 2179 2180 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611 2181 2182 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612 2183 2184 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613 2185 2186 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614 2187 2188 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615 2189 2190 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616 2191 2192 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617 2193 2194 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618 2195 2196 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619 2197 2198 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a 2199 2200 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b 2201 2202 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 2203 2204 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 2205 2206 #define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10 2207 2208 #define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11 2209 2210 #define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12 2211 2212 #define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13 2213 2214 #define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14 2215 2216 #define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15 2217 2218 #define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16 2219 2220 #define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17 2221 2222 #define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18 2223 2224 #define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19 2225 2226 #define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a 2227 2228 #define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b 2229 2230 #define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c 2231 2232 #define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c 2233 2234 #define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d 2235 2236 #define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e 2237 2238 #define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f 2239 2240 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 2241 2242 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 2243 2244 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 2245 2246 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 2247 2248 #define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34 2249 2250 #define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35 2251 2252 #define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36 2253 2254 #define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37 2255 2256 #define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38 2257 2258 #define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39 2259 2260 #define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a 2261 2262 #define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b 2263 2264 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 2265 2266 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10 2267 2268 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11 2269 2270 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12 2271 2272 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13 2273 2274 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14 2275 2276 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15 2277 2278 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 2279 2280 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 2281 2282 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 2283 2284 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610 2285 2286 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611 2287 2288 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612 2289 2290 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613 2291 2292 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614 2293 2294 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615 2295 2296 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616 2297 2298 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617 2299 2300 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 2301 2302 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604 2303 2304 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605 2305 2306 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606 2307 2308 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607 2309 2310 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608 2311 2312 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609 2313 2314 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 2315 2316 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 2317 2318 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 2319 2320 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 2321 2322 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 2323 2324 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 2325 2326 #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 2327 2328 #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 2329 2330 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 2331 2332 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 2333 2334 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 2335 2336 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 2337 2338 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 2339 2340 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 2341 2342 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 2343 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 2344 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 2345 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 2346 { 2347 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 2348 } 2349 2350 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c 2351 2352 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d 2353 2354 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e 2355 2356 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f 2357 2358 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20 2359 2360 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21 2361 2362 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22 2363 2364 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23 2365 2366 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24 2367 2368 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25 2369 2370 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26 2371 2372 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27 2373 2374 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 2375 2376 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 2377 2378 #define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10 2379 2380 #define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11 2381 2382 #define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12 2383 2384 #define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13 2385 2386 #define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14 2387 2388 #define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15 2389 2390 #define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16 2391 2392 #define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17 2393 2394 #define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18 2395 2396 #define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19 2397 2398 #define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a 2399 2400 #define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b 2401 2402 #define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c 2403 2404 #define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d 2405 2406 #define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e 2407 2408 #define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f 2409 2410 #define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20 2411 2412 #define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21 2413 2414 #define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22 2415 2416 #define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23 2417 2418 #define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24 2419 2420 #define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25 2421 2422 #define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26 2423 2424 #define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27 2425 2426 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 2427 2428 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 2429 2430 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610 2431 2432 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611 2433 2434 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612 2435 2436 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613 2437 2438 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614 2439 2440 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615 2441 2442 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616 2443 2444 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617 2445 2446 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618 2447 2448 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619 2449 2450 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a 2451 2452 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b 2453 2454 #define REG_A6XX_VBIF_VERSION 0x00003000 2455 2456 #define REG_A6XX_VBIF_CLKON 0x00003001 2457 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 2458 2459 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2460 2461 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 2462 2463 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 2464 2465 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2466 2467 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2468 2469 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2470 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 2471 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 2472 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 2473 { 2474 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 2475 } 2476 2477 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2478 2479 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2480 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 2481 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 2482 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 2483 { 2484 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 2485 } 2486 2487 #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 2488 2489 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 2490 2491 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 2492 2493 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 2494 2495 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 2496 2497 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 2498 2499 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 2500 2501 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 2502 2503 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 2504 2505 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 2506 2507 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 2508 2509 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 2510 2511 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 2512 2513 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 2514 2515 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 2516 2517 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 2518 2519 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 2520 2521 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 2522 2523 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 2524 2525 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 2526 2527 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 2528 2529 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 2530 2531 #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 2532 #define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000 2533 #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff 2534 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 2535 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 2536 { 2537 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 2538 } 2539 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x7fff0000 2540 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 2541 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 2542 { 2543 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 2544 } 2545 2546 #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 2547 #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 2548 #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff 2549 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 2550 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 2551 { 2552 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 2553 } 2554 #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000 2555 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 2556 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 2557 { 2558 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 2559 } 2560 2561 #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 2562 #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 2563 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff 2564 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 2565 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 2566 { 2567 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 2568 } 2569 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000 2570 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 2571 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 2572 { 2573 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 2574 } 2575 2576 #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2577 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x000000ff 2578 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2579 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2580 { 2581 assert(!(val & 0x1f)); 2582 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2583 } 2584 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x0001ff00 2585 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2586 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2587 { 2588 assert(!(val & 0xf)); 2589 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2590 } 2591 #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000 2592 #define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000 2593 2594 #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 2595 #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x000000ff 2596 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 2597 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 2598 { 2599 assert(!(val & 0x1f)); 2600 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 2601 } 2602 #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x0001ff00 2603 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 2604 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 2605 { 2606 assert(!(val & 0xf)); 2607 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 2608 } 2609 2610 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 2611 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 2612 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2613 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2614 { 2615 assert(!(val & 0x1f)); 2616 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 2617 } 2618 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 2619 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 2620 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2621 { 2622 assert(!(val & 0xf)); 2623 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 2624 } 2625 2626 #define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03 2627 2628 #define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04 2629 2630 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 2631 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 2632 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 2633 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 2634 { 2635 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 2636 } 2637 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 2638 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 2639 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 2640 { 2641 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 2642 } 2643 2644 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2645 2646 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2647 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2648 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2649 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2650 { 2651 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 2652 } 2653 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2654 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2655 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2656 { 2657 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2658 } 2659 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 2660 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2661 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2662 { 2663 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 2664 } 2665 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 2666 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 2667 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2668 { 2669 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 2670 } 2671 2672 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO 0x00000c30 2673 2674 #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI 0x00000c31 2675 2676 #define REG_A6XX_VSC_PIPE_DATA2_PITCH 0x00000c32 2677 2678 #define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH 0x00000c33 2679 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK 0xffffffff 2680 #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT 0 2681 static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val) 2682 { 2683 assert(!(val & 0xf)); 2684 return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK; 2685 } 2686 2687 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34 2688 2689 #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35 2690 2691 #define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36 2692 2693 #define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH 0x00000c37 2694 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK 0xffffffff 2695 #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT 0 2696 static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val) 2697 { 2698 assert(!(val & 0xf)); 2699 return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK; 2700 } 2701 2702 static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2703 2704 static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2705 2706 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 2707 2708 #define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000 2709 2710 #define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001 2711 2712 #define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004 2713 2714 #define REG_A6XX_GRAS_CNTL 0x00008005 2715 #define A6XX_GRAS_CNTL_VARYING 0x00000001 2716 #define A6XX_GRAS_CNTL_CENTROID 0x00000002 2717 #define A6XX_GRAS_CNTL_PERSAMP_VARYING 0x00000004 2718 #define A6XX_GRAS_CNTL_SIZE 0x00000008 2719 #define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020 2720 #define A6XX_GRAS_CNTL_XCOORD 0x00000040 2721 #define A6XX_GRAS_CNTL_YCOORD 0x00000080 2722 #define A6XX_GRAS_CNTL_ZCOORD 0x00000100 2723 #define A6XX_GRAS_CNTL_WCOORD 0x00000200 2724 2725 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2726 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff 2727 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 2728 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 2729 { 2730 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 2731 } 2732 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 2733 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 2734 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 2735 { 2736 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 2737 } 2738 2739 #define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0 0x00008010 2740 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 2741 #define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 2742 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val) 2743 { 2744 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 2745 } 2746 2747 #define REG_A6XX_GRAS_CL_VPORT_XSCALE_0 0x00008011 2748 #define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 2749 #define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 2750 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val) 2751 { 2752 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK; 2753 } 2754 2755 #define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0 0x00008012 2756 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 2757 #define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 2758 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val) 2759 { 2760 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 2761 } 2762 2763 #define REG_A6XX_GRAS_CL_VPORT_YSCALE_0 0x00008013 2764 #define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 2765 #define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 2766 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val) 2767 { 2768 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK; 2769 } 2770 2771 #define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0 0x00008014 2772 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 2773 #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 2774 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 2775 { 2776 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 2777 } 2778 2779 #define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0 0x00008015 2780 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 2781 #define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 2782 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val) 2783 { 2784 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 2785 } 2786 2787 #define REG_A6XX_GRAS_SU_CNTL 0x00008090 2788 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 2789 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 2790 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 2791 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 2792 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 2793 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 2794 { 2795 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 2796 } 2797 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2798 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 2799 2800 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 2801 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2802 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2803 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2804 { 2805 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2806 } 2807 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2808 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2809 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2810 { 2811 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2812 } 2813 2814 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2815 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2816 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 2817 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 2818 { 2819 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 2820 } 2821 2822 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2823 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 2824 2825 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 2826 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2827 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2828 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2829 { 2830 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2831 } 2832 2833 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 2834 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2835 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2836 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2837 { 2838 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2839 } 2840 2841 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 2842 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 2843 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 2844 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 2845 { 2846 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 2847 } 2848 2849 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 2850 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2851 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2852 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 2853 { 2854 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2855 } 2856 2857 #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099 2858 2859 #define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b 2860 2861 #define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0 2862 2863 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 2864 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2865 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2866 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2867 { 2868 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 2869 } 2870 2871 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 2872 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2873 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2874 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2875 { 2876 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 2877 } 2878 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2879 2880 #define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4 2881 2882 #define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5 2883 2884 #define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6 2885 2886 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 2887 2888 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x000080b0 2889 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2890 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff 2891 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 2892 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) 2893 { 2894 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; 2895 } 2896 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 2897 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 2898 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) 2899 { 2900 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; 2901 } 2902 2903 #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x000080b1 2904 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2905 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff 2906 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 2907 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) 2908 { 2909 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; 2910 } 2911 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 2912 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 2913 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) 2914 { 2915 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; 2916 } 2917 2918 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x000080d0 2919 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2920 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff 2921 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 2922 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) 2923 { 2924 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; 2925 } 2926 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 2927 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 2928 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) 2929 { 2930 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; 2931 } 2932 2933 #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x000080d1 2934 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2935 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff 2936 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 2937 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) 2938 { 2939 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; 2940 } 2941 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 2942 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 2943 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) 2944 { 2945 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; 2946 } 2947 2948 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 2949 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2950 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 2951 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2952 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2953 { 2954 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2955 } 2956 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 2957 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2958 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2959 { 2960 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2961 } 2962 2963 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 2964 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2965 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 2966 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2967 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2968 { 2969 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2970 } 2971 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 2972 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2973 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2974 { 2975 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2976 } 2977 2978 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 2979 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 2980 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 2981 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2982 #define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008 2983 #define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010 2984 2985 #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101 2986 2987 #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102 2988 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff 2989 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0 2990 static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 2991 { 2992 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; 2993 } 2994 2995 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103 2996 2997 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104 2998 2999 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 3000 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff 3001 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 3002 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 3003 { 3004 assert(!(val & 0x1f)); 3005 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 3006 } 3007 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 3008 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3009 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3010 { 3011 assert(!(val & 0x1f)); 3012 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 3013 } 3014 3015 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106 3016 3017 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107 3018 3019 #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 3020 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3021 3022 #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 3023 3024 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 3025 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000003 3026 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 3027 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(uint32_t val) 3028 { 3029 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 3030 } 3031 #define A6XX_GRAS_2D_BLIT_CNTL_HORIZONTAL_FLIP 0x00000004 3032 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000010 3033 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 3034 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3035 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) 3036 { 3037 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 3038 } 3039 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 3040 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 3041 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 3042 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 3043 { 3044 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 3045 } 3046 3047 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 3048 #define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0xffffff00 3049 #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8 3050 static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(int32_t val) 3051 { 3052 return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK; 3053 } 3054 3055 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 3056 #define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0xffffff00 3057 #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8 3058 static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(int32_t val) 3059 { 3060 return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK; 3061 } 3062 3063 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 3064 #define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0xffffff00 3065 #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8 3066 static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(int32_t val) 3067 { 3068 return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK; 3069 } 3070 3071 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 3072 #define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0xffffff00 3073 #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8 3074 static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(int32_t val) 3075 { 3076 return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK; 3077 } 3078 3079 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 3080 #define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE 0x80000000 3081 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00007fff 3082 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 3083 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 3084 { 3085 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 3086 } 3087 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x7fff0000 3088 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 3089 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 3090 { 3091 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 3092 } 3093 3094 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 3095 #define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE 0x80000000 3096 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00007fff 3097 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 3098 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 3099 { 3100 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 3101 } 3102 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x7fff0000 3103 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 3104 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 3105 { 3106 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 3107 } 3108 3109 #define REG_A6XX_GRAS_RESOLVE_CNTL_1 0x0000840a 3110 #define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 3111 #define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK 0x00007fff 3112 #define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT 0 3113 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val) 3114 { 3115 return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK; 3116 } 3117 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 3118 #define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT 16 3119 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val) 3120 { 3121 return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK; 3122 } 3123 3124 #define REG_A6XX_GRAS_RESOLVE_CNTL_2 0x0000840b 3125 #define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 3126 #define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK 0x00007fff 3127 #define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT 0 3128 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val) 3129 { 3130 return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK; 3131 } 3132 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 3133 #define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT 16 3134 static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val) 3135 { 3136 return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK; 3137 } 3138 3139 #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600 3140 3141 #define REG_A6XX_RB_BIN_CONTROL 0x00008800 3142 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x000000ff 3143 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 3144 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 3145 { 3146 assert(!(val & 0x1f)); 3147 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 3148 } 3149 #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x0001ff00 3150 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 3151 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 3152 { 3153 assert(!(val & 0xf)); 3154 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 3155 } 3156 #define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000 3157 #define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000 3158 3159 #define REG_A6XX_RB_RENDER_CNTL 0x00008801 3160 #define A6XX_RB_RENDER_CNTL_UNK4 0x00000010 3161 #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 3162 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 3163 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 3164 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 3165 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 3166 { 3167 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 3168 } 3169 3170 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 3171 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 3172 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 3173 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3174 { 3175 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 3176 } 3177 3178 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 3179 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 3180 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 3181 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3182 { 3183 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 3184 } 3185 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 3186 3187 #define REG_A6XX_RB_UNKNOWN_8804 0x00008804 3188 3189 #define REG_A6XX_RB_UNKNOWN_8805 0x00008805 3190 3191 #define REG_A6XX_RB_UNKNOWN_8806 0x00008806 3192 3193 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 3194 #define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001 3195 #define A6XX_RB_RENDER_CONTROL0_CENTROID 0x00000002 3196 #define A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING 0x00000004 3197 #define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008 3198 #define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020 3199 #define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 3200 #define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 3201 #define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 3202 #define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 3203 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 3204 3205 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 3206 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3207 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 3208 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 3209 #define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010 3210 #define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020 3211 #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040 3212 3213 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 3214 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 3215 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 3216 3217 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 3218 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 3219 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 3220 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 3221 { 3222 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 3223 } 3224 3225 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 3226 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 3227 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 3228 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 3229 { 3230 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 3231 } 3232 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 3233 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 3234 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 3235 { 3236 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 3237 } 3238 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 3239 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 3240 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 3241 { 3242 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 3243 } 3244 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 3245 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 3246 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 3247 { 3248 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 3249 } 3250 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 3251 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 3252 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 3253 { 3254 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 3255 } 3256 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 3257 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 3258 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 3259 { 3260 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 3261 } 3262 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 3263 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 3264 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 3265 { 3266 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 3267 } 3268 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 3269 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 3270 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 3271 { 3272 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 3273 } 3274 3275 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 3276 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 3277 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 3278 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 3279 { 3280 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 3281 } 3282 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 3283 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 3284 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 3285 { 3286 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 3287 } 3288 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 3289 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 3290 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 3291 { 3292 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 3293 } 3294 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 3295 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 3296 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 3297 { 3298 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 3299 } 3300 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 3301 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 3302 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 3303 { 3304 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 3305 } 3306 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 3307 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 3308 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 3309 { 3310 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 3311 } 3312 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 3313 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 3314 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 3315 { 3316 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 3317 } 3318 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 3319 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 3320 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 3321 { 3322 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 3323 } 3324 3325 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 3326 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 3327 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 3328 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 3329 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 3330 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 3331 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 3332 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 3333 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 3334 3335 #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3336 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3337 3338 #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3339 3340 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 3341 3342 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 3343 3344 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 3345 3346 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 3347 3348 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 3349 3350 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 3351 3352 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 3353 3354 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 3355 3356 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 3357 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 3358 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 3359 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 3360 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 3361 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 3362 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 3363 { 3364 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 3365 } 3366 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 3367 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 3368 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 3369 { 3370 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 3371 } 3372 3373 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 3374 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 3375 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 3376 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 3377 { 3378 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 3379 } 3380 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 3381 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 3382 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3383 { 3384 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 3385 } 3386 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 3387 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 3388 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 3389 { 3390 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 3391 } 3392 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 3393 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 3394 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 3395 { 3396 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 3397 } 3398 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 3399 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 3400 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3401 { 3402 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 3403 } 3404 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 3405 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 3406 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 3407 { 3408 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 3409 } 3410 3411 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 3412 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 3413 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3414 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 3415 { 3416 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 3417 } 3418 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 3419 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 3420 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 3421 { 3422 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 3423 } 3424 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 3425 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 3426 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3427 { 3428 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 3429 } 3430 3431 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3432 #define A6XX_RB_MRT_PITCH__MASK 0xffffffff 3433 #define A6XX_RB_MRT_PITCH__SHIFT 0 3434 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 3435 { 3436 assert(!(val & 0x3f)); 3437 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 3438 } 3439 3440 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3441 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff 3442 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 3443 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 3444 { 3445 assert(!(val & 0x3f)); 3446 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 3447 } 3448 3449 static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3450 3451 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } 3452 3453 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3454 3455 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 3456 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 3457 #define A6XX_RB_BLEND_RED_F32__SHIFT 0 3458 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 3459 { 3460 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 3461 } 3462 3463 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 3464 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 3465 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 3466 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 3467 { 3468 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 3469 } 3470 3471 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 3472 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 3473 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 3474 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 3475 { 3476 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 3477 } 3478 3479 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 3480 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 3481 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 3482 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 3483 { 3484 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 3485 } 3486 3487 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 3488 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 3489 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 3490 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 3491 { 3492 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 3493 } 3494 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 3495 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 3496 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 3497 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 3498 { 3499 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 3500 } 3501 3502 #define REG_A6XX_RB_BLEND_CNTL 0x00008865 3503 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 3504 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 3505 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 3506 { 3507 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 3508 } 3509 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3510 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3511 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 3512 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 3513 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 3514 { 3515 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 3516 } 3517 3518 #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3519 #define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 3520 3521 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 3522 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 3523 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 3524 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 3525 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 3526 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 3527 { 3528 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 3529 } 3530 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 3531 3532 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 3533 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 3534 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 3535 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 3536 { 3537 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 3538 } 3539 3540 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 3541 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff 3542 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 3543 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 3544 { 3545 assert(!(val & 0x3f)); 3546 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 3547 } 3548 3549 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 3550 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3551 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 3552 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 3553 { 3554 assert(!(val & 0x3f)); 3555 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 3556 } 3557 3558 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875 3559 3560 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876 3561 3562 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 3563 3564 #define REG_A6XX_RB_UNKNOWN_8878 0x00008878 3565 3566 #define REG_A6XX_RB_UNKNOWN_8879 0x00008879 3567 3568 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 3569 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 3570 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 3571 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 3572 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 3573 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 3574 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 3575 { 3576 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 3577 } 3578 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 3579 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 3580 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 3581 { 3582 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 3583 } 3584 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 3585 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 3586 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 3587 { 3588 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 3589 } 3590 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 3591 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 3592 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 3593 { 3594 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 3595 } 3596 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 3597 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 3598 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 3599 { 3600 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 3601 } 3602 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 3603 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 3604 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 3605 { 3606 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 3607 } 3608 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 3609 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 3610 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 3611 { 3612 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 3613 } 3614 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 3615 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 3616 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 3617 { 3618 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 3619 } 3620 3621 #define REG_A6XX_RB_STENCIL_INFO 0x00008881 3622 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3623 3624 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 3625 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0xffffffff 3626 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 3627 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 3628 { 3629 assert(!(val & 0x3f)); 3630 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 3631 } 3632 3633 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 3634 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3635 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 3636 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 3637 { 3638 assert(!(val & 0x3f)); 3639 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 3640 } 3641 3642 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884 3643 3644 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885 3645 3646 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 3647 3648 #define REG_A6XX_RB_STENCILREF 0x00008887 3649 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 3650 #define A6XX_RB_STENCILREF_REF__SHIFT 0 3651 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 3652 { 3653 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 3654 } 3655 #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3656 #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3657 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3658 { 3659 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3660 } 3661 3662 #define REG_A6XX_RB_STENCILMASK 0x00008888 3663 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 3664 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 3665 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 3666 { 3667 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 3668 } 3669 #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3670 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3671 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3672 { 3673 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3674 } 3675 3676 #define REG_A6XX_RB_STENCILWRMASK 0x00008889 3677 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 3678 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 3679 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 3680 { 3681 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 3682 } 3683 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3684 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3685 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3686 { 3687 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3688 } 3689 3690 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 3691 #define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 3692 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff 3693 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 3694 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 3695 { 3696 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 3697 } 3698 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 3699 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 3700 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 3701 { 3702 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 3703 } 3704 3705 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 3706 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 3707 3708 #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3709 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3710 3711 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 3712 3713 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 3714 #define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3715 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00007fff 3716 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 3717 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 3718 { 3719 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 3720 } 3721 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x7fff0000 3722 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 3723 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 3724 { 3725 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 3726 } 3727 3728 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 3729 #define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3730 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00007fff 3731 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 3732 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 3733 { 3734 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 3735 } 3736 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x7fff0000 3737 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 3738 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 3739 { 3740 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 3741 } 3742 3743 #define REG_A6XX_RB_MSAA_CNTL 0x000088d5 3744 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 3745 #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 3746 static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3747 { 3748 return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; 3749 } 3750 3751 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 3752 3753 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 3754 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 3755 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 3756 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 3757 { 3758 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 3759 } 3760 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 3761 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 3762 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 3763 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 3764 { 3765 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 3766 } 3767 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 3768 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 3769 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 3770 { 3771 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 3772 } 3773 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 3774 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 3775 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3776 { 3777 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 3778 } 3779 3780 #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8 3781 3782 #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9 3783 3784 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 3785 #define A6XX_RB_BLIT_DST_PITCH__MASK 0xffffffff 3786 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 3787 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 3788 { 3789 assert(!(val & 0x3f)); 3790 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 3791 } 3792 3793 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 3794 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff 3795 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 3796 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 3797 { 3798 assert(!(val & 0x3f)); 3799 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 3800 } 3801 3802 #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc 3803 3804 #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd 3805 3806 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 3807 3808 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 3809 3810 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 3811 3812 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 3813 3814 #define REG_A6XX_RB_BLIT_INFO 0x000088e3 3815 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 3816 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 3817 #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004 3818 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 3819 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 3820 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 3821 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 3822 { 3823 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 3824 } 3825 3826 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 3827 3828 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900 3829 3830 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901 3831 3832 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 3833 3834 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 3835 3836 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } 3837 3838 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } 3839 3840 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 3841 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 3842 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3843 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3844 { 3845 assert(!(val & 0x3f)); 3846 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 3847 } 3848 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 3849 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3850 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3851 { 3852 assert(!(val & 0x7f)); 3853 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3854 } 3855 3856 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927 3857 3858 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928 3859 3860 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 3861 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000003 3862 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 3863 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(uint32_t val) 3864 { 3865 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 3866 } 3867 #define A6XX_RB_2D_BLIT_CNTL_HORIZONTAL_FLIP 0x00000004 3868 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000010 3869 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 3870 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3871 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) 3872 { 3873 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 3874 } 3875 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 3876 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 3877 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 3878 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 3879 { 3880 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 3881 } 3882 3883 #define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01 3884 3885 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 3886 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 3887 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 3888 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 3889 { 3890 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 3891 } 3892 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 3893 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 3894 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 3895 { 3896 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 3897 } 3898 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 3899 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 3900 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3901 { 3902 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 3903 } 3904 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 3905 3906 #define REG_A6XX_RB_2D_DST_LO 0x00008c18 3907 3908 #define REG_A6XX_RB_2D_DST_HI 0x00008c19 3909 3910 #define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a 3911 #define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff 3912 #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 3913 static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val) 3914 { 3915 assert(!(val & 0x3f)); 3916 return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK; 3917 } 3918 3919 #define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20 3920 3921 #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21 3922 3923 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 3924 3925 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 3926 3927 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 3928 3929 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 3930 3931 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 3932 3933 #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 3934 3935 #define REG_A6XX_RB_CCU_CNTL 0x00008e07 3936 3937 #define REG_A6XX_VPC_UNKNOWN_9101 0x00009101 3938 3939 #define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104 3940 3941 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 3942 3943 #define REG_A6XX_VPC_UNKNOWN_9108 0x00009108 3944 3945 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 3946 3947 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 3948 3949 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 3950 3951 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 3952 3953 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 3954 3955 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 3956 3957 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 3958 3959 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 3960 3961 #define REG_A6XX_VPC_SO_CNTL 0x00009216 3962 #define A6XX_VPC_SO_CNTL_ENABLE 0x00010000 3963 3964 #define REG_A6XX_VPC_SO_PROG 0x00009217 3965 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 3966 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 3967 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 3968 { 3969 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 3970 } 3971 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 3972 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 3973 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 3974 { 3975 assert(!(val & 0x3)); 3976 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 3977 } 3978 #define A6XX_VPC_SO_PROG_A_EN 0x00000800 3979 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 3980 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 3981 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 3982 { 3983 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 3984 } 3985 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 3986 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 3987 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 3988 { 3989 assert(!(val & 0x3)); 3990 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 3991 } 3992 #define A6XX_VPC_SO_PROG_B_EN 0x00800000 3993 3994 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 3995 3996 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 3997 3998 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } 3999 4000 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4001 4002 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 4003 4004 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4005 4006 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } 4007 4008 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } 4009 4010 #define REG_A6XX_VPC_UNKNOWN_9236 0x00009236 4011 #define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK 0x00000001 4012 #define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT 0 4013 static inline uint32_t A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(uint32_t val) 4014 { 4015 return ((val) << A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT) & A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK; 4016 } 4017 4018 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 4019 4020 #define REG_A6XX_VPC_PACK 0x00009301 4021 #define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4022 #define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT 0 4023 static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val) 4024 { 4025 return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK; 4026 } 4027 #define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00 4028 #define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8 4029 static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) 4030 { 4031 return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK; 4032 } 4033 #define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000 4034 #define A6XX_VPC_PACK_PSIZELOC__SHIFT 16 4035 static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val) 4036 { 4037 return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK; 4038 } 4039 4040 #define REG_A6XX_VPC_CNTL_0 0x00009304 4041 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 4042 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 4043 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 4044 { 4045 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 4046 } 4047 #define A6XX_VPC_CNTL_0_VARYING 0x00010000 4048 4049 #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305 4050 #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 4051 #define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 4052 #define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 4053 #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 4054 #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 4055 4056 #define REG_A6XX_VPC_SO_OVERRIDE 0x00009306 4057 #define A6XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001 4058 4059 #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 4060 4061 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 4062 4063 #define REG_A6XX_PC_UNKNOWN_9801 0x00009801 4064 4065 #define REG_A6XX_PC_RESTART_INDEX 0x00009803 4066 4067 #define REG_A6XX_PC_MODE_CNTL 0x00009804 4068 4069 #define REG_A6XX_PC_UNKNOWN_9805 0x00009805 4070 4071 #define REG_A6XX_PC_UNKNOWN_9806 0x00009806 4072 4073 #define REG_A6XX_PC_UNKNOWN_9980 0x00009980 4074 4075 #define REG_A6XX_PC_UNKNOWN_9981 0x00009981 4076 4077 #define REG_A6XX_PC_UNKNOWN_9990 0x00009990 4078 4079 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 4080 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 4081 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 4082 4083 #define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01 4084 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f 4085 #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0 4086 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val) 4087 { 4088 return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK; 4089 } 4090 #define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100 4091 4092 #define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06 4093 4094 #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07 4095 4096 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08 4097 4098 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09 4099 4100 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 4101 4102 #define REG_A6XX_VFD_CONTROL_0 0x0000a000 4103 #define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f 4104 #define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 4105 static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val) 4106 { 4107 return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK; 4108 } 4109 4110 #define REG_A6XX_VFD_CONTROL_1 0x0000a001 4111 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 4112 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 4113 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 4114 { 4115 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 4116 } 4117 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 4118 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 4119 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 4120 { 4121 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 4122 } 4123 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 4124 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 4125 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 4126 { 4127 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 4128 } 4129 4130 #define REG_A6XX_VFD_CONTROL_2 0x0000a002 4131 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff 4132 #define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0 4133 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) 4134 { 4135 return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK; 4136 } 4137 4138 #define REG_A6XX_VFD_CONTROL_3 0x0000a003 4139 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00 4140 #define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8 4141 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) 4142 { 4143 return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK; 4144 } 4145 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 4146 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 4147 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 4148 { 4149 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 4150 } 4151 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 4152 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 4153 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 4154 { 4155 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 4156 } 4157 4158 #define REG_A6XX_VFD_CONTROL_4 0x0000a004 4159 4160 #define REG_A6XX_VFD_CONTROL_5 0x0000a005 4161 4162 #define REG_A6XX_VFD_CONTROL_6 0x0000a006 4163 4164 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 4165 #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001 4166 4167 #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008 4168 4169 #define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009 4170 4171 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 4172 4173 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 4174 4175 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 4176 4177 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 4178 4179 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } 4180 4181 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 4182 4183 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 4184 4185 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 4186 4187 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 4188 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 4189 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 4190 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 4191 { 4192 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 4193 } 4194 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 4195 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 4196 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 4197 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val) 4198 { 4199 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 4200 } 4201 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 4202 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 4203 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 4204 { 4205 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 4206 } 4207 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 4208 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 4209 4210 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 4211 4212 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 4213 4214 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 4215 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 4216 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 4217 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 4218 { 4219 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 4220 } 4221 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 4222 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 4223 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 4224 { 4225 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 4226 } 4227 4228 #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8 4229 4230 #define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802 4231 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f 4232 #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 4233 static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) 4234 { 4235 return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; 4236 } 4237 4238 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 4239 4240 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 4241 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 4242 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 4243 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 4244 { 4245 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 4246 } 4247 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 4248 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 4249 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 4250 { 4251 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 4252 } 4253 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 4254 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 4255 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 4256 { 4257 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 4258 } 4259 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 4260 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 4261 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 4262 { 4263 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 4264 } 4265 4266 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 4267 4268 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 4269 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 4270 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 4271 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 4272 { 4273 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 4274 } 4275 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 4276 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 4277 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 4278 { 4279 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 4280 } 4281 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 4282 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 4283 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 4284 { 4285 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 4286 } 4287 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 4288 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 4289 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 4290 { 4291 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 4292 } 4293 4294 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 4295 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 4296 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 4297 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4298 { 4299 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4300 } 4301 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 4302 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 4303 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4304 { 4305 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4306 } 4307 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 4308 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 4309 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4310 { 4311 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 4312 } 4313 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 4314 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 4315 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4316 { 4317 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 4318 } 4319 #define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000 4320 #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000 4321 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000 4322 4323 #define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b 4324 4325 #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c 4326 4327 #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d 4328 4329 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 4330 4331 #define REG_A6XX_SP_VS_CONFIG 0x0000a823 4332 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 4333 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 4334 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 4335 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 4336 { 4337 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 4338 } 4339 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 4340 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 4341 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 4342 { 4343 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 4344 } 4345 #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000 4346 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 4347 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 4348 { 4349 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 4350 } 4351 4352 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 4353 4354 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 4355 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 4356 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 4357 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4358 { 4359 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4360 } 4361 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 4362 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 4363 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4364 { 4365 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4366 } 4367 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 4368 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 4369 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4370 { 4371 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 4372 } 4373 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000 4374 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20 4375 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4376 { 4377 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; 4378 } 4379 #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000 4380 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000 4381 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000 4382 4383 #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831 4384 4385 #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834 4386 4387 #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835 4388 4389 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 4390 4391 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 4392 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 4393 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 4394 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 4395 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 4396 { 4397 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 4398 } 4399 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 4400 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 4401 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 4402 { 4403 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 4404 } 4405 #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000 4406 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 4407 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 4408 { 4409 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 4410 } 4411 4412 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 4413 4414 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 4415 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 4416 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 4417 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4418 { 4419 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4420 } 4421 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 4422 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 4423 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4424 { 4425 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4426 } 4427 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 4428 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 4429 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4430 { 4431 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 4432 } 4433 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000 4434 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20 4435 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4436 { 4437 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; 4438 } 4439 #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000 4440 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000 4441 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000 4442 4443 #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c 4444 4445 #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d 4446 4447 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 4448 4449 #define REG_A6XX_SP_DS_CONFIG 0x0000a863 4450 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 4451 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 4452 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 4453 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 4454 { 4455 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 4456 } 4457 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 4458 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 4459 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 4460 { 4461 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 4462 } 4463 #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000 4464 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 4465 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 4466 { 4467 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 4468 } 4469 4470 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 4471 4472 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 4473 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 4474 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 4475 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4476 { 4477 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4478 } 4479 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 4480 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 4481 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4482 { 4483 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4484 } 4485 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 4486 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 4487 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4488 { 4489 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 4490 } 4491 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000 4492 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20 4493 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4494 { 4495 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; 4496 } 4497 #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000 4498 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000 4499 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000 4500 4501 #define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871 4502 4503 #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d 4504 4505 #define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e 4506 4507 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 4508 4509 #define REG_A6XX_SP_GS_CONFIG 0x0000a894 4510 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 4511 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 4512 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 4513 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 4514 { 4515 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 4516 } 4517 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 4518 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 4519 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 4520 { 4521 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 4522 } 4523 #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000 4524 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 4525 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 4526 { 4527 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 4528 } 4529 4530 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 4531 4532 #define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0 4533 4534 #define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1 4535 4536 #define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2 4537 4538 #define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3 4539 4540 #define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4 4541 4542 #define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5 4543 4544 #define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6 4545 4546 #define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7 4547 4548 #define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8 4549 4550 #define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9 4551 4552 #define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa 4553 4554 #define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab 4555 4556 #define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac 4557 4558 #define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad 4559 4560 #define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae 4561 4562 #define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af 4563 4564 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 4565 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 4566 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 4567 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4568 { 4569 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4570 } 4571 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 4572 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 4573 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4574 { 4575 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4576 } 4577 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 4578 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 4579 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4580 { 4581 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 4582 } 4583 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 4584 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 4585 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4586 { 4587 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 4588 } 4589 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 4590 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 4591 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 4592 4593 #define REG_A6XX_SP_UNKNOWN_A982 0x0000a982 4594 4595 #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983 4596 4597 #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984 4598 4599 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 4600 #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001 4601 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 4602 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 4603 4604 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 4605 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 4606 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 4607 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 4608 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 4609 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 4610 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 4611 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 4612 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 4613 4614 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 4615 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 4616 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 4617 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 4618 { 4619 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 4620 } 4621 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 4622 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 4623 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 4624 { 4625 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 4626 } 4627 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 4628 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 4629 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 4630 { 4631 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 4632 } 4633 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 4634 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 4635 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 4636 { 4637 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 4638 } 4639 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 4640 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 4641 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 4642 { 4643 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 4644 } 4645 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 4646 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 4647 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 4648 { 4649 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 4650 } 4651 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 4652 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 4653 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 4654 { 4655 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 4656 } 4657 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 4658 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 4659 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 4660 { 4661 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 4662 } 4663 4664 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 4665 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 4666 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 4667 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 4668 { 4669 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 4670 } 4671 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 4672 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 4673 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 4674 { 4675 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 4676 } 4677 4678 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 4679 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 4680 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 4681 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 4682 { 4683 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 4684 } 4685 4686 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 4687 4688 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 4689 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 4690 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 4691 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val) 4692 { 4693 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 4694 } 4695 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 4696 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 4697 4698 #define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e 4699 4700 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 4701 4702 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 4703 4704 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 4705 4706 #define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3 4707 4708 #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 4709 4710 #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0 4711 4712 #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1 4713 4714 #define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2 4715 4716 #define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3 4717 4718 #define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4 4719 4720 #define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5 4721 4722 #define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6 4723 4724 #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7 4725 4726 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 4727 4728 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 4729 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 4730 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 4731 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 4732 { 4733 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 4734 } 4735 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 4736 4737 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 4738 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 4739 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 4740 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4741 { 4742 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4743 } 4744 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 4745 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 4746 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4747 { 4748 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4749 } 4750 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 4751 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 4752 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4753 { 4754 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 4755 } 4756 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 4757 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 4758 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4759 { 4760 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 4761 } 4762 #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000 4763 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000 4764 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 4765 4766 #define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4 4767 4768 #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5 4769 4770 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 4771 #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 4772 #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 4773 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 4774 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 4775 { 4776 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 4777 } 4778 #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 4779 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 4780 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 4781 { 4782 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 4783 } 4784 #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000 4785 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 4786 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 4787 { 4788 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 4789 } 4790 4791 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 4792 4793 #define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2 4794 4795 #define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3 4796 4797 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 4798 4799 #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00 4800 4801 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 4802 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 4803 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 4804 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 4805 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 4806 { 4807 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 4808 } 4809 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 4810 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 4811 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 4812 { 4813 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 4814 } 4815 #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000 4816 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 4817 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 4818 { 4819 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 4820 } 4821 4822 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 4823 4824 #define REG_A6XX_SP_IBO_LO 0x0000ab1a 4825 4826 #define REG_A6XX_SP_IBO_HI 0x0000ab1b 4827 4828 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 4829 4830 #define REG_A6XX_SP_2D_SRC_FORMAT 0x0000acc0 4831 #define A6XX_SP_2D_SRC_FORMAT_NORM 0x00000001 4832 #define A6XX_SP_2D_SRC_FORMAT_SINT 0x00000002 4833 #define A6XX_SP_2D_SRC_FORMAT_UINT 0x00000004 4834 #define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK 0x000007f8 4835 #define A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT 3 4836 static inline uint32_t A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(enum a6xx_color_fmt val) 4837 { 4838 return ((val) << A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT__MASK; 4839 } 4840 4841 #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 4842 4843 #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03 4844 4845 #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04 4846 4847 #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f 4848 4849 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 4850 4851 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 4852 4853 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 4854 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 4855 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 4856 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4857 { 4858 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 4859 } 4860 4861 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 4862 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 4863 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 4864 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4865 { 4866 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 4867 } 4868 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 4869 4870 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302 4871 4872 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303 4873 4874 #define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304 4875 4876 #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309 4877 4878 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 4879 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 4880 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 4881 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 4882 { 4883 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 4884 } 4885 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 4886 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 4887 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 4888 { 4889 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 4890 } 4891 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 4892 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 4893 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4894 { 4895 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 4896 } 4897 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 4898 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 4899 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 4900 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 4901 { 4902 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 4903 } 4904 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 4905 4906 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 4907 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 4908 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 4909 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 4910 { 4911 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 4912 } 4913 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 4914 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 4915 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 4916 { 4917 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 4918 } 4919 4920 #define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2 4921 4922 #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3 4923 4924 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 4925 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00 4926 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 4927 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 4928 { 4929 assert(!(val & 0x3f)); 4930 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 4931 } 4932 4933 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca 4934 4935 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb 4936 4937 #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600 4938 4939 #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605 4940 4941 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 4942 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 4943 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 4944 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 4945 { 4946 assert(!(val & 0x3)); 4947 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 4948 } 4949 #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 4950 4951 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 4952 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 4953 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 4954 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 4955 { 4956 assert(!(val & 0x3)); 4957 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 4958 } 4959 #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 4960 4961 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 4962 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 4963 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 4964 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 4965 { 4966 assert(!(val & 0x3)); 4967 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 4968 } 4969 #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 4970 4971 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 4972 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 4973 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 4974 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 4975 { 4976 assert(!(val & 0x3)); 4977 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 4978 } 4979 #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 4980 4981 #define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980 4982 4983 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 4984 4985 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 4986 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 4987 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 4988 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 4989 { 4990 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 4991 } 4992 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 4993 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 4994 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 4995 { 4996 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 4997 } 4998 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 4999 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 5000 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 5001 { 5002 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 5003 } 5004 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 5005 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 5006 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) 5007 { 5008 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK; 5009 } 5010 5011 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 5012 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK 0x000000ff 5013 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT 0 5014 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(uint32_t val) 5015 { 5016 return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK; 5017 } 5018 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK 0x00ff0000 5019 #define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT 16 5020 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(uint32_t val) 5021 { 5022 return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK; 5023 } 5024 5025 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 5026 #define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK 0x000000ff 5027 #define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT 0 5028 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(uint32_t val) 5029 { 5030 return ((val) << A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK; 5031 } 5032 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 5033 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 5034 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 5035 { 5036 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 5037 } 5038 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 5039 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 5040 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 5041 { 5042 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 5043 } 5044 5045 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 5046 5047 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 5048 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 5049 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 5050 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 5051 { 5052 assert(!(val & 0x3)); 5053 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 5054 } 5055 #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 5056 5057 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 5058 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 5059 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 5060 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 5061 { 5062 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 5063 } 5064 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 5065 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 5066 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 5067 { 5068 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 5069 } 5070 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 5071 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 5072 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 5073 { 5074 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 5075 } 5076 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 5077 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 5078 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 5079 { 5080 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 5081 } 5082 5083 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 5084 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 5085 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 5086 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 5087 { 5088 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 5089 } 5090 5091 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 5092 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 5093 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 5094 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 5095 { 5096 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 5097 } 5098 5099 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 5100 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 5101 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 5102 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 5103 { 5104 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 5105 } 5106 5107 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 5108 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 5109 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 5110 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 5111 { 5112 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 5113 } 5114 5115 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 5116 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 5117 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 5118 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 5119 { 5120 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 5121 } 5122 5123 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 5124 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 5125 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 5126 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 5127 { 5128 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 5129 } 5130 5131 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 5132 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 5133 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 5134 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 5135 { 5136 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 5137 } 5138 #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 5139 #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 5140 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) 5141 { 5142 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK; 5143 } 5144 #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 5145 #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 5146 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) 5147 { 5148 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK; 5149 } 5150 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 5151 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 5152 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 5153 { 5154 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 5155 } 5156 5157 #define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998 5158 5159 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 5160 5161 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 5162 5163 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 5164 5165 #define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08 5166 5167 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 5168 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 5169 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 5170 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 5171 { 5172 assert(!(val & 0x3)); 5173 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 5174 } 5175 #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 5176 5177 #define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11 5178 5179 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 5180 5181 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 5182 5183 #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 5184 5185 #define REG_A6XX_TEX_SAMP_0 0x00000000 5186 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 5187 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 5188 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 5189 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 5190 { 5191 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 5192 } 5193 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 5194 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 5195 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 5196 { 5197 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 5198 } 5199 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 5200 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 5201 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 5202 { 5203 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 5204 } 5205 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 5206 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 5207 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 5208 { 5209 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 5210 } 5211 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 5212 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 5213 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 5214 { 5215 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 5216 } 5217 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 5218 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 5219 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 5220 { 5221 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 5222 } 5223 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 5224 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 5225 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 5226 { 5227 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 5228 } 5229 5230 #define REG_A6XX_TEX_SAMP_1 0x00000001 5231 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 5232 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 5233 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 5234 { 5235 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 5236 } 5237 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 5238 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 5239 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 5240 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 5241 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 5242 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 5243 { 5244 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 5245 } 5246 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 5247 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 5248 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 5249 { 5250 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 5251 } 5252 5253 #define REG_A6XX_TEX_SAMP_2 0x00000002 5254 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffffff 5255 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 0 5256 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) 5257 { 5258 return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; 5259 } 5260 5261 #define REG_A6XX_TEX_SAMP_3 0x00000003 5262 5263 #define REG_A6XX_TEX_CONST_0 0x00000000 5264 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 5265 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 5266 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 5267 { 5268 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 5269 } 5270 #define A6XX_TEX_CONST_0_SRGB 0x00000004 5271 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 5272 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 5273 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 5274 { 5275 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 5276 } 5277 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 5278 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 5279 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 5280 { 5281 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 5282 } 5283 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 5284 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 5285 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 5286 { 5287 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 5288 } 5289 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 5290 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 5291 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 5292 { 5293 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 5294 } 5295 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 5296 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 5297 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 5298 { 5299 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 5300 } 5301 #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 5302 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 5303 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 5304 { 5305 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 5306 } 5307 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 5308 #define A6XX_TEX_CONST_0_FMT__SHIFT 22 5309 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val) 5310 { 5311 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 5312 } 5313 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 5314 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 5315 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 5316 { 5317 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 5318 } 5319 5320 #define REG_A6XX_TEX_CONST_1 0x00000001 5321 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 5322 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 5323 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 5324 { 5325 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 5326 } 5327 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 5328 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 5329 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 5330 { 5331 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 5332 } 5333 5334 #define REG_A6XX_TEX_CONST_2 0x00000002 5335 #define A6XX_TEX_CONST_2_UNK4 0x00000010 5336 #define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 5337 #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 5338 static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val) 5339 { 5340 return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK; 5341 } 5342 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 5343 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 5344 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 5345 { 5346 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 5347 } 5348 #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000 5349 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 5350 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 5351 { 5352 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 5353 } 5354 #define A6XX_TEX_CONST_2_UNK31 0x80000000 5355 5356 #define REG_A6XX_TEX_CONST_3 0x00000003 5357 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 5358 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 5359 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 5360 { 5361 assert(!(val & 0xfff)); 5362 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 5363 } 5364 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 5365 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 5366 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 5367 { 5368 assert(!(val & 0xfff)); 5369 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 5370 } 5371 #define A6XX_TEX_CONST_3_UNK27 0x08000000 5372 #define A6XX_TEX_CONST_3_FLAG 0x10000000 5373 5374 #define REG_A6XX_TEX_CONST_4 0x00000004 5375 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 5376 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 5377 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 5378 { 5379 assert(!(val & 0x1f)); 5380 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 5381 } 5382 5383 #define REG_A6XX_TEX_CONST_5 0x00000005 5384 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 5385 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 5386 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 5387 { 5388 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 5389 } 5390 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 5391 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 5392 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 5393 { 5394 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 5395 } 5396 5397 #define REG_A6XX_TEX_CONST_6 0x00000006 5398 5399 #define REG_A6XX_TEX_CONST_7 0x00000007 5400 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 5401 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 5402 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 5403 { 5404 assert(!(val & 0x1f)); 5405 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 5406 } 5407 5408 #define REG_A6XX_TEX_CONST_8 0x00000008 5409 #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 5410 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 5411 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 5412 { 5413 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 5414 } 5415 5416 #define REG_A6XX_TEX_CONST_9 0x00000009 5417 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 5418 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 5419 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 5420 { 5421 assert(!(val & 0xf)); 5422 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 5423 } 5424 5425 #define REG_A6XX_TEX_CONST_10 0x0000000a 5426 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 5427 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 5428 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 5429 { 5430 assert(!(val & 0x3f)); 5431 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 5432 } 5433 5434 #define REG_A6XX_TEX_CONST_11 0x0000000b 5435 5436 #define REG_A6XX_TEX_CONST_12 0x0000000c 5437 5438 #define REG_A6XX_TEX_CONST_13 0x0000000d 5439 5440 #define REG_A6XX_TEX_CONST_14 0x0000000e 5441 5442 #define REG_A6XX_TEX_CONST_15 0x0000000f 5443 5444 #define REG_A6XX_IBO_0 0x00000000 5445 #define A6XX_IBO_0_TILE_MODE__MASK 0x00000003 5446 #define A6XX_IBO_0_TILE_MODE__SHIFT 0 5447 static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val) 5448 { 5449 return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK; 5450 } 5451 #define A6XX_IBO_0_FMT__MASK 0x3fc00000 5452 #define A6XX_IBO_0_FMT__SHIFT 22 5453 static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_tex_fmt val) 5454 { 5455 return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK; 5456 } 5457 5458 #define REG_A6XX_IBO_1 0x00000001 5459 #define A6XX_IBO_1_WIDTH__MASK 0x00007fff 5460 #define A6XX_IBO_1_WIDTH__SHIFT 0 5461 static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val) 5462 { 5463 return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK; 5464 } 5465 #define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000 5466 #define A6XX_IBO_1_HEIGHT__SHIFT 15 5467 static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val) 5468 { 5469 return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK; 5470 } 5471 5472 #define REG_A6XX_IBO_2 0x00000002 5473 #define A6XX_IBO_2_UNK4 0x00000010 5474 #define A6XX_IBO_2_PITCH__MASK 0x1fffff80 5475 #define A6XX_IBO_2_PITCH__SHIFT 7 5476 static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val) 5477 { 5478 return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK; 5479 } 5480 #define A6XX_IBO_2_TYPE__MASK 0x60000000 5481 #define A6XX_IBO_2_TYPE__SHIFT 29 5482 static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val) 5483 { 5484 return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK; 5485 } 5486 #define A6XX_IBO_2_UNK31 0x80000000 5487 5488 #define REG_A6XX_IBO_3 0x00000003 5489 #define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff 5490 #define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0 5491 static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val) 5492 { 5493 assert(!(val & 0xfff)); 5494 return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK; 5495 } 5496 #define A6XX_IBO_3_UNK27 0x08000000 5497 #define A6XX_IBO_3_FLAG 0x10000000 5498 5499 #define REG_A6XX_IBO_4 0x00000004 5500 #define A6XX_IBO_4_BASE_LO__MASK 0xffffffff 5501 #define A6XX_IBO_4_BASE_LO__SHIFT 0 5502 static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val) 5503 { 5504 return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK; 5505 } 5506 5507 #define REG_A6XX_IBO_5 0x00000005 5508 #define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff 5509 #define A6XX_IBO_5_BASE_HI__SHIFT 0 5510 static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val) 5511 { 5512 return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK; 5513 } 5514 #define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000 5515 #define A6XX_IBO_5_DEPTH__SHIFT 17 5516 static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val) 5517 { 5518 return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK; 5519 } 5520 5521 #define REG_A6XX_IBO_6 0x00000006 5522 5523 #define REG_A6XX_IBO_7 0x00000007 5524 5525 #define REG_A6XX_IBO_8 0x00000008 5526 5527 #define REG_A6XX_IBO_9 0x00000009 5528 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 5529 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 5530 static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 5531 { 5532 assert(!(val & 0xf)); 5533 return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 5534 } 5535 5536 #define REG_A6XX_IBO_10 0x0000000a 5537 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 5538 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0 5539 static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val) 5540 { 5541 assert(!(val & 0x3f)); 5542 return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK; 5543 } 5544 5545 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 5546 5547 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 5548 5549 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 5550 5551 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 5552 5553 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 5554 5555 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 5556 5557 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 5558 5559 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 5560 5561 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 5562 5563 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 5564 5565 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 5566 5567 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 5568 5569 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 5570 5571 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 5572 5573 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 5574 5575 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 5576 5577 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 5578 5579 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 5580 5581 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 5582 5583 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 5584 5585 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 5586 5587 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 5588 5589 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 5590 5591 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 5592 5593 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 5594 5595 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 5596 5597 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 5598 5599 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 5600 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 5601 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 5602 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 5603 { 5604 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 5605 } 5606 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 5607 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 5608 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 5609 { 5610 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 5611 } 5612 5613 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 5614 5615 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 5616 5617 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 5618 5619 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 5620 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 5621 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 5622 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 5623 { 5624 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 5625 } 5626 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 5627 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 5628 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 5629 { 5630 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 5631 } 5632 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 5633 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 5634 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 5635 { 5636 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 5637 } 5638 5639 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 5640 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 5641 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 5642 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 5643 { 5644 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 5645 } 5646 5647 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 5648 5649 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 5650 5651 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 5652 5653 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 5654 5655 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 5656 5657 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 5658 5659 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 5660 5661 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 5662 5663 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 5664 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 5665 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 5666 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 5667 { 5668 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 5669 } 5670 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 5671 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 5672 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 5673 { 5674 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 5675 } 5676 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 5677 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 5678 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 5679 { 5680 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 5681 } 5682 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 5683 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 5684 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 5685 { 5686 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 5687 } 5688 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 5689 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 5690 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 5691 { 5692 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 5693 } 5694 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 5695 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 5696 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 5697 { 5698 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 5699 } 5700 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 5701 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 5702 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 5703 { 5704 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 5705 } 5706 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 5707 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 5708 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 5709 { 5710 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 5711 } 5712 5713 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 5714 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 5715 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 5716 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 5717 { 5718 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 5719 } 5720 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 5721 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 5722 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 5723 { 5724 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 5725 } 5726 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 5727 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 5728 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 5729 { 5730 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 5731 } 5732 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 5733 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 5734 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 5735 { 5736 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 5737 } 5738 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 5739 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 5740 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 5741 { 5742 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 5743 } 5744 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 5745 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 5746 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 5747 { 5748 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 5749 } 5750 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 5751 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 5752 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 5753 { 5754 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 5755 } 5756 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 5757 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 5758 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 5759 { 5760 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 5761 } 5762 5763 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 5764 5765 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 5766 5767 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 5768 5769 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 5770 5771 5772 #endif /* A6XX_XML */ 5773
Indexes created Sat Aug 01 00:24:56 UTC 2026