1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2022 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_H 23 #define GCC_AARCH64_H 24 25 /* Target CPU builtins. */ 26 #define TARGET_CPU_CPP_BUILTINS() \ 27 aarch64_cpu_cpp_builtins (pfile) 28 29 30 32 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () 33 34 /* Target machine storage layout. */ 35 36 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 37 if (GET_MODE_CLASS (MODE) == MODE_INT \ 38 && GET_MODE_SIZE (MODE) < 4) \ 39 { \ 40 if (MODE == QImode || MODE == HImode) \ 41 { \ 42 MODE = SImode; \ 43 } \ 44 } 45 46 /* Bits are always numbered from the LSBit. */ 47 #define BITS_BIG_ENDIAN 0 48 49 /* Big/little-endian flavour. */ 50 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 51 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 52 53 /* AdvSIMD is supported in the default configuration, unless disabled by 54 -mgeneral-regs-only or by the +nosimd extension. */ 55 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 56 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 57 58 #define UNITS_PER_WORD 8 59 60 #define UNITS_PER_VREG 16 61 62 #define PARM_BOUNDARY 64 63 64 #define STACK_BOUNDARY 128 65 66 #define FUNCTION_BOUNDARY 32 67 68 #define EMPTY_FIELD_BOUNDARY 32 69 70 #define BIGGEST_ALIGNMENT 128 71 72 #define SHORT_TYPE_SIZE 16 73 74 #define INT_TYPE_SIZE 32 75 76 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 77 78 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 79 80 #define LONG_LONG_TYPE_SIZE 64 81 82 #define FLOAT_TYPE_SIZE 32 83 84 #define DOUBLE_TYPE_SIZE 64 85 86 #define LONG_DOUBLE_TYPE_SIZE 128 87 88 /* This value is the amount of bytes a caller is allowed to drop the stack 89 before probing has to be done for stack clash protection. */ 90 #define STACK_CLASH_CALLER_GUARD 1024 91 92 /* This value represents the minimum amount of bytes we expect the function's 93 outgoing arguments to be when stack-clash is enabled. */ 94 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8 95 96 /* This value controls how many pages we manually unroll the loop for when 97 generating stack clash probes. */ 98 #define STACK_CLASH_MAX_UNROLL_PAGES 4 99 100 /* The architecture reserves all bits of the address for hardware use, 101 so the vbit must go into the delta field of pointers to member 102 functions. This is the same config as that in the AArch32 103 port. */ 104 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 105 106 107 /* Emit calls to libgcc helpers for atomic operations for runtime detection 108 of LSE instructions. */ 109 #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics) 110 111 /* Align definitions of arrays, unions and structures so that 112 initializations and copies can be made more efficient. This is not 113 ABI-changing, so it only affects places where we can see the 114 definition. Increasing the alignment tends to introduce padding, 115 so don't do this when optimizing for size/conserving stack space. */ 116 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 117 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 118 && (TREE_CODE (EXP) == ARRAY_TYPE \ 119 || TREE_CODE (EXP) == UNION_TYPE \ 120 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 121 122 /* Align global data. */ 123 #define DATA_ALIGNMENT(EXP, ALIGN) \ 124 AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN) 125 126 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 127 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 128 AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN) 129 130 #define STRUCTURE_SIZE_BOUNDARY 8 131 132 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */ 133 #define MALLOC_ABI_ALIGNMENT 128 134 135 /* Defined by the ABI */ 136 #define WCHAR_TYPE "unsigned int" 137 #define WCHAR_TYPE_SIZE 32 138 139 /* Using long long breaks -ansi and -std=c90, so these will need to be 140 made conditional for an LLP64 ABI. */ 141 142 #define SIZE_TYPE "long unsigned int" 143 144 #define PTRDIFF_TYPE "long int" 145 146 #define PCC_BITFIELD_TYPE_MATTERS 1 147 148 /* Major revision number of the ARM Architecture implemented by the target. */ 149 extern unsigned aarch64_architecture_version; 150 151 /* Instruction tuning/selection flags. */ 152 153 /* Bit values used to identify processor capabilities. */ 154 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 155 #define AARCH64_FL_FP (1 << 1) /* Has FP. */ 156 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 157 #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ 158 /* ARMv8.1-A architecture extensions. */ 159 #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ 160 #define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ 161 #define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ 162 /* Armv8-R. */ 163 #define AARCH64_FL_V8_R (1 << 7) /* Armv8-R AArch64. */ 164 /* ARMv8.2-A architecture extensions. */ 165 #define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ 166 #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ 167 #define AARCH64_FL_SVE (1 << 10) /* Has Scalable Vector Extensions. */ 168 /* ARMv8.3-A architecture extensions. */ 169 #define AARCH64_FL_V8_3 (1 << 11) /* Has ARMv8.3-A features. */ 170 #define AARCH64_FL_RCPC (1 << 12) /* Has support for RCpc model. */ 171 #define AARCH64_FL_DOTPROD (1 << 13) /* Has ARMv8.2-A Dot Product ins. */ 172 /* New flags to split crypto into aes and sha2. */ 173 #define AARCH64_FL_AES (1 << 14) /* Has Crypto AES. */ 174 #define AARCH64_FL_SHA2 (1 << 15) /* Has Crypto SHA2. */ 175 /* ARMv8.4-A architecture extensions. */ 176 #define AARCH64_FL_V8_4 (1 << 16) /* Has ARMv8.4-A features. */ 177 #define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */ 178 #define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */ 179 #define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */ 180 #define AARCH64_FL_RCPC8_4 (1 << 20) /* Has ARMv8.4-a RCPC extensions. */ 181 182 /* Statistical Profiling extensions. */ 183 #define AARCH64_FL_PROFILE (1 << 21) 184 185 /* ARMv8.5-A architecture extensions. */ 186 #define AARCH64_FL_V8_5 (1 << 22) /* Has ARMv8.5-A features. */ 187 #define AARCH64_FL_RNG (1 << 23) /* ARMv8.5-A Random Number Insns. */ 188 #define AARCH64_FL_MEMTAG (1 << 24) /* ARMv8.5-A Memory Tagging 189 Extensions. */ 190 191 /* Speculation Barrier instruction supported. */ 192 #define AARCH64_FL_SB (1 << 25) 193 194 /* Speculative Store Bypass Safe instruction supported. */ 195 #define AARCH64_FL_SSBS (1 << 26) 196 197 /* Execution and Data Prediction Restriction instructions supported. */ 198 #define AARCH64_FL_PREDRES (1 << 27) 199 200 /* SVE2 instruction supported. */ 201 #define AARCH64_FL_SVE2 (1 << 28) 202 #define AARCH64_FL_SVE2_AES (1 << 29) 203 #define AARCH64_FL_SVE2_SM4 (1 << 30) 204 #define AARCH64_FL_SVE2_SHA3 (1ULL << 31) 205 #define AARCH64_FL_SVE2_BITPERM (1ULL << 32) 206 207 /* Transactional Memory Extension. */ 208 #define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */ 209 210 /* Armv8.6-A architecture extensions. */ 211 #define AARCH64_FL_V8_6 (1ULL << 34) 212 213 /* 8-bit Integer Matrix Multiply (I8MM) extensions. */ 214 #define AARCH64_FL_I8MM (1ULL << 35) 215 216 /* Brain half-precision floating-point (BFloat16) Extension. */ 217 #define AARCH64_FL_BF16 (1ULL << 36) 218 219 /* 32-bit Floating-point Matrix Multiply (F32MM) extensions. */ 220 #define AARCH64_FL_F32MM (1ULL << 37) 221 222 /* 64-bit Floating-point Matrix Multiply (F64MM) extensions. */ 223 #define AARCH64_FL_F64MM (1ULL << 38) 224 225 /* Flag Manipulation Instructions (FLAGM) extension. */ 226 #define AARCH64_FL_FLAGM (1ULL << 39) 227 228 /* Pointer Authentication (PAUTH) extension. */ 229 #define AARCH64_FL_PAUTH (1ULL << 40) 230 231 /* Armv9.0-A. */ 232 #define AARCH64_FL_V9 (1ULL << 41) /* Armv9.0-A Architecture. */ 233 234 /* 64-byte atomic load/store extensions. */ 235 #define AARCH64_FL_LS64 (1ULL << 42) 236 237 /* Armv8.7-a architecture extensions. */ 238 #define AARCH64_FL_V8_7 (1ULL << 43) 239 240 /* Hardware memory operation instructions. */ 241 #define AARCH64_FL_MOPS (1ULL << 44) 242 243 /* Armv8.8-a architecture extensions. */ 244 #define AARCH64_FL_V8_8 (1ULL << 45) 245 246 /* Has FP and SIMD. */ 247 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 248 249 /* Has FP without SIMD. */ 250 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 251 252 /* Architecture flags that effect instruction selection. */ 253 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 254 #define AARCH64_FL_FOR_ARCH8_1 \ 255 (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \ 256 | AARCH64_FL_RDMA | AARCH64_FL_V8_1) 257 #define AARCH64_FL_FOR_ARCH8_2 \ 258 (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) 259 #define AARCH64_FL_FOR_ARCH8_3 \ 260 (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3 | AARCH64_FL_PAUTH \ 261 | AARCH64_FL_RCPC) 262 #define AARCH64_FL_FOR_ARCH8_4 \ 263 (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \ 264 | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4 | AARCH64_FL_FLAGM) 265 #define AARCH64_FL_FOR_ARCH8_5 \ 266 (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \ 267 | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) 268 #define AARCH64_FL_FOR_ARCH8_6 \ 269 (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \ 270 | AARCH64_FL_I8MM | AARCH64_FL_BF16) 271 #define AARCH64_FL_FOR_ARCH8_7 \ 272 (AARCH64_FL_FOR_ARCH8_6 | AARCH64_FL_V8_7) 273 #define AARCH64_FL_FOR_ARCH8_8 \ 274 (AARCH64_FL_FOR_ARCH8_7 | AARCH64_FL_V8_8 | AARCH64_FL_MOPS) 275 276 #define AARCH64_FL_FOR_ARCH8_R \ 277 (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_R) 278 #define AARCH64_FL_FOR_ARCH9 \ 279 (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_V9 \ 280 | AARCH64_FL_F16) 281 282 /* Macros to test ISA flags. */ 283 284 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 285 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 286 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 287 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 288 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) 289 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) 290 #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) 291 #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) 292 #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) 293 #define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2) 294 #define AARCH64_ISA_SVE2_AES (aarch64_isa_flags & AARCH64_FL_SVE2_AES) 295 #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) 296 #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) 297 #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) 298 #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) 299 #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) 300 #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) 301 #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) 302 #define AARCH64_ISA_V8_4 (aarch64_isa_flags & AARCH64_FL_V8_4) 303 #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) 304 #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) 305 #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) 306 #define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC) 307 #define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4) 308 #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) 309 #define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARCH64_FL_V8_5) 310 #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) 311 #define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG) 312 #define AARCH64_ISA_V8_6 (aarch64_isa_flags & AARCH64_FL_V8_6) 313 #define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM) 314 #define AARCH64_ISA_F32MM (aarch64_isa_flags & AARCH64_FL_F32MM) 315 #define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM) 316 #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) 317 #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) 318 #define AARCH64_ISA_V8_R (aarch64_isa_flags & AARCH64_FL_V8_R) 319 #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) 320 #define AARCH64_ISA_V9 (aarch64_isa_flags & AARCH64_FL_V9) 321 #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) 322 #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) 323 324 /* Crypto is an optional extension to AdvSIMD. */ 325 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) 326 327 /* SHA2 is an optional extension to AdvSIMD. */ 328 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO) 329 330 /* SHA3 is an optional extension to AdvSIMD. */ 331 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3) 332 333 /* AES is an optional extension to AdvSIMD. */ 334 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO) 335 336 /* SM is an optional extension to AdvSIMD. */ 337 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4) 338 339 /* FP16FML is an optional extension to AdvSIMD. */ 340 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) 341 342 /* CRC instructions that can be enabled through +crc arch extension. */ 343 #define TARGET_CRC32 (AARCH64_ISA_CRC) 344 345 /* Atomic instructions that can be enabled through the +lse extension. */ 346 #define TARGET_LSE (AARCH64_ISA_LSE) 347 348 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ 349 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) 350 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) 351 352 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ 353 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD) 354 355 /* SVE instructions, enabled through +sve. */ 356 #define TARGET_SVE (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SVE) 357 358 /* SVE2 instructions, enabled through +sve2. */ 359 #define TARGET_SVE2 (TARGET_SVE && AARCH64_ISA_SVE2) 360 361 /* SVE2 AES instructions, enabled through +sve2-aes. */ 362 #define TARGET_SVE2_AES (TARGET_SVE2 && AARCH64_ISA_SVE2_AES) 363 364 /* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */ 365 #define TARGET_SVE2_BITPERM (TARGET_SVE2 && AARCH64_ISA_SVE2_BITPERM) 366 367 /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */ 368 #define TARGET_SVE2_SHA3 (TARGET_SVE2 && AARCH64_ISA_SVE2_SHA3) 369 370 /* SVE2 SM4 instructions, enabled through +sve2-sm4. */ 371 #define TARGET_SVE2_SM4 (TARGET_SVE2 && AARCH64_ISA_SVE2_SM4) 372 373 /* ARMv8.3-A features. */ 374 #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) 375 376 /* Javascript conversion instruction from Armv8.3-a. */ 377 #define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3) 378 379 /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ 380 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) 381 382 /* Floating-point rounding instructions from Armv8.5-a. */ 383 #define TARGET_FRINT (AARCH64_ISA_V8_5 && TARGET_FLOAT) 384 385 /* TME instructions are enabled. */ 386 #define TARGET_TME (AARCH64_ISA_TME) 387 388 /* Random number instructions from Armv8.5-a. */ 389 #define TARGET_RNG (AARCH64_ISA_RNG) 390 391 /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */ 392 #define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG) 393 394 /* I8MM instructions are enabled through +i8mm. */ 395 #define TARGET_I8MM (AARCH64_ISA_I8MM) 396 #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM) 397 398 /* F32MM instructions are enabled through +f32mm. */ 399 #define TARGET_F32MM (AARCH64_ISA_F32MM) 400 #define TARGET_SVE_F32MM (TARGET_SVE && AARCH64_ISA_F32MM) 401 402 /* F64MM instructions are enabled through +f64mm. */ 403 #define TARGET_F64MM (AARCH64_ISA_F64MM) 404 #define TARGET_SVE_F64MM (TARGET_SVE && AARCH64_ISA_F64MM) 405 406 /* BF16 instructions are enabled through +bf16. */ 407 #define TARGET_BF16_FP (AARCH64_ISA_BF16) 408 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD) 409 #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16) 410 411 /* PAUTH instructions are enabled through +pauth. */ 412 #define TARGET_PAUTH (AARCH64_ISA_PAUTH) 413 414 /* MOPS instructions are enabled through +mops. */ 415 #define TARGET_MOPS (AARCH64_ISA_MOPS) 416 417 /* LS64 instructions are enabled through +ls64. */ 418 #define TARGET_LS64 (AARCH64_ISA_LS64) 419 420 /* Make sure this is always defined so we don't have to check for ifdefs 421 but rather use normal ifs. */ 422 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT 423 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 424 #else 425 #undef TARGET_FIX_ERR_A53_835769_DEFAULT 426 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 427 #endif 428 429 /* SB instruction is enabled through +sb. */ 430 #define TARGET_SB (AARCH64_ISA_SB) 431 432 /* Apply the workaround for Cortex-A53 erratum 835769. */ 433 #define TARGET_FIX_ERR_A53_835769 \ 434 ((aarch64_fix_a53_err835769 == 2) \ 435 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) 436 437 /* Make sure this is always defined so we don't have to check for ifdefs 438 but rather use normal ifs. */ 439 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT 440 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 441 #else 442 #undef TARGET_FIX_ERR_A53_843419_DEFAULT 443 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 444 #endif 445 446 /* Apply the workaround for Cortex-A53 erratum 843419. */ 447 #define TARGET_FIX_ERR_A53_843419 \ 448 ((aarch64_fix_a53_err843419 == 2) \ 449 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) 450 451 /* ARMv8.1-A Adv.SIMD support. */ 452 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) 453 454 /* Standard register usage. */ 455 456 /* 31 64-bit general purpose registers R0-R30: 457 R30 LR (link register) 458 R29 FP (frame pointer) 459 R19-R28 Callee-saved registers 460 R18 The platform register; use as temporary register. 461 R17 IP1 The second intra-procedure-call temporary register 462 (can be used by call veneers and PLT code); otherwise use 463 as a temporary register 464 R16 IP0 The first intra-procedure-call temporary register (can 465 be used by call veneers and PLT code); otherwise use as a 466 temporary register 467 R9-R15 Temporary registers 468 R8 Structure value parameter / temporary register 469 R0-R7 Parameter/result registers 470 471 SP stack pointer, encoded as X/R31 where permitted. 472 ZR zero register, encoded as X/R31 elsewhere 473 474 32 x 128-bit floating-point/vector registers 475 V16-V31 Caller-saved (temporary) registers 476 V8-V15 Callee-saved registers 477 V0-V7 Parameter/result registers 478 479 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 480 significant bits. Unlike AArch32 S1 is not packed into D0, etc. 481 482 P0-P7 Predicate low registers: valid in all predicate contexts 483 P8-P15 Predicate high registers: used as scratch space 484 485 FFR First Fault Register, a fixed-use SVE predicate register 486 FFRT FFR token: a fake register used for modelling dependencies 487 488 VG Pseudo "vector granules" register 489 490 VG is the number of 64-bit elements in an SVE vector. We define 491 it as a hard register so that we can easily map it to the DWARF VG 492 register. GCC internally uses the poly_int variable aarch64_sve_vg 493 instead. */ 494 495 #define FIXED_REGISTERS \ 496 { \ 497 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 498 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 499 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 500 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 501 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 502 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 503 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 504 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 505 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 506 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \ 507 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \ 508 1, 1 /* FFR and FFRT */ \ 509 } 510 511 /* X30 is marked as caller-saved which is in line with regular function call 512 behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does 513 that for regular function calls and avoids it for sibcalls. X30 is 514 considered live for sibcalls; EPILOGUE_USES helps achieve that by returning 515 true but not until function epilogues have been generated. This ensures 516 that X30 is available for use in leaf functions if needed. */ 517 518 #define CALL_USED_REGISTERS \ 519 { \ 520 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 521 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 522 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 523 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 524 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 525 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 526 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 527 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 528 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 529 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \ 530 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \ 531 1, 1 /* FFR and FFRT */ \ 532 } 533 534 #define REGISTER_NAMES \ 535 { \ 536 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 537 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 538 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 539 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 540 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 541 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 542 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 543 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 544 "sfp", "ap", "cc", "vg", \ 545 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \ 546 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \ 547 "ffr", "ffrt" \ 548 } 549 550 /* Generate the register aliases for core register N */ 551 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 552 {"w" # N, R0_REGNUM + (N)} 553 554 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 555 {"d" # N, V0_REGNUM + (N)}, \ 556 {"s" # N, V0_REGNUM + (N)}, \ 557 {"h" # N, V0_REGNUM + (N)}, \ 558 {"b" # N, V0_REGNUM + (N)}, \ 559 {"z" # N, V0_REGNUM + (N)} 560 561 /* Provide aliases for all of the ISA defined register name forms. 562 These aliases are convenient for use in the clobber lists of inline 563 asm statements. */ 564 565 #define ADDITIONAL_REGISTER_NAMES \ 566 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 567 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 568 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 569 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 570 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 571 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 572 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 573 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 574 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 575 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 576 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 577 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 578 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 579 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 580 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 581 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 582 } 583 584 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO)) 585 586 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 587 the stack pointer does not matter. This is only true if the function 588 uses alloca. */ 589 #define EXIT_IGNORE_STACK (cfun->calls_alloca) 590 591 #define STATIC_CHAIN_REGNUM R18_REGNUM 592 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM 593 #define FRAME_POINTER_REGNUM SFP_REGNUM 594 #define STACK_POINTER_REGNUM SP_REGNUM 595 #define ARG_POINTER_REGNUM AP_REGNUM 596 #define FIRST_PSEUDO_REGISTER (FFRT_REGNUM + 1) 597 598 /* The number of argument registers available for each class. */ 599 #define NUM_ARG_REGS 8 600 #define NUM_FP_ARG_REGS 8 601 #define NUM_PR_ARG_REGS 4 602 603 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 604 four members. */ 605 #define HA_MAX_NUM_FLDS 4 606 607 /* External dwarf register number scheme. These number are used to 608 identify registers in dwarf debug information, the values are 609 defined by the AArch64 ABI. The numbering scheme is independent of 610 GCC's internal register numbering scheme. */ 611 612 #define AARCH64_DWARF_R0 0 613 614 /* The number of R registers, note 31! not 32. */ 615 #define AARCH64_DWARF_NUMBER_R 31 616 617 #define AARCH64_DWARF_SP 31 618 #define AARCH64_DWARF_VG 46 619 #define AARCH64_DWARF_P0 48 620 #define AARCH64_DWARF_V0 64 621 622 /* The number of V registers. */ 623 #define AARCH64_DWARF_NUMBER_V 32 624 625 /* For signal frames we need to use an alternative return column. This 626 value must not correspond to a hard register and must be out of the 627 range of DWARF_FRAME_REGNUM(). */ 628 #define DWARF_ALT_FRAME_RETURN_COLUMN \ 629 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 630 631 /* We add 1 extra frame register for use as the 632 DWARF_ALT_FRAME_RETURN_COLUMN. */ 633 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 634 635 636 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 637 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 638 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 639 as the default definition in dwarf2out.cc. */ 640 #undef DWARF_FRAME_REGNUM 641 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 642 643 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 644 645 #define DWARF2_UNWIND_INFO 1 646 647 /* Use R0 through R3 to pass exception handling information. */ 648 #define EH_RETURN_DATA_REGNO(N) \ 649 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 650 651 /* Select a format to encode pointers in exception handling data. */ 652 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 653 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 654 655 /* Output the assembly strings we want to add to a function definition. */ 656 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 657 aarch64_declare_function_name (STR, NAME, DECL) 658 659 /* Output assembly strings for alias definition. */ 660 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ 661 aarch64_asm_output_alias (STR, DECL, TARGET) 662 663 /* Output assembly strings for undefined extern symbols. */ 664 #undef ASM_OUTPUT_EXTERNAL 665 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ 666 aarch64_asm_output_external (STR, DECL, NAME) 667 668 /* Output assembly strings after .cfi_startproc is emitted. */ 669 #define ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc 670 671 /* For EH returns X4 contains the stack adjustment. */ 672 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) 673 #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () 674 675 /* Don't use __builtin_setjmp until we've defined it. */ 676 #undef DONT_USE_BUILTIN_SETJMP 677 #define DONT_USE_BUILTIN_SETJMP 1 678 679 #undef TARGET_COMPUTE_FRAME_LAYOUT 680 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame 681 682 /* Register in which the structure value is to be returned. */ 683 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 684 685 /* Non-zero if REGNO is part of the Core register set. 686 687 The rather unusual way of expressing this check is to avoid 688 warnings when building the compiler when R0_REGNUM is 0 and REGNO 689 is unsigned. */ 690 #define GP_REGNUM_P(REGNO) \ 691 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 692 693 /* Registers known to be preserved over a BL instruction. This consists of the 694 GENERAL_REGS without x16, x17, and x30. The x30 register is changed by the 695 BL instruction itself, while the x16 and x17 registers may be used by 696 veneers which can be inserted by the linker. */ 697 #define STUB_REGNUM_P(REGNO) \ 698 (GP_REGNUM_P (REGNO) \ 699 && (REGNO) != R16_REGNUM \ 700 && (REGNO) != R17_REGNUM \ 701 && (REGNO) != R30_REGNUM) \ 702 703 #define FP_REGNUM_P(REGNO) \ 704 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 705 706 #define FP_LO_REGNUM_P(REGNO) \ 707 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 708 709 #define FP_LO8_REGNUM_P(REGNO) \ 710 (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) 711 712 #define PR_REGNUM_P(REGNO)\ 713 (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) 714 715 #define PR_LO_REGNUM_P(REGNO)\ 716 (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) 717 718 #define FP_SIMD_SAVED_REGNUM_P(REGNO) \ 719 (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM)) 720 721 /* Register and constant classes. */ 723 724 enum reg_class 725 { 726 NO_REGS, 727 TAILCALL_ADDR_REGS, 728 STUB_REGS, 729 GENERAL_REGS, 730 STACK_REG, 731 POINTER_REGS, 732 FP_LO8_REGS, 733 FP_LO_REGS, 734 FP_REGS, 735 POINTER_AND_FP_REGS, 736 PR_LO_REGS, 737 PR_HI_REGS, 738 PR_REGS, 739 FFR_REGS, 740 PR_AND_FFR_REGS, 741 ALL_REGS, 742 LIM_REG_CLASSES /* Last */ 743 }; 744 745 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 746 747 #define REG_CLASS_NAMES \ 748 { \ 749 "NO_REGS", \ 750 "TAILCALL_ADDR_REGS", \ 751 "STUB_REGS", \ 752 "GENERAL_REGS", \ 753 "STACK_REG", \ 754 "POINTER_REGS", \ 755 "FP_LO8_REGS", \ 756 "FP_LO_REGS", \ 757 "FP_REGS", \ 758 "POINTER_AND_FP_REGS", \ 759 "PR_LO_REGS", \ 760 "PR_HI_REGS", \ 761 "PR_REGS", \ 762 "FFR_REGS", \ 763 "PR_AND_FFR_REGS", \ 764 "ALL_REGS" \ 765 } 766 767 #define REG_CLASS_CONTENTS \ 768 { \ 769 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 770 { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ 771 { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \ 772 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 773 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 774 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 775 { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ 776 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 777 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 778 { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ 779 { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ 780 { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \ 781 { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \ 782 { 0x00000000, 0x00000000, 0x00300000 }, /* FFR_REGS */ \ 783 { 0x00000000, 0x00000000, 0x003ffff0 }, /* PR_AND_FFR_REGS */ \ 784 { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \ 785 } 786 787 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 788 789 #define INDEX_REG_CLASS GENERAL_REGS 790 #define BASE_REG_CLASS POINTER_REGS 791 792 /* Register pairs used to eliminate unneeded registers that point into 793 the stack frame. */ 794 #define ELIMINABLE_REGS \ 795 { \ 796 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 797 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 798 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 799 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 800 } 801 802 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 803 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 804 805 /* CPU/ARCH option handling. */ 806 #include "config/aarch64/aarch64-opts.h" 807 808 enum target_cpus 809 { 810 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ 811 TARGET_CPU_##INTERNAL_IDENT, 812 #include "aarch64-cores.def" 813 TARGET_CPU_generic 814 }; 815 816 /* Define how many bits are used to represent the CPU in TARGET_CPU_DEFAULT. 817 This needs to be big enough to fit the value of TARGET_CPU_generic. 818 All bits after this are used to represent the AARCH64_CPU_DEFAULT_FLAGS. */ 819 #define TARGET_CPU_NBITS 8 820 #define TARGET_CPU_MASK ((1 << TARGET_CPU_NBITS) - 1) 821 822 /* If there is no CPU defined at configure, use generic as default. */ 823 #ifndef TARGET_CPU_DEFAULT 824 #define TARGET_CPU_DEFAULT \ 825 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << TARGET_CPU_NBITS)) 826 #endif 827 828 /* If inserting NOP before a mult-accumulate insn remember to adjust the 829 length so that conditional branching code is updated appropriately. */ 830 #define ADJUST_INSN_LENGTH(insn, length) \ 831 do \ 832 { \ 833 if (aarch64_madd_needs_nop (insn)) \ 834 length += 4; \ 835 } while (0) 836 837 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 838 aarch64_final_prescan_insn (INSN); \ 839 840 /* The processor for which instructions should be scheduled. */ 841 extern enum aarch64_processor aarch64_tune; 842 843 /* RTL generation support. */ 844 #define INIT_EXPANDERS aarch64_init_expanders () 845 846 848 /* Stack layout; function entry, exit and calling. */ 849 #define STACK_GROWS_DOWNWARD 1 850 851 #define FRAME_GROWS_DOWNWARD 1 852 853 #define ACCUMULATE_OUTGOING_ARGS 1 854 855 #define FIRST_PARM_OFFSET(FNDECL) 0 856 857 /* Fix for VFP */ 858 #define LIBCALL_VALUE(MODE) \ 859 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 860 861 #define DEFAULT_PCC_STRUCT_RETURN 0 862 863 #ifdef HAVE_POLY_INT_H 864 struct GTY (()) aarch64_frame 865 { 866 /* The offset from the bottom of the static frame (the bottom of the 867 outgoing arguments) of each register save slot, or -2 if no save is 868 needed. */ 869 poly_int64 reg_offset[LAST_SAVED_REGNUM + 1]; 870 871 /* The number of extra stack bytes taken up by register varargs. 872 This area is allocated by the callee at the very top of the 873 frame. This value is rounded up to a multiple of 874 STACK_BOUNDARY. */ 875 HOST_WIDE_INT saved_varargs_size; 876 877 /* The number of bytes between the bottom of the static frame (the bottom 878 of the outgoing arguments) and the bottom of the register save area. 879 This value is always a multiple of STACK_BOUNDARY. */ 880 poly_int64 bytes_below_saved_regs; 881 882 /* The number of bytes between the bottom of the static frame (the bottom 883 of the outgoing arguments) and the hard frame pointer. This value is 884 always a multiple of STACK_BOUNDARY. */ 885 poly_int64 bytes_below_hard_fp; 886 887 /* The number of bytes between the top of the locals area and the top 888 of the frame (the incomming SP). This value is always a multiple of 889 STACK_BOUNDARY. */ 890 poly_int64 bytes_above_locals; 891 892 /* The number of bytes between the hard_frame_pointer and the top of 893 the frame (the incomming SP). This value is always a multiple of 894 STACK_BOUNDARY. */ 895 poly_int64 bytes_above_hard_fp; 896 897 /* The size of the frame, i.e. the number of bytes between the bottom 898 of the outgoing arguments and the incoming SP. This value is always 899 a multiple of STACK_BOUNDARY. */ 900 poly_int64 frame_size; 901 902 /* The size of the initial stack adjustment before saving callee-saves. */ 903 poly_int64 initial_adjust; 904 905 /* The writeback value when pushing callee-save registers. 906 It is zero when no push is used. */ 907 HOST_WIDE_INT callee_adjust; 908 909 /* The size of the stack adjustment before saving or after restoring 910 SVE registers. */ 911 poly_int64 sve_callee_adjust; 912 913 /* The size of the stack adjustment after saving callee-saves. */ 914 poly_int64 final_adjust; 915 916 /* Store FP,LR and setup a frame pointer. */ 917 bool emit_frame_chain; 918 919 /* In each frame, we can associate up to two register saves with the 920 initial stack allocation. This happens in one of two ways: 921 922 (1) Using an STR or STP with writeback to perform the initial 923 stack allocation. When EMIT_FRAME_CHAIN, the registers will 924 be those needed to create a frame chain. 925 926 Indicated by CALLEE_ADJUST != 0. 927 928 (2) Using a separate STP to set up the frame record, after the 929 initial stack allocation but before setting up the frame pointer. 930 This is used if the offset is too large to use writeback. 931 932 Indicated by CALLEE_ADJUST == 0 && EMIT_FRAME_CHAIN. 933 934 These fields indicate which registers we've decided to handle using 935 (1) or (2), or INVALID_REGNUM if none. 936 937 In some cases we don't always need to pop all registers in the push 938 candidates, pop candidates record which registers need to be popped 939 eventually. The initial value of a pop candidate is copied from its 940 corresponding push candidate. 941 942 Currently, different pop candidates are only used for shadow call 943 stack. When "-fsanitize=shadow-call-stack" is specified, we replace 944 x30 in the pop candidate with INVALID_REGNUM to ensure that x30 is 945 not popped twice. */ 946 unsigned wb_push_candidate1; 947 unsigned wb_push_candidate2; 948 unsigned wb_pop_candidate1; 949 unsigned wb_pop_candidate2; 950 951 /* Big-endian SVE frames need a spare predicate register in order 952 to save vector registers in the correct layout for unwinding. 953 This is the register they should use. */ 954 unsigned spare_pred_reg; 955 956 /* An SVE register that is saved below the hard frame pointer and that acts 957 as a probe for later allocations, or INVALID_REGNUM if none. */ 958 unsigned sve_save_and_probe; 959 960 /* A register that is saved at the hard frame pointer and that acts 961 as a probe for later allocations, or INVALID_REGNUM if none. */ 962 unsigned hard_fp_save_and_probe; 963 964 bool laid_out; 965 966 /* True if shadow call stack should be enabled for the current function. */ 967 bool is_scs_enabled; 968 }; 969 970 #ifdef hash_set_h 971 typedef struct GTY (()) machine_function 972 { 973 struct aarch64_frame frame; 974 /* One entry for each hard register. */ 975 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; 976 /* One entry for each general purpose register. */ 977 rtx call_via[SP_REGNUM]; 978 bool label_is_assembled; 979 /* A set of all decls that have been passed to a vld1 intrinsic in the 980 current function. This is used to help guide the vector cost model. */ 981 hash_set<tree> *vector_load_decls; 982 } machine_function; 983 #endif 984 #endif 985 986 /* Which ABI to use. */ 987 enum aarch64_abi_type 988 { 989 AARCH64_ABI_LP64 = 0, 990 AARCH64_ABI_ILP32 = 1 991 }; 992 993 #ifndef AARCH64_ABI_DEFAULT 994 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 995 #endif 996 997 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 998 999 enum arm_pcs 1000 { 1001 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 1002 ARM_PCS_SIMD, /* For aarch64_vector_pcs functions. */ 1003 ARM_PCS_SVE, /* For functions that pass or return 1004 values in SVE registers. */ 1005 ARM_PCS_TLSDESC, /* For targets of tlsdesc calls. */ 1006 ARM_PCS_UNKNOWN 1007 }; 1008 1009 1010 1011 1012 /* We can't use machine_mode inside a generator file because it 1013 hasn't been created yet; we shouldn't be using any code that 1014 needs the real definition though, so this ought to be safe. */ 1015 #ifdef GENERATOR_FILE 1016 #define MACHMODE int 1017 #else 1018 #include "insn-modes.h" 1019 #define MACHMODE machine_mode 1020 #endif 1021 1022 #ifndef USED_FOR_TARGET 1023 /* AAPCS related state tracking. */ 1024 typedef struct 1025 { 1026 enum arm_pcs pcs_variant; 1027 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1028 int aapcs_ncrn; /* Next Core register number. */ 1029 int aapcs_nextncrn; /* Next next core register number. */ 1030 int aapcs_nvrn; /* Next Vector register number. */ 1031 int aapcs_nextnvrn; /* Next Next Vector register number. */ 1032 int aapcs_nprn; /* Next Predicate register number. */ 1033 int aapcs_nextnprn; /* Next Next Predicate register number. */ 1034 rtx aapcs_reg; /* Register assigned to this argument. This 1035 is NULL_RTX if this parameter goes on 1036 the stack. */ 1037 MACHMODE aapcs_vfp_rmode; 1038 int aapcs_stack_words; /* If the argument is passed on the stack, this 1039 is the number of words needed, after rounding 1040 up. Only meaningful when 1041 aapcs_reg == NULL_RTX. */ 1042 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 1043 stack arg area so far. */ 1044 bool silent_p; /* True if we should act silently, rather than 1045 raise an error for invalid calls. */ 1046 } CUMULATIVE_ARGS; 1047 #endif 1048 1049 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1050 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1051 1052 #define PAD_VARARGS_DOWN 0 1053 1054 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1055 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 1056 1057 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1058 aarch64_function_arg_regno_p(REGNO) 1059 1060 1062 /* ISA Features. */ 1063 1064 /* Addressing modes, etc. */ 1065 #define HAVE_POST_INCREMENT 1 1066 #define HAVE_PRE_INCREMENT 1 1067 #define HAVE_POST_DECREMENT 1 1068 #define HAVE_PRE_DECREMENT 1 1069 #define HAVE_POST_MODIFY_DISP 1 1070 #define HAVE_PRE_MODIFY_DISP 1 1071 1072 #define MAX_REGS_PER_ADDRESS 2 1073 1074 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 1075 1076 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1077 aarch64_regno_ok_for_base_p (REGNO, true) 1078 1079 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1080 aarch64_regno_ok_for_index_p (REGNO, true) 1081 1082 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1083 aarch64_legitimate_pic_operand_p (X) 1084 1085 #define CASE_VECTOR_MODE Pmode 1086 1087 #define DEFAULT_SIGNED_CHAR 0 1088 1089 /* An integer expression for the size in bits of the largest integer machine 1090 mode that should actually be used. We allow pairs of registers. */ 1091 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 1092 1093 /* Maximum bytes moved by a single instruction (load/store pair). */ 1094 #define MOVE_MAX (UNITS_PER_WORD * 2) 1095 1096 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 1097 #define AARCH64_CALL_RATIO 8 1098 1099 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 1100 move_by_pieces will continually copy the largest safe chunks. So a 1101 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 1102 for both size and speed of copy, so we will instead use the "cpymem" 1103 standard name to implement the copy. This logic does not apply when 1104 targeting -mstrict-align or TARGET_MOPS, so keep a sensible default in 1105 that case. */ 1106 #define MOVE_RATIO(speed) \ 1107 ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 1108 1109 /* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when 1110 we would use more than 3 scalar instructions. 1111 Otherwise follow a sensible default: when optimizing for size, give a better 1112 estimate of the length of a memset call, but use the default otherwise. */ 1113 #define CLEAR_RATIO(speed) \ 1114 (!STRICT_ALIGNMENT ? (TARGET_MOPS ? 0 : 4) : (speed) ? 15 : AARCH64_CALL_RATIO) 1115 1116 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant. Without 1117 -mstrict-align, make decisions in "setmem". Otherwise follow a sensible 1118 default: when optimizing for size adjust the ratio to account for the 1119 overhead of loading the constant. */ 1120 #define SET_RATIO(speed) \ 1121 ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2) 1122 1123 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 1124 rarely a good idea in straight-line code since it adds an extra address 1125 dependency between each instruction. Better to use incrementing offsets. */ 1126 #define USE_LOAD_POST_INCREMENT(MODE) 0 1127 #define USE_LOAD_POST_DECREMENT(MODE) 0 1128 #define USE_LOAD_PRE_INCREMENT(MODE) 0 1129 #define USE_LOAD_PRE_DECREMENT(MODE) 0 1130 #define USE_STORE_POST_INCREMENT(MODE) 0 1131 #define USE_STORE_POST_DECREMENT(MODE) 0 1132 #define USE_STORE_PRE_INCREMENT(MODE) 0 1133 #define USE_STORE_PRE_DECREMENT(MODE) 0 1134 1135 /* WORD_REGISTER_OPERATIONS does not hold for AArch64. 1136 The assigned word_mode is DImode but operations narrower than SImode 1137 behave as 32-bit operations if using the W-form of the registers rather 1138 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS 1139 expects. */ 1140 #define WORD_REGISTER_OPERATIONS 0 1141 1142 /* Define if loading from memory in MODE, an integral mode narrower than 1143 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 1144 macro should be the code that says which one of the two operations is 1145 implicitly done, or UNKNOWN if none. */ 1146 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1147 1148 /* Define this macro to be non-zero if instructions will fail to work 1149 if given data not on the nominal alignment. */ 1150 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 1151 1152 /* Enable wide bitfield accesses for more efficient bitfield code. */ 1153 #define SLOW_BYTE_ACCESS 1 1154 1155 #define NO_FUNCTION_CSE 1 1156 1157 /* Specify the machine mode that the hardware addresses have. 1158 After generation of rtl, the compiler makes no further distinction 1159 between pointers and any other objects of this machine mode. */ 1160 #define Pmode DImode 1161 1162 /* A C expression whose value is zero if pointers that need to be extended 1163 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1164 greater then zero if they are zero-extended and less then zero if the 1165 ptr_extend instruction should be used. */ 1166 #define POINTERS_EXTEND_UNSIGNED 1 1167 1168 /* Mode of a function address in a call instruction (for indexing purposes). */ 1169 #define FUNCTION_MODE Pmode 1170 1171 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 1172 1173 /* Having an integer comparison mode guarantees that we can use 1174 reverse_condition, but the usual restrictions apply to floating-point 1175 comparisons. */ 1176 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode) 1177 1178 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1179 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1180 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1181 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1182 1183 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 1184 1185 #define RETURN_ADDR_RTX aarch64_return_addr 1186 1187 /* BTI c + 3 insns 1188 + sls barrier of DSB + ISB. 1189 + 2 pointer-sized entries. */ 1190 #define TRAMPOLINE_SIZE (24 + (TARGET_ILP32 ? 8 : 16)) 1191 1192 /* Trampolines contain dwords, so must be dword aligned. */ 1193 #define TRAMPOLINE_ALIGNMENT 64 1194 1195 /* Put trampolines in the text section so that mapping symbols work 1196 correctly. */ 1197 #define TRAMPOLINE_SECTION text_section 1198 1199 /* To start with. */ 1200 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 1201 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) 1202 1203 1205 /* Assembly output. */ 1206 1207 /* For now we'll make all jump tables pc-relative. */ 1208 #define CASE_VECTOR_PC_RELATIVE 1 1209 1210 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1211 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 1212 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 1213 : QImode) 1214 1215 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 1216 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 1217 1218 #define MCOUNT_NAME "_mcount" 1219 1220 #define NO_PROFILE_COUNTERS 1 1221 1222 /* Emit rtl for profiling. Output assembler code to FILE 1223 to call "_mcount" for profiling a function entry. */ 1224 #define PROFILE_HOOK(LABEL) \ 1225 { \ 1226 rtx fun, lr; \ 1227 lr = aarch64_return_addr_rtx (); \ 1228 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 1229 emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \ 1230 } 1231 1232 /* All the work done in PROFILE_HOOK, but still required. */ 1233 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 1234 1235 /* For some reason, the Linux headers think they know how to define 1236 these macros. They don't!!! */ 1237 #undef ASM_APP_ON 1238 #undef ASM_APP_OFF 1239 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 1240 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 1241 1242 #define CONSTANT_POOL_BEFORE_FUNCTION 0 1243 1244 /* This definition should be relocated to aarch64-elf-raw.h. This macro 1245 should be undefined in aarch64-linux.h and a clear_cache pattern 1246 implmented to emit either the call to __aarch64_sync_cache_range() 1247 directly or preferably the appropriate sycall or cache clear 1248 instructions inline. */ 1249 #define CLEAR_INSN_CACHE(beg, end) \ 1250 extern void __aarch64_sync_cache_range (void *, void *); \ 1251 __aarch64_sync_cache_range (beg, end) 1252 1253 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) 1254 1255 /* Choose appropriate mode for caller saves, so we do the minimum 1256 required size of load/store. */ 1257 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1258 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 1259 1260 #undef SWITCHABLE_TARGET 1261 #define SWITCHABLE_TARGET 1 1262 1263 /* Check TLS Descriptors mechanism is selected. */ 1264 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 1265 1266 extern enum aarch64_code_model aarch64_cmodel; 1267 1268 /* When using the tiny addressing model conditional and unconditional branches 1269 can span the whole of the available address space (1MB). */ 1270 #define HAS_LONG_COND_BRANCH \ 1271 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1272 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1273 1274 #define HAS_LONG_UNCOND_BRANCH \ 1275 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1276 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1277 1278 #define TARGET_SUPPORTS_WIDE_INT 1 1279 1280 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ 1281 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ 1282 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1283 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ 1284 || (MODE) == DFmode || (MODE) == V4BFmode) 1285 1286 /* Modes valid for AdvSIMD Q registers. */ 1287 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 1288 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1289 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ 1290 || (MODE) == V2DFmode || (MODE) == V8BFmode) 1291 1292 #define ENDIAN_LANE_N(NUNITS, N) \ 1293 (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) 1294 1295 /* Support for configure-time --with-arch, --with-cpu and --with-tune. 1296 --with-arch and --with-cpu are ignored if either -mcpu or -march is used. 1297 --with-tune is ignored if either -mtune or -mcpu is used (but is not 1298 affected by -march). */ 1299 #define OPTION_DEFAULT_SPECS \ 1300 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 1301 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 1302 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"}, 1303 1304 #define MCPU_TO_MARCH_SPEC \ 1305 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" 1306 1307 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 1308 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ 1309 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 1310 1311 #if defined(__aarch64__) && (defined(__linux__) || defined(__NetBSD__)) 1312 extern const char *host_detect_local_cpu (int argc, const char **argv); 1313 #define HAVE_LOCAL_CPU_DETECT 1314 # define EXTRA_SPEC_FUNCTIONS \ 1315 { "local_cpu_detect", host_detect_local_cpu }, \ 1316 MCPU_TO_MARCH_SPEC_FUNCTIONS 1317 1318 # define MCPU_MTUNE_NATIVE_SPECS \ 1319 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 1320 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 1321 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 1322 #else 1323 # define MCPU_MTUNE_NATIVE_SPECS "" 1324 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS 1325 #endif 1326 1327 #define ASM_CPU_SPEC \ 1328 MCPU_TO_MARCH_SPEC 1329 1330 #define EXTRA_SPECS \ 1331 { "asm_cpu_spec", ASM_CPU_SPEC } 1332 1333 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue 1334 1335 /* This type is the user-visible __fp16, and a pointer to that type. We 1336 need it in many places in the backend. Defined in aarch64-builtins.cc. */ 1337 extern GTY(()) tree aarch64_fp16_type_node; 1338 extern GTY(()) tree aarch64_fp16_ptr_type_node; 1339 1340 /* This type is the user-visible __bf16, and a pointer to that type. Defined 1341 in aarch64-builtins.cc. */ 1342 extern GTY(()) tree aarch64_bf16_type_node; 1343 extern GTY(()) tree aarch64_bf16_ptr_type_node; 1344 1345 /* The generic unwind code in libgcc does not initialize the frame pointer. 1346 So in order to unwind a function using a frame pointer, the very first 1347 function that is unwound must save the frame pointer. That way the frame 1348 pointer is restored and its value is now valid - otherwise _Unwind_GetGR 1349 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ 1350 #define LIBGCC2_UNWIND_ATTRIBUTE \ 1351 __attribute__((optimize ("no-omit-frame-pointer"))) 1352 1353 #ifndef USED_FOR_TARGET 1354 extern poly_uint16 aarch64_sve_vg; 1355 1356 /* The number of bits and bytes in an SVE vector. */ 1357 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64)) 1358 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8)) 1359 1360 /* The number of bits and bytes in an SVE predicate. */ 1361 #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR 1362 #define BYTES_PER_SVE_PRED aarch64_sve_vg 1363 1364 /* The SVE mode for a vector of bytes. */ 1365 #define SVE_BYTE_MODE VNx16QImode 1366 1367 /* The maximum number of bytes in a fixed-size vector. This is 256 bytes 1368 (for -msve-vector-bits=2048) multiplied by the maximum number of 1369 vectors in a structure mode (4). 1370 1371 This limit must not be used for variable-size vectors, since 1372 VL-agnostic code must work with arbitary vector lengths. */ 1373 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4) 1374 #endif 1375 1376 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE) 1377 1378 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the 1379 outgoing arguments if stack clash protection is enabled. This is essential 1380 as the extra arg space allows us to skip a check in alloca. */ 1381 #undef STACK_DYNAMIC_OFFSET 1382 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1383 ((flag_stack_clash_protection \ 1384 && cfun->calls_alloca \ 1385 && known_lt (crtl->outgoing_args_size, \ 1386 STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \ 1387 ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \ 1388 STACK_BOUNDARY / BITS_PER_UNIT) \ 1389 : (crtl->outgoing_args_size + STACK_POINTER_OFFSET)) 1390 1391 #endif /* GCC_AARCH64_H */ 1392
Indexes created Thu Jul 16 00:26:27 UTC 2026