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      1 /* Copyright (C) 2011-2024 Free Software Foundation, Inc.
      2    Contributed by ARM Ltd.
      3 
      4    This file is part of GCC.
      5 
      6    GCC is free software; you can redistribute it and/or modify it
      7    under the terms of the GNU General Public License as published
      8    by the Free Software Foundation; either version 3, or (at your
      9    option) any later version.
     10 
     11    GCC is distributed in the hope that it will be useful, but WITHOUT
     12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     14    License for more details.
     15 
     16    You should have received a copy of the GNU General Public License
     17    along with GCC; see the file COPYING3.  If not see
     18    <http://www.gnu.org/licenses/>.  */
     19 
     20 /* Definitions for option handling for AArch64.  */
     21 
     22 #ifndef GCC_AARCH64_OPTS_H
     23 #define GCC_AARCH64_OPTS_H
     24 
     25 #ifndef USED_FOR_TARGET
     26 typedef uint64_t aarch64_feature_flags;
     27 #endif
     28 
     29 /* The various cores that implement AArch64.  */
     30 enum aarch64_processor
     31 {
     32 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
     33   INTERNAL_IDENT,
     34 #include "aarch64-cores.def"
     35   /* Used to mark the end of the processor table.  */
     36   aarch64_none
     37 };
     38 
     39 enum aarch64_arch
     40 {
     41 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
     42   AARCH64_ARCH_##ARCH_IDENT,
     43 #include "aarch64-arches.def"
     44   aarch64_no_arch
     45 };
     46 
     47 /* TLS types.  */
     48 enum aarch64_tls_type {
     49   TLS_TRADITIONAL,
     50   TLS_DESCRIPTORS
     51 };
     52 
     53 /* The code model defines the address generation strategy.
     54    Most have a PIC and non-PIC variant.  */
     55 enum aarch64_code_model {
     56   /* Static code and data fit within a 1MB region.
     57      Not fully implemented, mostly treated as SMALL.  */
     58   AARCH64_CMODEL_TINY,
     59   /* Static code, data and GOT/PLT fit within a 1MB region.
     60      Not fully implemented, mostly treated as SMALL_PIC.  */
     61   AARCH64_CMODEL_TINY_PIC,
     62   /* Static code and data fit within a 4GB region.
     63      The default non-PIC code model.  */
     64   AARCH64_CMODEL_SMALL,
     65   /* Static code, data and GOT/PLT fit within a 4GB region.
     66      The default PIC code model.  */
     67   AARCH64_CMODEL_SMALL_PIC,
     68   /* -fpic for small memory model.
     69      GOT size to 28KiB (4K*8-4K) or 3580 entries.  */
     70   AARCH64_CMODEL_SMALL_SPIC,
     71   /* No assumptions about addresses of code and data.
     72      The PIC variant is not yet implemented.  */
     73   AARCH64_CMODEL_LARGE
     74 };
     75 
     76 /* The register to use as a thread pointer for TLS accesses.
     77    tpidr_el0 by default, but can be changed through the -mtp option.  */
     78 enum aarch64_tp_reg {
     79   AARCH64_TPIDR_EL0 = 0,
     80   AARCH64_TPIDR_EL1 = 1,
     81   AARCH64_TPIDR_EL2 = 2,
     82   AARCH64_TPIDR_EL3 = 3,
     83   AARCH64_TPIDRRO_EL0 = 4
     84 };
     85 
     86 /* SVE vector register sizes.  */
     87 enum aarch64_sve_vector_bits_enum {
     88   SVE_SCALABLE,
     89   SVE_NOT_IMPLEMENTED = SVE_SCALABLE,
     90   SVE_128 = 128,
     91   SVE_256 = 256,
     92   SVE_512 = 512,
     93   SVE_1024 = 1024,
     94   SVE_2048 = 2048
     95 };
     96 
     97 /* Where to get the canary for the stack protector.  */
     98 enum stack_protector_guard {
     99   SSP_SYSREG,			/* per-thread canary in special system register */
    100   SSP_GLOBAL			/* global canary */
    101 };
    102 
    103 /* The key type that -msign-return-address should use.  */
    104 enum aarch64_key_type {
    105   AARCH64_KEY_A,
    106   AARCH64_KEY_B
    107 };
    108 
    109 /* An enum specifying how to handle load and store pairs using
    110    a fine-grained policy:
    111    - LDP_STP_POLICY_DEFAULT: Use the policy defined in the tuning structure.
    112    - LDP_STP_POLICY_ALIGNED: Emit ldp/stp if the source pointer is aligned
    113    to at least double the alignment of the type.
    114    - LDP_STP_POLICY_ALWAYS: Emit ldp/stp regardless of alignment.
    115    - LDP_STP_POLICY_NEVER: Do not emit ldp/stp.  */
    116 enum aarch64_ldp_stp_policy {
    117   AARCH64_LDP_STP_POLICY_DEFAULT,
    118   AARCH64_LDP_STP_POLICY_ALIGNED,
    119   AARCH64_LDP_STP_POLICY_ALWAYS,
    120   AARCH64_LDP_STP_POLICY_NEVER
    121 };
    122 
    123 /* An enum specifying when the early-ra pass should be run:
    124    - AARCH64_EARLY_RA_ALL: for all functions
    125    - AARCH64_EARLY_RA_STRIDED: for functions that have access to strided
    126      multi-register instructions
    127    - AARCH64_EARLY_RA_NONE: for no functions.  */
    128 enum aarch64_early_ra_scope {
    129   AARCH64_EARLY_RA_ALL,
    130   AARCH64_EARLY_RA_STRIDED,
    131   AARCH64_EARLY_RA_NONE
    132 };
    133 
    134 #endif
    135