1 /* $NetBSD: spr.h,v 1.6 2026/06/13 19:45:50 rkujawa Exp $ */ 2 3 #ifndef _POWERPC_IBM4XX_SPR_H_ 4 #define _POWERPC_IBM4XX_SPR_H_ 5 6 #ifdef _KERNEL_OPT 7 #include "opt_ppcarch.h" 8 #endif 9 10 /* 11 * IBM4xx Special Purpose Register declarations. 12 * 13 * The first column in the comments indicates which PowerPC architectures the 14 * SPR is valid on - E for BookE series, 4 for 4xx series, 15 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series. 16 */ 17 18 #define SPR_44XPID 0x030 /* E4.. 440 Process ID */ 19 #define SPR_USPRG0 0x100 /* E4.. User SPR General 0 */ 20 #define IBM403 0x0020 21 #define IBM401A1 0x0021 22 #define IBM401B2 0x0022 23 #define IBM401C2 0x0023 24 #define IBM401D2 0x0024 25 #define IBM401E2 0x0025 26 #define IBM401F2 0x0026 27 #define IBM401G2 0x0027 28 #define AMCC405EX 0x1291 29 #define XILVIRTEX 0x2001 30 #define IBM405GP 0x4011 31 #define IBMSTB03 0x4013 32 #define IBMSTB04 0x4081 33 #define IBM405GS3 0x40b1 34 #define IBM405H 0x4141 35 #define IBM405L 0x4161 36 #define IBM405LP 0x41f1 37 #define IBM405GPR 0x5091 38 #define IBM405EP 0x5121 39 #define IBMSTB25 0x5151 40 41 /* PVRs for different IBM CPUs */ 42 #define PVR_401A1 0x00210000 43 #define PVR_401B2 0x00220000 44 #define PVR_401C2 0x00230000 45 #define PVR_401D2 0x00240000 46 #define PVR_401E2 0x00250000 47 #define PVR_401F2 0x00260000 48 #define PVR_401G2 0x00270000 49 50 #define PVR_403GA 0x00200000 /* XXX no MMU */ 51 #define PVR_403GB 0x00200100 /* XXX no MMU */ 52 #define PVR_403GC 0x00200200 53 #define PVR_403GCX 0x00201400 54 55 #define PVR_405GP 0x40110000 56 #define PVR_405GP_PASS1 0x40110000 /* RevA */ 57 #define PVR_405GP_PASS2 0x40110040 /* RevB */ 58 #define PVR_405GP_PASS2_1 0x40110082 /* RevC */ 59 #define PVR_405GP_PASS3 0x401100c4 /* RevD */ 60 #define PVR_405GPR 0x50910000 61 #define PVR_405GPR_REVB 0x50910951 62 63 #define PVR_405D5X1 0x20010000 /* Virtex II Pro */ 64 #define PVR_405D5X2 0x20011000 /* Virtex 4 FX */ 65 66 #define PVR_405EX 0x12910000 67 68 #define AMCC460EX 0x1302 69 #define PVR_460EX 0x13020000 70 71 #define SPR_ZPR 0x3b0 /* .4.. Zone Protection Register */ 72 #ifdef PPC_IBM440 73 /* 74 * The 440/460 family is Book E really, but it fits better here than into 75 * our existing Book E support which is e500-centric... 76 */ 77 #define SPR_PID SPR_44XPID /* E... Process ID */ 78 #define SPR_DECAR 0x036 /* E... Decrementer Auto-Reload */ 79 #define SPR_CSRR0 0x03a /* E... Critical Save/Restore 0 */ 80 #define SPR_CSRR1 0x03b /* E... Critical Save/Restore 1 */ 81 #define SPR_DEAR 0x03d /* E... Data Exception Address */ 82 #define SPR_ESR 0x03e /* E... Exception Syndrome */ 83 #define SPR_IVPR 0x03f /* E... Interrupt Vector Prefix */ 84 #define SPR_IVOR0 0x190 /* E... Critical input */ 85 #define SPR_IVOR1 0x191 /* E... Machine check */ 86 #define SPR_IVOR2 0x192 /* E... Data storage */ 87 #define SPR_IVOR3 0x193 /* E... Instruction storage */ 88 #define SPR_IVOR4 0x194 /* E... External input */ 89 #define SPR_IVOR5 0x195 /* E... Alignment */ 90 #define SPR_IVOR6 0x196 /* E... Program */ 91 #define SPR_IVOR7 0x197 /* E... FP unavailable */ 92 #define SPR_IVOR8 0x198 /* E... System call */ 93 #define SPR_IVOR9 0x199 /* E... AP unavailable */ 94 #define SPR_IVOR10 0x19a /* E... Decrementer */ 95 #define SPR_IVOR11 0x19b /* E... Fixed-interval timer */ 96 #define SPR_IVOR12 0x19c /* E... Watchdog timer */ 97 #define SPR_IVOR13 0x19d /* E... Data TLB error */ 98 #define SPR_IVOR14 0x19e /* E... Instruction TLB error */ 99 #define SPR_IVOR15 0x19f /* E... Debug */ 100 #define SPR_MCSRR0 0x23a /* E... Machine check SRR0 (440x6/460) */ 101 #define SPR_MCSRR1 0x23b /* E... Machine check SRR1 (440x6/460) */ 102 #define SPR_MCSR 0x23c /* E... Machine check Syndrome (440x6/460) */ 103 #define MCSR_MCS 0x80000000 /* Machine check summary */ 104 #define MCSR_IB 0x40000000 /* Instruction PLB error */ 105 #define MCSR_DRB 0x20000000 /* Data read PLB error */ 106 #define MCSR_DWB 0x10000000 /* Data write PLB error */ 107 #define MCSR_TLBP 0x08000000 /* TLB parity error */ 108 #define MCSR_ICP 0x04000000 /* I-cache parity error */ 109 #define MCSR_DCSP 0x02000000 /* D-cache search parity error */ 110 #define MCSR_DCFP 0x01000000 /* D-cache flush parity error */ 111 #define MCSR_IMPE 0x00800000 /* Imprecise machine check */ 112 #else 113 #define SPR_PID 0x3b1 /* .4.. Process ID */ 114 #endif /* PPC_IBM440 */ 115 #define SPR_MMUCR 0x3b2 /* .4.. MMU Control Register */ 116 #define MMUCR_SW0A 0x01000000 /* Store WithOut Allocate */ 117 #define MMUCR_U1TE 0x00400000 /* U1 Transient Enable */ 118 #define MMUCR_U2SWOAE 0x00200000 /* U2 SWOA Enab */ 119 #define MMUCR_DULXE 0x00080000 /* Data Cache Unlock Exc. Ena. */ 120 #define MMUCR_IULXE 0x00040000 /* Inst. Cache Unlock Exc. Ena. */ 121 #define MMUCR_STS 0x00010000 /* Search Translation Space [TS] */ 122 #define MMUCR_STID 0x000000ff /* Search Translation ID */ 123 #define SPR_CCR0 0x3b3 /* .4.. Core Configuration Register 0 */ 124 #define SPR_IAC3 0x3b4 /* .4.. Instruction Address Compare 3 */ 125 #define SPR_IAC4 0x3b5 /* .4.. Instruction Address Compare 4 */ 126 #define SPR_DVC1 0x3b6 /* .4.. Data Value Compare 1 */ 127 #define SPR_DVC2 0x3b7 /* .4.. Data Value Compare 2 */ 128 #define SPR_SGR 0x3b9 /* .4.. Storage Guarded Register */ 129 #define SPR_DCWR 0x3ba /* .4.. Data Cache Write-through Register */ 130 #define SPR_SLER 0x3bb /* .4.. Storage Little Endian Register */ 131 #define SPR_SU0R 0x3bc /* .4.. Storage User-defined 0 Register */ 132 #define SPR_DBCR1 0x3bd /* .4.. Debug Control Register 1 */ 133 #define SPR_ICDBDR 0x3d3 /* .4.. Instruction Cache Debug Data Register */ 134 #ifndef PPC_IBM440 135 #define SPR_ESR 0x3d4 /* .4.. Exception Syndrome Register */ 136 #endif 137 #define ESR_MCI 0x80000000 /* 0: Machine check - instruction */ 138 #define ESR_PIL 0x08000000 /* 4: Program interrupt - illegal */ 139 #define ESR_PPR 0x04000000 /* 5: Program interrupt - privileged */ 140 #define ESR_PTR 0x02000000 /* 6: Program interrupt - trap */ 141 #define ESR_DST 0x00800000 /* 8: Data storage interrupt - store fault */ 142 #define ESR_DIZ 0x00800000 /* 8: Data/instruction storage interrupt - zone fault */ 143 #define ESR_ST 0x00800000 /* 8: Store operation */ 144 #define ESR_DLK 0x00200000 /* 10: dcache exception */ 145 #define ESR_ILK 0x00100000 /* 11: icache exception */ 146 #define ESR_BO 0x00020000 /* 14: Byte ordering exception */ 147 #define ESR_U0F 0x00008000 /* 16: Data storage interrupt - U0 fault */ 148 #define ESR_SPE 0x00000080 /* 24: SPE exception */ 149 #ifndef PPC_IBM440 150 #define SPR_DEAR 0x3d5 /* .4.. Data Error Address Register */ 151 #endif 152 #define SPR_EVPR 0x3d6 /* .4.. Exception Vector Prefix Register */ 153 #ifdef PPC_IBM440 154 #define SPR_TSR 0x150 /* E... Timer Status Register */ 155 #else 156 #define SPR_TSR 0x3d8 /* .4.. Timer Status Register */ 157 #endif 158 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 159 #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 160 #define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 161 #define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ 162 #define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 163 #define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 164 #define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 165 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 166 #define TSR_DIS TSR_PIS /* E... Decrementer Intr Status */ 167 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 168 #ifdef PPC_IBM440 169 #define SPR_TCR 0x154 /* E... Timer Control Register */ 170 #else 171 #define SPR_TCR 0x3da /* .4.. Timer Control Register */ 172 #endif 173 #define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 174 #ifdef PPC_IBM440 175 /* 176 * 440/460EX watchdog 177 */ 178 #define TCR_WP_2_21 0x00000000 /* 0b00: 2**21 clocks */ 179 #define TCR_WP_2_25 0x40000000 /* 0b01: 2**25 clocks */ 180 #define TCR_WP_2_29 0x80000000 /* 0b10: 2**29 clocks */ 181 #define TCR_WP_2_33 0xc0000000 /* 0b11: 2**33 clocks */ 182 #else 183 #define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 184 #define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 185 #define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 186 #define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 187 #endif 188 #define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 189 #define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 190 #define TCR_WRC_CORE 0x10000000 /* Core reset */ 191 #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 192 #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 193 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 194 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 195 #define TCR_DIE TCR_PIE /* E... Decrementer Intr Enable */ 196 #define TCR_FP_MASK 0x03000000 /* FIT Period */ 197 #ifdef PPC_IBM440 198 /* 199 * 440/460EX FIT periods 200 */ 201 #define TCR_FP_2_13 0x00000000 /* 0b00: TBL19, 2**13 clocks */ 202 #define TCR_FP_2_17 0x01000000 /* 0b01: TBL15, 2**17 clocks */ 203 #define TCR_FP_2_21 0x02000000 /* 0b10: TBL11, 2**21 clocks */ 204 #define TCR_FP_2_25 0x03000000 /* 0b11: TBL7, 2**25 clocks */ 205 #else 206 #define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 207 #define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 208 #define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 209 #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 210 #endif 211 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 212 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 213 #ifndef PPC_IBM440 214 #define SPR_PIT 0x3db /* .4.. Programmable Interval Timer */ 215 #define SPR_SRR2 0x3de /* .4.. Save/Restore Register 2 */ 216 #define SPR_SRR3 0x3df /* .4.. Save/Restore Register 3 */ 217 #endif 218 #ifdef PPC_IBM440 219 #define SPR_DBSR 0x130 /* E... Debug Status Register */ 220 #else 221 #define SPR_DBSR 0x3f0 /* .4.. Debug Status Register */ 222 #endif 223 #define DBSR_IC 0x80000000 /* Instruction completion debug event */ 224 #define DBSR_IDE 0x80000000 /* Imprecise debug event */ 225 #define DBSR_BT 0x40000000 /* Branch Taken debug event */ 226 #define DBSR_EDE 0x20000000 /* Exception debug event */ 227 #define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 228 #define DBSR_UDE 0x08000000 /* Unconditional debug event */ 229 #define DBSR_IA1 0x04000000 /* IAC1 debug event */ 230 #define DBSR_IA2 0x02000000 /* IAC2 debug event */ 231 #define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ 232 #define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ 233 #define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ 234 #define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ 235 #define DBSR_IA3 0x00080000 /* IAC3 debug event */ 236 #define DBSR_IA4 0x00040000 /* IAC4 debug event */ 237 #define DBSR_MRR 0x00000300 /* Most recent reset */ 238 #ifdef PPC_IBM440 239 #define SPR_DBCR0 0x134 /* E... Debug Control Register 0 */ 240 #else 241 #define SPR_DBCR0 0x3f2 /* .4.. Debug Control Register 0 */ 242 #endif 243 #define DBCR0_EDM 0x80000000 /* 0: External Debug Mode */ 244 #define DBCR0_IDM 0x40000000 /* 1: Internal Debug Mode */ 245 #define DBCR0_RST_MASK 0x30000000 /* 2..3: ReSeT */ 246 #define DBCR0_RST_NONE 0x00000000 /* No action */ 247 #define DBCR0_RST_CORE 0x10000000 /* Core reset */ 248 #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 249 #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 250 #define DBCR0_IC 0x08000000 /* 4: Instruction Completion debug event */ 251 #define DBCR0_BT 0x04000000 /* 5: Branch Taken debug event */ 252 #define DBCR0_EDE 0x02000000 /* 6: Exception Debug Event */ 253 #define DBCR0_TDE 0x01000000 /* 7: Trap Debug Event */ 254 #define DBCR0_IA1 0x00800000 /* 8: IAC (Instruction Address Compare) 1 debug event */ 255 #define DBCR0_IA2 0x00400000 /* 9: IAC 2 debug event */ 256 #define DBCR0_IA12 0x00200000 /* 10: Instruction Address Range Compare 1-2 */ 257 #define DBCR0_IA12X 0x00100000 /* 11: IA12 eXclusive */ 258 #define DBCR0_IA3 0x00080000 /* 12: IAC 3 debug event */ 259 #define DBCR0_IA4 0x00040000 /* 13: IAC 4 debug event */ 260 #define DBCR0_IA34 0x00020000 /* 14: Instruction Address Range Compare 3-4 */ 261 #define DBCR0_IA34X 0x00010000 /* 15: IA34 eXclusive */ 262 #define DBCR0_IA12T 0x00008000 /* 16: Instruction Address Range Compare 1-2 range Toggle */ 263 #define DBCR0_IA34T 0x00004000 /* 17: Instruction Address Range Compare 3-4 range Toggle */ 264 #define DBCR0_FT 0x00000001 /* 31: Freeze Timers on debug event */ 265 #define SPR_IAC1 0x3f4 /* .4.. Instruction Address Compare 1 */ 266 #define SPR_IAC2 0x3f5 /* .4.. Instruction Address Compare 2 */ 267 #define SPR_DAC1 0x3f6 /* .4.. Data Address Compare 1 */ 268 #define SPR_DAC2 0x3f7 /* .4.. Data Address Compare 2 */ 269 #define SPR_DCCR 0x3fa /* .4.. Data Cache Cachability Register */ 270 #define SPR_ICCR 0x3fb /* .4.. Instruction Cache Cachability Register */ 271 272 /* 273 * XXXclang 274 * clang cannot correctly assemble m[ft]pid for ibm4xx. 275 * Yes, this is ugly, but may not be ugliest... 276 */ 277 #define MFPID(reg) "mfspr "#reg","___STRING(SPR_PID)";" 278 #define MTPID(reg) "mtspr "___STRING(SPR_PID)","#reg";" 279 280 #define MFMMUCR(reg) "mfspr "#reg","___STRING(SPR_MMUCR)";" 281 #define MTMMUCR(reg) "mtspr "___STRING(SPR_MMUCR)","#reg";" 282 283 #endif /* !_POWERPC_IBM4XX_SPR_H_ */ 284
Indexes created Tue Jul 07 00:25:39 UTC 2026