1 /* $NetBSD: gcscpcibreg.h,v 1.1 2011/08/27 12:47:49 bouyer Exp $ */ 2 /* $OpenBSD: glxpcib.c,v 1.6 2007/11/17 17:02:47 mbalmer Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Marc Balmer <mbalmer (at) openbsd.org> 6 * Copyright (c) 2007 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 18 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 19 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Register definitions for the AMD CS5535/CS5536 Companion Device. 24 */ 25 26 #ifndef _IC_GCSCPCIBREG_H_ 27 #define _IC_GCSCPCIBREG_H_ 28 29 #define AMD553X_REV 0x51400017 30 #define AMD553X_REV_MASK 0xff 31 #define AMD553X_TMC 0x51400050 32 33 /* Multi-Functional General Purpose Timer */ 34 #define MSR_LBAR_MFGPT 0x5140000d 35 #define AMD553X_MFGPT_MAX 6 /* 6 timers for wdog */ 36 #define AMD553X_MFGPT_REGOFFSET 0x8 37 #define AMD553X_MFGPTX_CMP1(x) (0x00000000 + (AMD553X_MFGPT_REGOFFSET * (x))) 38 #define AMD553X_MFGPTX_CMP2(x) (0x00000002 + (AMD553X_MFGPT_REGOFFSET * (x))) 39 #define AMD553X_MFGPTX_CNT(x) (0x00000004 + (AMD553X_MFGPT_REGOFFSET * (x))) 40 #define AMD553X_MFGPTX_SETUP(x) (0x00000006 + (AMD553X_MFGPT_REGOFFSET * (x))) 41 #define AMD553X_MFGPT_DIV_MASK 0x000f /* div = 1 << mask */ 42 #define AMD553X_MFGPT_DIV_1 0x0000 43 #define AMD553X_MFGPT_DIV_2 0x0001 44 #define AMD553X_MFGPT_DIV_4 0x0002 45 #define AMD553X_MFGPT_DIV_8 0x0003 46 #define AMD553X_MFGPT_DIV_16 0x0004 47 #define AMD553X_MFGPT_DIV_32 0x0005 48 #define AMD553X_MFGPT_DIV_64 0x0006 49 #define AMD553X_MFGPT_DIV_128 0x0007 50 #define AMD553X_MFGPT_DIV_256 0x0008 51 #define AMD553X_MFGPT_DIV_512 0x0009 52 #define AMD553X_MFGPT_DIV_1K 0x000a 53 #define AMD553X_MFGPT_DIV_2K 0x000b 54 #define AMD553X_MFGPT_DIV_4K 0x000c 55 #define AMD553X_MFGPT_DIV_8K 0x000d 56 #define AMD553X_MFGPT_DIV_16K 0x000e 57 #define AMD553X_MFGPT_DIV_32K 0x000f 58 #define AMD553X_MFGPT_CLKSEL 0x0010 59 #define AMD553X_MFGPT_REV_EN 0x0020 60 #define AMD553X_MFGPT_CMP1DIS 0x0000 61 #define AMD553X_MFGPT_CMP1EQ 0x0040 62 #define AMD553X_MFGPT_CMP1GE 0x0080 63 #define AMD553X_MFGPT_CMP1EV 0x00c0 64 #define AMD553X_MFGPT_CMP2DIS 0x0000 65 #define AMD553X_MFGPT_CMP2EQ 0x0100 66 #define AMD553X_MFGPT_CMP2GE 0x0200 67 #define AMD553X_MFGPT_CMP2EV 0x0300 68 #define AMD553X_MFGPT_STOP_EN 0x0800 69 #define AMD553X_MFGPT_SET 0x1000 70 #define AMD553X_MFGPT_CMP1 0x2000 71 #define AMD553X_MFGPT_CMP2 0x4000 72 #define AMD553X_MFGPT_CNT_EN 0x8000 73 #define AMD553X_MFGPT_IRQ 0x51400028 74 #define AMD553X_MFGPT0_C1_IRQM 0x00000001 75 #define AMD553X_MFGPT1_C1_IRQM 0x00000002 76 #define AMD553X_MFGPT2_C1_IRQM 0x00000004 77 #define AMD553X_MFGPT3_C1_IRQM 0x00000008 78 #define AMD553X_MFGPT4_C1_IRQM 0x00000010 79 #define AMD553X_MFGPT5_C1_IRQM 0x00000020 80 #define AMD553X_MFGPT6_C1_IRQM 0x00000040 81 #define AMD553X_MFGPT7_C1_IRQM 0x00000080 82 #define AMD553X_MFGPT0_C2_IRQM 0x00000100 83 #define AMD553X_MFGPT1_C2_IRQM 0x00000200 84 #define AMD553X_MFGPT2_C2_IRQM 0x00000400 85 #define AMD553X_MFGPT3_C2_IRQM 0x00000800 86 #define AMD553X_MFGPT4_C2_IRQM 0x00001000 87 #define AMD553X_MFGPT5_C2_IRQM 0x00002000 88 #define AMD553X_MFGPT6_C2_IRQM 0x00004000 89 #define AMD553X_MFGPT7_C2_IRQM 0x00008000 90 #define AMD553X_MFGPT_NR 0x51400029 /* NMI and Reset mask */ 91 #define AMD553X_MFGPT0_C1_NMIM 0x00000001 92 #define AMD553X_MFGPT1_C1_NMIM 0x00000002 93 #define AMD553X_MFGPT2_C1_NMIM 0x00000004 94 #define AMD553X_MFGPT3_C1_NMIM 0x00000008 95 #define AMD553X_MFGPT4_C1_NMIM 0x00000010 96 #define AMD553X_MFGPT5_C1_NMIM 0x00000020 97 #define AMD553X_MFGPT6_C1_NMIM 0x00000040 98 #define AMD553X_MFGPT7_C1_NMIM 0x00000080 99 #define AMD553X_MFGPT0_C2_NMIM 0x00000100 100 #define AMD553X_MFGPT1_C2_NMIM 0x00000200 101 #define AMD553X_MFGPT2_C2_NMIM 0x00000400 102 #define AMD553X_MFGPT3_C2_NMIM 0x00000800 103 #define AMD553X_MFGPT4_C2_NMIM 0x00001000 104 #define AMD553X_MFGPT5_C2_NMIM 0x00002000 105 #define AMD553X_MFGPT6_C2_NMIM 0x00004000 106 #define AMD553X_MFGPT7_C2_NMIM 0x00008000 107 #define AMD553X_NMI_LEG 0x00010000 108 #define AMD553X_MFGPT0_C2_RSTEN 0x01000000 109 #define AMD553X_MFGPT1_C2_RSTEN 0x02000000 110 #define AMD553X_MFGPT2_C2_RSTEN 0x04000000 111 #define AMD553X_MFGPT3_C2_RSTEN 0x08000000 112 #define AMD553X_MFGPT4_C2_RSTEN 0x10000000 113 #define AMD553X_MFGPT5_C2_RSTEN 0x20000000 114 #define AMD553X_MFGPT_SETUP 0x5140002b 115 116 /* SMB / IIC */ 117 #define MSR_LBAR_SMB 0x5140000b 118 119 /* GPIO */ 120 #define MSR_LBAR_GPIO 0x5140000c 121 #define AMD553X_GPIO_NPINS 32 122 #define AMD553X_GPIOH_OFFSET 0x80 /* high bank register offset */ 123 #define AMD553X_GPIO_OUT_VAL 0x00 /* output value */ 124 #define AMD553X_GPIO_OUT_EN 0x04 /* output enable */ 125 #define AMD553X_GPIO_OD_EN 0x08 /* open-drain enable */ 126 #define AMD553X_GPIO_OUT_INVRT_EN 0x0c /* invert output enable*/ 127 #define AMD553X_GPIO_PU_EN 0x18 /* pull-up enable */ 128 #define AMD553X_GPIO_PD_EN 0x1c /* pull-down enable */ 129 #define AMD553X_GPIO_IN_EN 0x20 /* input enable */ 130 #define AMD553X_GPIO_IN_INVRT_EN 0x24 /* invert input */ 131 #define AMD553X_GPIO_IN_FLTR_EN 0x28 /* filter enable */ 132 #define AMD553X_GPIO_IN_EVNTCNT_EN 0x2c /* event counter enable */ 133 #define AMD553X_GPIO_READ_BACK 0x30 /* read back value */ 134 #define AMD553X_GPIO_EVNT_EN 0x38 /* event enable */ 135 #define AMD553X_GPIO_LOCK_EN 0x3c /* lock enable */ 136 #define AMD553X_GPIO_IN_PE_EN 0x40 /* input positive edge enable */ 137 #define AMD553X_GPIO_IN_NE_EN 0x44 /* input negative edge enable */ 138 #define AMD553X_GPIO_IN_NE_STS 0x48 /* input negative edge status */ 139 #define AMD553X_GPIO_IN_PE_STS 0x4c /* input positive edge status */ 140 141 #endif /* _IC_GCSCPCIBREG_H_ */ 142
Indexes created Sat Sep 20 22:09:52 GMT 2025