1 /* $NetBSD: amdgpu_drm.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $ */ 2 3 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 4 * 5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 6 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 7 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the "Software"), 12 * to deal in the Software without restriction, including without limitation 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 14 * and/or sell copies of the Software, and to permit persons to whom the 15 * Software is furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 26 * OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Kevin E. Martin <martin (at) valinux.com> 30 * Gareth Hughes <gareth (at) valinux.com> 31 * Keith Whitwell <keith (at) tungstengraphics.com> 32 */ 33 34 #ifndef __AMDGPU_DRM_H__ 35 #define __AMDGPU_DRM_H__ 36 37 #include "drm.h" 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif 42 43 #define DRM_AMDGPU_GEM_CREATE 0x00 44 #define DRM_AMDGPU_GEM_MMAP 0x01 45 #define DRM_AMDGPU_CTX 0x02 46 #define DRM_AMDGPU_BO_LIST 0x03 47 #define DRM_AMDGPU_CS 0x04 48 #define DRM_AMDGPU_INFO 0x05 49 #define DRM_AMDGPU_GEM_METADATA 0x06 50 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 51 #define DRM_AMDGPU_GEM_VA 0x08 52 #define DRM_AMDGPU_WAIT_CS 0x09 53 #define DRM_AMDGPU_GEM_OP 0x10 54 #define DRM_AMDGPU_GEM_USERPTR 0x11 55 #define DRM_AMDGPU_WAIT_FENCES 0x12 56 #define DRM_AMDGPU_VM 0x13 57 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 58 #define DRM_AMDGPU_SCHED 0x15 59 60 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 61 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 62 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 63 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 64 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 65 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 66 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 67 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 68 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 69 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 70 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 71 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 72 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 73 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 74 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 75 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 76 77 /** 78 * DOC: memory domains 79 * 80 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 81 * Memory in this pool could be swapped out to disk if there is pressure. 82 * 83 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 84 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 85 * pages of system memory, allows GPU access system memory in a linezrized 86 * fashion. 87 * 88 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 89 * carved out by the BIOS. 90 * 91 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 92 * across shader threads. 93 * 94 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 95 * execution of all the waves on a device. 96 * 97 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 98 * for appending data. 99 */ 100 #define AMDGPU_GEM_DOMAIN_CPU 0x1 101 #define AMDGPU_GEM_DOMAIN_GTT 0x2 102 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 103 #define AMDGPU_GEM_DOMAIN_GDS 0x8 104 #define AMDGPU_GEM_DOMAIN_GWS 0x10 105 #define AMDGPU_GEM_DOMAIN_OA 0x20 106 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 107 AMDGPU_GEM_DOMAIN_GTT | \ 108 AMDGPU_GEM_DOMAIN_VRAM | \ 109 AMDGPU_GEM_DOMAIN_GDS | \ 110 AMDGPU_GEM_DOMAIN_GWS | \ 111 AMDGPU_GEM_DOMAIN_OA) 112 113 /* Flag that CPU access will be required for the case of VRAM domain */ 114 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 115 /* Flag that CPU access will not work, this VRAM domain is invisible */ 116 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 117 /* Flag that USWC attributes should be used for GTT */ 118 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 119 /* Flag that the memory should be in VRAM and cleared */ 120 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 121 /* Flag that create shadow bo(GTT) while allocating vram bo */ 122 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 123 /* Flag that allocating the BO should use linear VRAM */ 124 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 125 /* Flag that BO is always valid in this VM */ 126 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 127 /* Flag that BO sharing will be explicitly synchronized */ 128 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 129 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 130 * for the second page onward should be set to NC. 131 */ 132 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 133 /* Flag that BO may contain sensitive data that must be wiped before 134 * releasing the memory 135 */ 136 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 137 138 struct drm_amdgpu_gem_create_in { 139 /** the requested memory size */ 140 __u64 bo_size; 141 /** physical start_addr alignment in bytes for some HW requirements */ 142 __u64 alignment; 143 /** the requested memory domains */ 144 __u64 domains; 145 /** allocation flags */ 146 __u64 domain_flags; 147 }; 148 149 struct drm_amdgpu_gem_create_out { 150 /** returned GEM object handle */ 151 __u32 handle; 152 __u32 _pad; 153 }; 154 155 union drm_amdgpu_gem_create { 156 struct drm_amdgpu_gem_create_in in; 157 struct drm_amdgpu_gem_create_out out; 158 }; 159 160 /** Opcode to create new residency list. */ 161 #define AMDGPU_BO_LIST_OP_CREATE 0 162 /** Opcode to destroy previously created residency list */ 163 #define AMDGPU_BO_LIST_OP_DESTROY 1 164 /** Opcode to update resource information in the list */ 165 #define AMDGPU_BO_LIST_OP_UPDATE 2 166 167 struct drm_amdgpu_bo_list_in { 168 /** Type of operation */ 169 __u32 operation; 170 /** Handle of list or 0 if we want to create one */ 171 __u32 list_handle; 172 /** Number of BOs in list */ 173 __u32 bo_number; 174 /** Size of each element describing BO */ 175 __u32 bo_info_size; 176 /** Pointer to array describing BOs */ 177 __u64 bo_info_ptr; 178 }; 179 180 struct drm_amdgpu_bo_list_entry { 181 /** Handle of BO */ 182 __u32 bo_handle; 183 /** New (if specified) BO priority to be used during migration */ 184 __u32 bo_priority; 185 }; 186 187 struct drm_amdgpu_bo_list_out { 188 /** Handle of resource list */ 189 __u32 list_handle; 190 __u32 _pad; 191 }; 192 193 union drm_amdgpu_bo_list { 194 struct drm_amdgpu_bo_list_in in; 195 struct drm_amdgpu_bo_list_out out; 196 }; 197 198 /* context related */ 199 #define AMDGPU_CTX_OP_ALLOC_CTX 1 200 #define AMDGPU_CTX_OP_FREE_CTX 2 201 #define AMDGPU_CTX_OP_QUERY_STATE 3 202 #define AMDGPU_CTX_OP_QUERY_STATE2 4 203 204 /* GPU reset status */ 205 #define AMDGPU_CTX_NO_RESET 0 206 /* this the context caused it */ 207 #define AMDGPU_CTX_GUILTY_RESET 1 208 /* some other context caused it */ 209 #define AMDGPU_CTX_INNOCENT_RESET 2 210 /* unknown cause */ 211 #define AMDGPU_CTX_UNKNOWN_RESET 3 212 213 /* indicate gpu reset occured after ctx created */ 214 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 215 /* indicate vram lost occured after ctx created */ 216 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 217 /* indicate some job from this context once cause gpu hang */ 218 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 219 /* indicate some errors are detected by RAS */ 220 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 221 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 222 223 /* Context priority level */ 224 #define AMDGPU_CTX_PRIORITY_UNSET -2048 225 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 226 #define AMDGPU_CTX_PRIORITY_LOW -512 227 #define AMDGPU_CTX_PRIORITY_NORMAL 0 228 /* 229 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 230 * CAP_SYS_NICE or DRM_MASTER 231 */ 232 #define AMDGPU_CTX_PRIORITY_HIGH 512 233 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 234 235 struct drm_amdgpu_ctx_in { 236 /** AMDGPU_CTX_OP_* */ 237 __u32 op; 238 /** For future use, no flags defined so far */ 239 __u32 flags; 240 __u32 ctx_id; 241 /** AMDGPU_CTX_PRIORITY_* */ 242 __s32 priority; 243 }; 244 245 union drm_amdgpu_ctx_out { 246 struct { 247 __u32 ctx_id; 248 __u32 _pad; 249 } alloc; 250 251 struct { 252 /** For future use, no flags defined so far */ 253 __u64 flags; 254 /** Number of resets caused by this context so far. */ 255 __u32 hangs; 256 /** Reset status since the last call of the ioctl. */ 257 __u32 reset_status; 258 } state; 259 }; 260 261 union drm_amdgpu_ctx { 262 struct drm_amdgpu_ctx_in in; 263 union drm_amdgpu_ctx_out out; 264 }; 265 266 /* vm ioctl */ 267 #define AMDGPU_VM_OP_RESERVE_VMID 1 268 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 269 270 struct drm_amdgpu_vm_in { 271 /** AMDGPU_VM_OP_* */ 272 __u32 op; 273 __u32 flags; 274 }; 275 276 struct drm_amdgpu_vm_out { 277 /** For future use, no flags defined so far */ 278 __u64 flags; 279 }; 280 281 union drm_amdgpu_vm { 282 struct drm_amdgpu_vm_in in; 283 struct drm_amdgpu_vm_out out; 284 }; 285 286 /* sched ioctl */ 287 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 288 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 289 290 struct drm_amdgpu_sched_in { 291 /* AMDGPU_SCHED_OP_* */ 292 __u32 op; 293 __u32 fd; 294 /** AMDGPU_CTX_PRIORITY_* */ 295 __s32 priority; 296 __u32 ctx_id; 297 }; 298 299 union drm_amdgpu_sched { 300 struct drm_amdgpu_sched_in in; 301 }; 302 303 /* 304 * This is not a reliable API and you should expect it to fail for any 305 * number of reasons and have fallback path that do not use userptr to 306 * perform any operation. 307 */ 308 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 309 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 310 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 311 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 312 313 struct drm_amdgpu_gem_userptr { 314 __u64 addr; 315 __u64 size; 316 /* AMDGPU_GEM_USERPTR_* */ 317 __u32 flags; 318 /* Resulting GEM handle */ 319 __u32 handle; 320 }; 321 322 /* SI-CI-VI: */ 323 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 324 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 325 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 326 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 327 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 328 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 329 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 330 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 331 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 332 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 333 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 334 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 335 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 336 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 337 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 338 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 339 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 340 341 /* GFX9 and later: */ 342 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 343 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 344 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 345 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 346 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 347 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 348 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 349 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 350 351 /* Set/Get helpers for tiling flags. */ 352 #define AMDGPU_TILING_SET(field, value) \ 353 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 354 #define AMDGPU_TILING_GET(value, field) \ 355 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 356 357 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 358 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 359 360 /** The same structure is shared for input/output */ 361 struct drm_amdgpu_gem_metadata { 362 /** GEM Object handle */ 363 __u32 handle; 364 /** Do we want get or set metadata */ 365 __u32 op; 366 struct { 367 /** For future use, no flags defined so far */ 368 __u64 flags; 369 /** family specific tiling info */ 370 __u64 tiling_info; 371 __u32 data_size_bytes; 372 __u32 data[64]; 373 } data; 374 }; 375 376 struct drm_amdgpu_gem_mmap_in { 377 /** the GEM object handle */ 378 __u32 handle; 379 __u32 _pad; 380 }; 381 382 struct drm_amdgpu_gem_mmap_out { 383 /** mmap offset from the vma offset manager */ 384 __u64 addr_ptr; 385 }; 386 387 union drm_amdgpu_gem_mmap { 388 struct drm_amdgpu_gem_mmap_in in; 389 struct drm_amdgpu_gem_mmap_out out; 390 }; 391 392 struct drm_amdgpu_gem_wait_idle_in { 393 /** GEM object handle */ 394 __u32 handle; 395 /** For future use, no flags defined so far */ 396 __u32 flags; 397 /** Absolute timeout to wait */ 398 __u64 timeout; 399 }; 400 401 struct drm_amdgpu_gem_wait_idle_out { 402 /** BO status: 0 - BO is idle, 1 - BO is busy */ 403 __u32 status; 404 /** Returned current memory domain */ 405 __u32 domain; 406 }; 407 408 union drm_amdgpu_gem_wait_idle { 409 struct drm_amdgpu_gem_wait_idle_in in; 410 struct drm_amdgpu_gem_wait_idle_out out; 411 }; 412 413 struct drm_amdgpu_wait_cs_in { 414 /* Command submission handle 415 * handle equals 0 means none to wait for 416 * handle equals ~0ull means wait for the latest sequence number 417 */ 418 __u64 handle; 419 /** Absolute timeout to wait */ 420 __u64 timeout; 421 __u32 ip_type; 422 __u32 ip_instance; 423 __u32 ring; 424 __u32 ctx_id; 425 }; 426 427 struct drm_amdgpu_wait_cs_out { 428 /** CS status: 0 - CS completed, 1 - CS still busy */ 429 __u64 status; 430 }; 431 432 union drm_amdgpu_wait_cs { 433 struct drm_amdgpu_wait_cs_in in; 434 struct drm_amdgpu_wait_cs_out out; 435 }; 436 437 struct drm_amdgpu_fence { 438 __u32 ctx_id; 439 __u32 ip_type; 440 __u32 ip_instance; 441 __u32 ring; 442 __u64 seq_no; 443 }; 444 445 struct drm_amdgpu_wait_fences_in { 446 /** This points to uint64_t * which points to fences */ 447 __u64 fences; 448 __u32 fence_count; 449 __u32 wait_all; 450 __u64 timeout_ns; 451 }; 452 453 struct drm_amdgpu_wait_fences_out { 454 __u32 status; 455 __u32 first_signaled; 456 }; 457 458 union drm_amdgpu_wait_fences { 459 struct drm_amdgpu_wait_fences_in in; 460 struct drm_amdgpu_wait_fences_out out; 461 }; 462 463 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 464 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 465 466 /* Sets or returns a value associated with a buffer. */ 467 struct drm_amdgpu_gem_op { 468 /** GEM object handle */ 469 __u32 handle; 470 /** AMDGPU_GEM_OP_* */ 471 __u32 op; 472 /** Input or return value */ 473 __u64 value; 474 }; 475 476 #define AMDGPU_VA_OP_MAP 1 477 #define AMDGPU_VA_OP_UNMAP 2 478 #define AMDGPU_VA_OP_CLEAR 3 479 #define AMDGPU_VA_OP_REPLACE 4 480 481 /* Delay the page table update till the next CS */ 482 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 483 484 /* Mapping flags */ 485 /* readable mapping */ 486 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 487 /* writable mapping */ 488 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 489 /* executable mapping, new for VI */ 490 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 491 /* partially resident texture */ 492 #define AMDGPU_VM_PAGE_PRT (1 << 4) 493 /* MTYPE flags use bit 5 to 8 */ 494 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 495 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 496 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 497 /* Use NC MTYPE instead of default MTYPE */ 498 #define AMDGPU_VM_MTYPE_NC (1 << 5) 499 /* Use WC MTYPE instead of default MTYPE */ 500 #define AMDGPU_VM_MTYPE_WC (2 << 5) 501 /* Use CC MTYPE instead of default MTYPE */ 502 #define AMDGPU_VM_MTYPE_CC (3 << 5) 503 /* Use UC MTYPE instead of default MTYPE */ 504 #define AMDGPU_VM_MTYPE_UC (4 << 5) 505 /* Use RW MTYPE instead of default MTYPE */ 506 #define AMDGPU_VM_MTYPE_RW (5 << 5) 507 508 struct drm_amdgpu_gem_va { 509 /** GEM object handle */ 510 __u32 handle; 511 __u32 _pad; 512 /** AMDGPU_VA_OP_* */ 513 __u32 operation; 514 /** AMDGPU_VM_PAGE_* */ 515 __u32 flags; 516 /** va address to assign . Must be correctly aligned.*/ 517 __u64 va_address; 518 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 519 __u64 offset_in_bo; 520 /** Specify mapping size. Must be correctly aligned. */ 521 __u64 map_size; 522 }; 523 524 #define AMDGPU_HW_IP_GFX 0 525 #define AMDGPU_HW_IP_COMPUTE 1 526 #define AMDGPU_HW_IP_DMA 2 527 #define AMDGPU_HW_IP_UVD 3 528 #define AMDGPU_HW_IP_VCE 4 529 #define AMDGPU_HW_IP_UVD_ENC 5 530 #define AMDGPU_HW_IP_VCN_DEC 6 531 #define AMDGPU_HW_IP_VCN_ENC 7 532 #define AMDGPU_HW_IP_VCN_JPEG 8 533 #define AMDGPU_HW_IP_NUM 9 534 535 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 536 537 #define AMDGPU_CHUNK_ID_IB 0x01 538 #define AMDGPU_CHUNK_ID_FENCE 0x02 539 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 540 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 541 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 542 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 543 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 544 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 545 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 546 547 struct drm_amdgpu_cs_chunk { 548 __u32 chunk_id; 549 __u32 length_dw; 550 __u64 chunk_data; 551 }; 552 553 struct drm_amdgpu_cs_in { 554 /** Rendering context id */ 555 __u32 ctx_id; 556 /** Handle of resource list associated with CS */ 557 __u32 bo_list_handle; 558 __u32 num_chunks; 559 __u32 _pad; 560 /** this points to __u64 * which point to cs chunks */ 561 __u64 chunks; 562 }; 563 564 struct drm_amdgpu_cs_out { 565 __u64 handle; 566 }; 567 568 union drm_amdgpu_cs { 569 struct drm_amdgpu_cs_in in; 570 struct drm_amdgpu_cs_out out; 571 }; 572 573 /* Specify flags to be used for IB */ 574 575 /* This IB should be submitted to CE */ 576 #define AMDGPU_IB_FLAG_CE (1<<0) 577 578 /* Preamble flag, which means the IB could be dropped if no context switch */ 579 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 580 581 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 582 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 583 584 /* The IB fence should do the L2 writeback but not invalidate any shader 585 * caches (L2/vL1/sL1/I$). */ 586 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 587 588 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 589 * This will reset wave ID counters for the IB. 590 */ 591 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 592 593 struct drm_amdgpu_cs_chunk_ib { 594 __u32 _pad; 595 /** AMDGPU_IB_FLAG_* */ 596 __u32 flags; 597 /** Virtual address to begin IB execution */ 598 __u64 va_start; 599 /** Size of submission */ 600 __u32 ib_bytes; 601 /** HW IP to submit to */ 602 __u32 ip_type; 603 /** HW IP index of the same type to submit to */ 604 __u32 ip_instance; 605 /** Ring index to submit to */ 606 __u32 ring; 607 }; 608 609 struct drm_amdgpu_cs_chunk_dep { 610 __u32 ip_type; 611 __u32 ip_instance; 612 __u32 ring; 613 __u32 ctx_id; 614 __u64 handle; 615 }; 616 617 struct drm_amdgpu_cs_chunk_fence { 618 __u32 handle; 619 __u32 offset; 620 }; 621 622 struct drm_amdgpu_cs_chunk_sem { 623 __u32 handle; 624 }; 625 626 struct drm_amdgpu_cs_chunk_syncobj { 627 __u32 handle; 628 __u32 flags; 629 __u64 point; 630 }; 631 632 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 633 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 634 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 635 636 union drm_amdgpu_fence_to_handle { 637 struct { 638 struct drm_amdgpu_fence fence; 639 __u32 what; 640 __u32 pad; 641 } in; 642 struct { 643 __u32 handle; 644 } out; 645 }; 646 647 struct drm_amdgpu_cs_chunk_data { 648 union { 649 struct drm_amdgpu_cs_chunk_ib ib_data; 650 struct drm_amdgpu_cs_chunk_fence fence_data; 651 }; 652 }; 653 654 /** 655 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 656 * 657 */ 658 #define AMDGPU_IDS_FLAGS_FUSION 0x1 659 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 660 661 /* indicate if acceleration can be working */ 662 #define AMDGPU_INFO_ACCEL_WORKING 0x00 663 /* get the crtc_id from the mode object id? */ 664 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 665 /* query hw IP info */ 666 #define AMDGPU_INFO_HW_IP_INFO 0x02 667 /* query hw IP instance count for the specified type */ 668 #define AMDGPU_INFO_HW_IP_COUNT 0x03 669 /* timestamp for GL_ARB_timer_query */ 670 #define AMDGPU_INFO_TIMESTAMP 0x05 671 /* Query the firmware version */ 672 #define AMDGPU_INFO_FW_VERSION 0x0e 673 /* Subquery id: Query VCE firmware version */ 674 #define AMDGPU_INFO_FW_VCE 0x1 675 /* Subquery id: Query UVD firmware version */ 676 #define AMDGPU_INFO_FW_UVD 0x2 677 /* Subquery id: Query GMC firmware version */ 678 #define AMDGPU_INFO_FW_GMC 0x03 679 /* Subquery id: Query GFX ME firmware version */ 680 #define AMDGPU_INFO_FW_GFX_ME 0x04 681 /* Subquery id: Query GFX PFP firmware version */ 682 #define AMDGPU_INFO_FW_GFX_PFP 0x05 683 /* Subquery id: Query GFX CE firmware version */ 684 #define AMDGPU_INFO_FW_GFX_CE 0x06 685 /* Subquery id: Query GFX RLC firmware version */ 686 #define AMDGPU_INFO_FW_GFX_RLC 0x07 687 /* Subquery id: Query GFX MEC firmware version */ 688 #define AMDGPU_INFO_FW_GFX_MEC 0x08 689 /* Subquery id: Query SMC firmware version */ 690 #define AMDGPU_INFO_FW_SMC 0x0a 691 /* Subquery id: Query SDMA firmware version */ 692 #define AMDGPU_INFO_FW_SDMA 0x0b 693 /* Subquery id: Query PSP SOS firmware version */ 694 #define AMDGPU_INFO_FW_SOS 0x0c 695 /* Subquery id: Query PSP ASD firmware version */ 696 #define AMDGPU_INFO_FW_ASD 0x0d 697 /* Subquery id: Query VCN firmware version */ 698 #define AMDGPU_INFO_FW_VCN 0x0e 699 /* Subquery id: Query GFX RLC SRLC firmware version */ 700 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 701 /* Subquery id: Query GFX RLC SRLG firmware version */ 702 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 703 /* Subquery id: Query GFX RLC SRLS firmware version */ 704 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 705 /* Subquery id: Query DMCU firmware version */ 706 #define AMDGPU_INFO_FW_DMCU 0x12 707 #define AMDGPU_INFO_FW_TA 0x13 708 /* Subquery id: Query DMCUB firmware version */ 709 #define AMDGPU_INFO_FW_DMCUB 0x14 710 711 /* number of bytes moved for TTM migration */ 712 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 713 /* the used VRAM size */ 714 #define AMDGPU_INFO_VRAM_USAGE 0x10 715 /* the used GTT size */ 716 #define AMDGPU_INFO_GTT_USAGE 0x11 717 /* Information about GDS, etc. resource configuration */ 718 #define AMDGPU_INFO_GDS_CONFIG 0x13 719 /* Query information about VRAM and GTT domains */ 720 #define AMDGPU_INFO_VRAM_GTT 0x14 721 /* Query information about register in MMR address space*/ 722 #define AMDGPU_INFO_READ_MMR_REG 0x15 723 /* Query information about device: rev id, family, etc. */ 724 #define AMDGPU_INFO_DEV_INFO 0x16 725 /* visible vram usage */ 726 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 727 /* number of TTM buffer evictions */ 728 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 729 /* Query memory about VRAM and GTT domains */ 730 #define AMDGPU_INFO_MEMORY 0x19 731 /* Query vce clock table */ 732 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 733 /* Query vbios related information */ 734 #define AMDGPU_INFO_VBIOS 0x1B 735 /* Subquery id: Query vbios size */ 736 #define AMDGPU_INFO_VBIOS_SIZE 0x1 737 /* Subquery id: Query vbios image */ 738 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 739 /* Query UVD handles */ 740 #define AMDGPU_INFO_NUM_HANDLES 0x1C 741 /* Query sensor related information */ 742 #define AMDGPU_INFO_SENSOR 0x1D 743 /* Subquery id: Query GPU shader clock */ 744 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 745 /* Subquery id: Query GPU memory clock */ 746 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 747 /* Subquery id: Query GPU temperature */ 748 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 749 /* Subquery id: Query GPU load */ 750 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 751 /* Subquery id: Query average GPU power */ 752 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 753 /* Subquery id: Query northbridge voltage */ 754 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 755 /* Subquery id: Query graphics voltage */ 756 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 757 /* Subquery id: Query GPU stable pstate shader clock */ 758 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 759 /* Subquery id: Query GPU stable pstate memory clock */ 760 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 761 /* Number of VRAM page faults on CPU access. */ 762 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 763 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 764 /* query ras mask of enabled features*/ 765 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 766 767 /* RAS MASK: UMC (VRAM) */ 768 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 769 /* RAS MASK: SDMA */ 770 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 771 /* RAS MASK: GFX */ 772 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 773 /* RAS MASK: MMHUB */ 774 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 775 /* RAS MASK: ATHUB */ 776 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 777 /* RAS MASK: PCIE */ 778 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 779 /* RAS MASK: HDP */ 780 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 781 /* RAS MASK: XGMI */ 782 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 783 /* RAS MASK: DF */ 784 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 785 /* RAS MASK: SMN */ 786 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 787 /* RAS MASK: SEM */ 788 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 789 /* RAS MASK: MP0 */ 790 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 791 /* RAS MASK: MP1 */ 792 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 793 /* RAS MASK: FUSE */ 794 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 795 796 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 797 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 798 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 799 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 800 801 struct drm_amdgpu_query_fw { 802 /** AMDGPU_INFO_FW_* */ 803 __u32 fw_type; 804 /** 805 * Index of the IP if there are more IPs of 806 * the same type. 807 */ 808 __u32 ip_instance; 809 /** 810 * Index of the engine. Whether this is used depends 811 * on the firmware type. (e.g. MEC, SDMA) 812 */ 813 __u32 index; 814 __u32 _pad; 815 }; 816 817 /* Input structure for the INFO ioctl */ 818 struct drm_amdgpu_info { 819 /* Where the return value will be stored */ 820 __u64 return_pointer; 821 /* The size of the return value. Just like "size" in "snprintf", 822 * it limits how many bytes the kernel can write. */ 823 __u32 return_size; 824 /* The query request id. */ 825 __u32 query; 826 827 union { 828 struct { 829 __u32 id; 830 __u32 _pad; 831 } mode_crtc; 832 833 struct { 834 /** AMDGPU_HW_IP_* */ 835 __u32 type; 836 /** 837 * Index of the IP if there are more IPs of the same 838 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 839 */ 840 __u32 ip_instance; 841 } query_hw_ip; 842 843 struct { 844 __u32 dword_offset; 845 /** number of registers to read */ 846 __u32 count; 847 __u32 instance; 848 /** For future use, no flags defined so far */ 849 __u32 flags; 850 } read_mmr_reg; 851 852 struct drm_amdgpu_query_fw query_fw; 853 854 struct { 855 __u32 type; 856 __u32 offset; 857 } vbios_info; 858 859 struct { 860 __u32 type; 861 } sensor_info; 862 }; 863 }; 864 865 struct drm_amdgpu_info_gds { 866 /** GDS GFX partition size */ 867 __u32 gds_gfx_partition_size; 868 /** GDS compute partition size */ 869 __u32 compute_partition_size; 870 /** total GDS memory size */ 871 __u32 gds_total_size; 872 /** GWS size per GFX partition */ 873 __u32 gws_per_gfx_partition; 874 /** GSW size per compute partition */ 875 __u32 gws_per_compute_partition; 876 /** OA size per GFX partition */ 877 __u32 oa_per_gfx_partition; 878 /** OA size per compute partition */ 879 __u32 oa_per_compute_partition; 880 __u32 _pad; 881 }; 882 883 struct drm_amdgpu_info_vram_gtt { 884 __u64 vram_size; 885 __u64 vram_cpu_accessible_size; 886 __u64 gtt_size; 887 }; 888 889 struct drm_amdgpu_heap_info { 890 /** max. physical memory */ 891 __u64 total_heap_size; 892 893 /** Theoretical max. available memory in the given heap */ 894 __u64 usable_heap_size; 895 896 /** 897 * Number of bytes allocated in the heap. This includes all processes 898 * and private allocations in the kernel. It changes when new buffers 899 * are allocated, freed, and moved. It cannot be larger than 900 * heap_size. 901 */ 902 __u64 heap_usage; 903 904 /** 905 * Theoretical possible max. size of buffer which 906 * could be allocated in the given heap 907 */ 908 __u64 max_allocation; 909 }; 910 911 struct drm_amdgpu_memory_info { 912 struct drm_amdgpu_heap_info vram; 913 struct drm_amdgpu_heap_info cpu_accessible_vram; 914 struct drm_amdgpu_heap_info gtt; 915 }; 916 917 struct drm_amdgpu_info_firmware { 918 __u32 ver; 919 __u32 feature; 920 }; 921 922 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 923 #define AMDGPU_VRAM_TYPE_GDDR1 1 924 #define AMDGPU_VRAM_TYPE_DDR2 2 925 #define AMDGPU_VRAM_TYPE_GDDR3 3 926 #define AMDGPU_VRAM_TYPE_GDDR4 4 927 #define AMDGPU_VRAM_TYPE_GDDR5 5 928 #define AMDGPU_VRAM_TYPE_HBM 6 929 #define AMDGPU_VRAM_TYPE_DDR3 7 930 #define AMDGPU_VRAM_TYPE_DDR4 8 931 #define AMDGPU_VRAM_TYPE_GDDR6 9 932 933 struct drm_amdgpu_info_device { 934 /** PCI Device ID */ 935 __u32 device_id; 936 /** Internal chip revision: A0, A1, etc.) */ 937 __u32 chip_rev; 938 __u32 external_rev; 939 /** Revision id in PCI Config space */ 940 __u32 pci_rev; 941 __u32 family; 942 __u32 num_shader_engines; 943 __u32 num_shader_arrays_per_engine; 944 /* in KHz */ 945 __u32 gpu_counter_freq; 946 __u64 max_engine_clock; 947 __u64 max_memory_clock; 948 /* cu information */ 949 __u32 cu_active_number; 950 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 951 __u32 cu_ao_mask; 952 __u32 cu_bitmap[4][4]; 953 /** Render backend pipe mask. One render backend is CB+DB. */ 954 __u32 enabled_rb_pipes_mask; 955 __u32 num_rb_pipes; 956 __u32 num_hw_gfx_contexts; 957 __u32 _pad; 958 __u64 ids_flags; 959 /** Starting virtual address for UMDs. */ 960 __u64 virtual_address_offset; 961 /** The maximum virtual address */ 962 __u64 virtual_address_max; 963 /** Required alignment of virtual addresses. */ 964 __u32 virtual_address_alignment; 965 /** Page table entry - fragment size */ 966 __u32 pte_fragment_size; 967 __u32 gart_page_size; 968 /** constant engine ram size*/ 969 __u32 ce_ram_size; 970 /** video memory type info*/ 971 __u32 vram_type; 972 /** video memory bit width*/ 973 __u32 vram_bit_width; 974 /* vce harvesting instance */ 975 __u32 vce_harvest_config; 976 /* gfx double offchip LDS buffers */ 977 __u32 gc_double_offchip_lds_buf; 978 /* NGG Primitive Buffer */ 979 __u64 prim_buf_gpu_addr; 980 /* NGG Position Buffer */ 981 __u64 pos_buf_gpu_addr; 982 /* NGG Control Sideband */ 983 __u64 cntl_sb_buf_gpu_addr; 984 /* NGG Parameter Cache */ 985 __u64 param_buf_gpu_addr; 986 __u32 prim_buf_size; 987 __u32 pos_buf_size; 988 __u32 cntl_sb_buf_size; 989 __u32 param_buf_size; 990 /* wavefront size*/ 991 __u32 wave_front_size; 992 /* shader visible vgprs*/ 993 __u32 num_shader_visible_vgprs; 994 /* CU per shader array*/ 995 __u32 num_cu_per_sh; 996 /* number of tcc blocks*/ 997 __u32 num_tcc_blocks; 998 /* gs vgt table depth*/ 999 __u32 gs_vgt_table_depth; 1000 /* gs primitive buffer depth*/ 1001 __u32 gs_prim_buffer_depth; 1002 /* max gs wavefront per vgt*/ 1003 __u32 max_gs_waves_per_vgt; 1004 __u32 _pad1; 1005 /* always on cu bitmap */ 1006 __u32 cu_ao_bitmap[4][4]; 1007 /** Starting high virtual address for UMDs. */ 1008 __u64 high_va_offset; 1009 /** The maximum high virtual address */ 1010 __u64 high_va_max; 1011 /* gfx10 pa_sc_tile_steering_override */ 1012 __u32 pa_sc_tile_steering_override; 1013 /* disabled TCCs */ 1014 __u64 tcc_disabled_mask; 1015 }; 1016 1017 struct drm_amdgpu_info_hw_ip { 1018 /** Version of h/w IP */ 1019 __u32 hw_ip_version_major; 1020 __u32 hw_ip_version_minor; 1021 /** Capabilities */ 1022 __u64 capabilities_flags; 1023 /** command buffer address start alignment*/ 1024 __u32 ib_start_alignment; 1025 /** command buffer size alignment*/ 1026 __u32 ib_size_alignment; 1027 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1028 __u32 available_rings; 1029 __u32 _pad; 1030 }; 1031 1032 struct drm_amdgpu_info_num_handles { 1033 /** Max handles as supported by firmware for UVD */ 1034 __u32 uvd_max_handles; 1035 /** Handles currently in use for UVD */ 1036 __u32 uvd_used_handles; 1037 }; 1038 1039 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1040 1041 struct drm_amdgpu_info_vce_clock_table_entry { 1042 /** System clock */ 1043 __u32 sclk; 1044 /** Memory clock */ 1045 __u32 mclk; 1046 /** VCE clock */ 1047 __u32 eclk; 1048 __u32 pad; 1049 }; 1050 1051 struct drm_amdgpu_info_vce_clock_table { 1052 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1053 __u32 num_valid_entries; 1054 __u32 pad; 1055 }; 1056 1057 /* 1058 * Supported GPU families 1059 */ 1060 #define AMDGPU_FAMILY_UNKNOWN 0 1061 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1062 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1063 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1064 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1065 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1066 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1067 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1068 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1069 1070 #if defined(__cplusplus) 1071 } 1072 #endif 1073 1074 #endif 1075
Indexes created Sat Sep 20 22:09:52 GMT 2025