1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /** 25 * \file amdgpu.h 26 * 27 * Declare public libdrm_amdgpu API 28 * 29 * This file define API exposed by libdrm_amdgpu library. 30 * User wanted to use libdrm_amdgpu functionality must include 31 * this file. 32 * 33 */ 34 #ifndef _AMDGPU_H_ 35 #define _AMDGPU_H_ 36 37 #include <stdint.h> 38 #include <stdbool.h> 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 struct drm_amdgpu_info_hw_ip; 45 struct drm_amdgpu_info_uq_fw_areas; 46 struct drm_amdgpu_bo_list_entry; 47 struct drm_amdgpu_userq_signal; 48 struct drm_amdgpu_userq_wait; 49 50 /*--------------------------------------------------------------------------*/ 51 /* --------------------------- Defines ------------------------------------ */ 52 /*--------------------------------------------------------------------------*/ 53 54 /** 55 * Define max. number of Command Buffers (IB) which could be sent to the single 56 * hardware IP to accommodate CE/DE requirements 57 * 58 * \sa amdgpu_cs_ib_info 59 */ 60 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 61 62 /** 63 * Special timeout value meaning that the timeout is infinite. 64 */ 65 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull 66 67 /** 68 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout 69 * is absolute. 70 */ 71 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) 72 73 /*--------------------------------------------------------------------------*/ 74 /* ----------------------------- Enums ------------------------------------ */ 75 /*--------------------------------------------------------------------------*/ 76 77 /** 78 * Enum describing possible handle types 79 * 80 * \sa amdgpu_bo_import, amdgpu_bo_export 81 * 82 */ 83 enum amdgpu_bo_handle_type { 84 /** GEM flink name (needs DRM authentication, used by DRI2) */ 85 amdgpu_bo_handle_type_gem_flink_name = 0, 86 87 /** KMS handle which is used by all driver ioctls */ 88 amdgpu_bo_handle_type_kms = 1, 89 90 /** DMA-buf fd handle */ 91 amdgpu_bo_handle_type_dma_buf_fd = 2, 92 93 /** Deprecated in favour of and same behaviour as 94 * amdgpu_bo_handle_type_kms, use that instead of this 95 */ 96 amdgpu_bo_handle_type_kms_noimport = 3, 97 }; 98 99 /** Define known types of GPU VM VA ranges */ 100 enum amdgpu_gpu_va_range 101 { 102 /** Allocate from "normal"/general range */ 103 amdgpu_gpu_va_range_general = 0 104 }; 105 106 enum amdgpu_sw_info { 107 amdgpu_sw_info_address32_hi = 0, 108 /** Query the PRT control bit when the half VA range is reserved for 109 * PRT when the device is initialized. This depends on the GFX version. 110 * A return value of ~0 should be ignored. 111 */ 112 amdgpu_sw_info_address_prt_wa_control_bit = 1, 113 }; 114 115 enum amdgpu_va_manager_sw_info { 116 /** Query the PRT control bit when the half VA range is reserved for 117 * PRT with AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT. The default value of 118 * ~0 shouldn't be considered a valid value. 119 */ 120 amdgpu_va_manager_sw_info_address_prt_wa_control_bit = 0, 121 }; 122 123 /*--------------------------------------------------------------------------*/ 124 /* -------------------------- Datatypes ----------------------------------- */ 125 /*--------------------------------------------------------------------------*/ 126 127 /** 128 * Define opaque pointer to context associated with fd. 129 * This context will be returned as the result of 130 * "initialize" function and should be pass as the first 131 * parameter to any API call 132 */ 133 #ifndef AMDGPU_DEVICE_TYPEDEF 134 #define AMDGPU_DEVICE_TYPEDEF 135 typedef struct amdgpu_device *amdgpu_device_handle; 136 #endif 137 138 /** 139 * Define GPU Context type as pointer to opaque structure 140 * Example of GPU Context is the "rendering" context associated 141 * with OpenGL context (glCreateContext) 142 */ 143 typedef struct amdgpu_context *amdgpu_context_handle; 144 145 /** 146 * Define handle for amdgpu resources: buffer, GDS, etc. 147 */ 148 typedef struct amdgpu_bo *amdgpu_bo_handle; 149 150 /** 151 * Define handle for list of BOs 152 */ 153 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; 154 155 /** 156 * Define handle to be used to work with VA allocated ranges 157 */ 158 typedef struct amdgpu_va *amdgpu_va_handle; 159 160 /** 161 * Define handle dealing with VA allocation. An amdgpu_device 162 * owns one of these, but they can also be used without a device. 163 */ 164 typedef struct amdgpu_va_manager *amdgpu_va_manager_handle; 165 166 /** 167 * Define handle for semaphore 168 */ 169 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; 170 171 /*--------------------------------------------------------------------------*/ 172 /* -------------------------- Structures ---------------------------------- */ 173 /*--------------------------------------------------------------------------*/ 174 175 /** 176 * Structure describing memory allocation request 177 * 178 * \sa amdgpu_bo_alloc() 179 * 180 */ 181 struct amdgpu_bo_alloc_request { 182 /** Allocation request. It must be aligned correctly. */ 183 uint64_t alloc_size; 184 185 /** 186 * It may be required to have some specific alignment requirements 187 * for physical back-up storage (e.g. for displayable surface). 188 * If 0 there is no special alignment requirement 189 */ 190 uint64_t phys_alignment; 191 192 /** 193 * UMD should specify where to allocate memory and how it 194 * will be accessed by the CPU. 195 */ 196 uint32_t preferred_heap; 197 198 /** Additional flags passed on allocation */ 199 uint64_t flags; 200 }; 201 202 /** 203 * Special UMD specific information associated with buffer. 204 * 205 * It may be need to pass some buffer charactersitic as part 206 * of buffer sharing. Such information are defined UMD and 207 * opaque for libdrm_amdgpu as well for kernel driver. 208 * 209 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, 210 * amdgpu_bo_import(), amdgpu_bo_export 211 * 212 */ 213 struct amdgpu_bo_metadata { 214 /** Special flag associated with surface */ 215 uint64_t flags; 216 217 /** 218 * ASIC-specific tiling information (also used by DCE). 219 * The encoding is defined by the AMDGPU_TILING_* definitions. 220 */ 221 uint64_t tiling_info; 222 223 /** Size of metadata associated with the buffer, in bytes. */ 224 uint32_t size_metadata; 225 226 /** UMD specific metadata. Opaque for kernel */ 227 uint32_t umd_metadata[64]; 228 }; 229 230 /** 231 * Structure describing allocated buffer. Client may need 232 * to query such information as part of 'sharing' buffers mechanism 233 * 234 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), 235 * amdgpu_bo_import(), amdgpu_bo_export() 236 */ 237 struct amdgpu_bo_info { 238 /** Allocated memory size */ 239 uint64_t alloc_size; 240 241 /** 242 * It may be required to have some specific alignment requirements 243 * for physical back-up storage. 244 */ 245 uint64_t phys_alignment; 246 247 /** Heap where to allocate memory. */ 248 uint32_t preferred_heap; 249 250 /** Additional allocation flags. */ 251 uint64_t alloc_flags; 252 253 /** Metadata associated with buffer if any. */ 254 struct amdgpu_bo_metadata metadata; 255 }; 256 257 /** 258 * Structure with information about "imported" buffer 259 * 260 * \sa amdgpu_bo_import() 261 * 262 */ 263 struct amdgpu_bo_import_result { 264 /** Handle of memory/buffer to use */ 265 amdgpu_bo_handle buf_handle; 266 267 /** Buffer size */ 268 uint64_t alloc_size; 269 }; 270 271 /** 272 * 273 * Structure to describe GDS partitioning information. 274 * \note OA and GWS resources are asscoiated with GDS partition 275 * 276 * \sa amdgpu_gpu_resource_query_gds_info 277 * 278 */ 279 struct amdgpu_gds_resource_info { 280 uint32_t gds_gfx_partition_size; 281 uint32_t compute_partition_size; 282 uint32_t gds_total_size; 283 uint32_t gws_per_gfx_partition; 284 uint32_t gws_per_compute_partition; 285 uint32_t oa_per_gfx_partition; 286 uint32_t oa_per_compute_partition; 287 }; 288 289 /** 290 * Structure describing CS fence 291 * 292 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit() 293 * 294 */ 295 struct amdgpu_cs_fence { 296 297 /** In which context IB was sent to execution */ 298 amdgpu_context_handle context; 299 300 /** To which HW IP type the fence belongs */ 301 uint32_t ip_type; 302 303 /** IP instance index if there are several IPs of the same type. */ 304 uint32_t ip_instance; 305 306 /** Ring index of the HW IP */ 307 uint32_t ring; 308 309 /** Specify fence for which we need to check submission status.*/ 310 uint64_t fence; 311 }; 312 313 /** 314 * Structure describing IB 315 * 316 * \sa amdgpu_cs_request, amdgpu_cs_submit() 317 * 318 */ 319 struct amdgpu_cs_ib_info { 320 /** Special flags */ 321 uint64_t flags; 322 323 /** Virtual MC address of the command buffer */ 324 uint64_t ib_mc_address; 325 326 /** 327 * Size of Command Buffer to be submitted. 328 * - The size is in units of dwords (4 bytes). 329 * - Could be 0 330 */ 331 uint32_t size; 332 }; 333 334 /** 335 * Structure describing fence information 336 * 337 * \sa amdgpu_cs_request, amdgpu_cs_query_fence, 338 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() 339 */ 340 struct amdgpu_cs_fence_info { 341 /** buffer object for the fence */ 342 amdgpu_bo_handle handle; 343 344 /** fence offset in the unit of sizeof(uint64_t) */ 345 uint64_t offset; 346 }; 347 348 /** 349 * Structure describing submission request 350 * 351 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx 352 * 353 * \sa amdgpu_cs_submit() 354 */ 355 struct amdgpu_cs_request { 356 /** Specify flags with additional information */ 357 uint64_t flags; 358 359 /** Specify HW IP block type to which to send the IB. */ 360 unsigned ip_type; 361 362 /** IP instance index if there are several IPs of the same type. */ 363 unsigned ip_instance; 364 365 /** 366 * Specify ring index of the IP. We could have several rings 367 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. 368 */ 369 uint32_t ring; 370 371 /** 372 * List handle with resources used by this request. 373 */ 374 amdgpu_bo_list_handle resources; 375 376 /** 377 * Number of dependencies this Command submission needs to 378 * wait for before starting execution. 379 */ 380 uint32_t number_of_dependencies; 381 382 /** 383 * Array of dependencies which need to be met before 384 * execution can start. 385 */ 386 struct amdgpu_cs_fence *dependencies; 387 388 /** Number of IBs to submit in the field ibs. */ 389 uint32_t number_of_ibs; 390 391 /** 392 * IBs to submit. Those IBs will be submit together as single entity 393 */ 394 struct amdgpu_cs_ib_info *ibs; 395 396 /** 397 * The returned sequence number for the command submission 398 */ 399 uint64_t seq_no; 400 401 /** 402 * The fence information 403 */ 404 struct amdgpu_cs_fence_info fence_info; 405 }; 406 407 /** 408 * Structure which provide information about GPU VM MC Address space 409 * alignments requirements 410 * 411 * \sa amdgpu_query_buffer_size_alignment 412 */ 413 struct amdgpu_buffer_size_alignments { 414 /** Size alignment requirement for allocation in 415 * local memory */ 416 uint64_t size_local; 417 418 /** 419 * Size alignment requirement for allocation in remote memory 420 */ 421 uint64_t size_remote; 422 }; 423 424 /** 425 * Structure which provide information about heap 426 * 427 * \sa amdgpu_query_heap_info() 428 * 429 */ 430 struct amdgpu_heap_info { 431 /** Theoretical max. available memory in the given heap */ 432 uint64_t heap_size; 433 434 /** 435 * Number of bytes allocated in the heap. This includes all processes 436 * and private allocations in the kernel. It changes when new buffers 437 * are allocated, freed, and moved. It cannot be larger than 438 * heap_size. 439 */ 440 uint64_t heap_usage; 441 442 /** 443 * Theoretical possible max. size of buffer which 444 * could be allocated in the given heap 445 */ 446 uint64_t max_allocation; 447 }; 448 449 /** 450 * Describe GPU h/w info needed for UMD correct initialization 451 * 452 * \sa amdgpu_query_gpu_info() 453 */ 454 struct amdgpu_gpu_info { 455 /** Asic id */ 456 uint32_t asic_id; 457 /** Chip revision */ 458 uint32_t chip_rev; 459 /** Chip external revision */ 460 uint32_t chip_external_rev; 461 /** Family ID */ 462 uint32_t family_id; 463 /** Special flags */ 464 uint64_t ids_flags; 465 /** max engine clock*/ 466 uint64_t max_engine_clk; 467 /** max memory clock */ 468 uint64_t max_memory_clk; 469 /** number of shader engines */ 470 uint32_t num_shader_engines; 471 /** number of shader arrays per engine */ 472 uint32_t num_shader_arrays_per_engine; 473 /** Number of available good shader pipes */ 474 uint32_t avail_quad_shader_pipes; 475 /** Max. number of shader pipes.(including good and bad pipes */ 476 uint32_t max_quad_shader_pipes; 477 /** Number of parameter cache entries per shader quad pipe */ 478 uint32_t cache_entries_per_quad_pipe; 479 /** Number of available graphics context */ 480 uint32_t num_hw_gfx_contexts; 481 /** Number of render backend pipes */ 482 uint32_t rb_pipes; 483 /** Enabled render backend pipe mask */ 484 uint32_t enabled_rb_pipes_mask; 485 /** Frequency of GPU Counter */ 486 uint32_t gpu_counter_freq; 487 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ 488 uint32_t backend_disable[4]; 489 /** Value of MC_ARB_RAMCFG register*/ 490 uint32_t mc_arb_ramcfg; 491 /** Value of GB_ADDR_CONFIG */ 492 uint32_t gb_addr_cfg; 493 /** Values of the GB_TILE_MODE0..31 registers */ 494 uint32_t gb_tile_mode[32]; 495 /** Values of GB_MACROTILE_MODE0..15 registers */ 496 uint32_t gb_macro_tile_mode[16]; 497 /** Value of PA_SC_RASTER_CONFIG register per SE */ 498 uint32_t pa_sc_raster_cfg[4]; 499 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ 500 uint32_t pa_sc_raster_cfg1[4]; 501 /* CU info */ 502 uint32_t cu_active_number; 503 uint32_t cu_ao_mask; 504 uint32_t cu_bitmap[4][4]; 505 /* video memory type info*/ 506 uint32_t vram_type; 507 /* video memory bit width*/ 508 uint32_t vram_bit_width; 509 /** constant engine ram size*/ 510 uint32_t ce_ram_size; 511 /* vce harvesting instance */ 512 uint32_t vce_harvest_config; 513 /* PCI revision ID */ 514 uint32_t pci_rev_id; 515 }; 516 517 518 /*--------------------------------------------------------------------------*/ 519 /*------------------------- Functions --------------------------------------*/ 520 /*--------------------------------------------------------------------------*/ 521 522 /* 523 * Initialization / Cleanup 524 * 525 */ 526 527 /** 528 * 529 * \param fd - \c [in] File descriptor for AMD GPU device 530 * received previously as the result of 531 * e.g. drmOpen() call. 532 * For legacy fd type, the DRI2/DRI3 533 * authentication should be done before 534 * calling this function. 535 * \param major_version - \c [out] Major version of library. It is assumed 536 * that adding new functionality will cause 537 * increase in major version 538 * \param minor_version - \c [out] Minor version of library 539 * \param device_handle - \c [out] Pointer to opaque context which should 540 * be passed as the first parameter on each 541 * API call 542 * 543 * 544 * \return 0 on success\n 545 * <0 - Negative POSIX Error code 546 * 547 * 548 * \sa amdgpu_device_deinitialize() 549 */ 550 int amdgpu_device_initialize(int fd, 551 uint32_t *major_version, 552 uint32_t *minor_version, 553 amdgpu_device_handle *device_handle); 554 555 /** 556 * Same as amdgpu_device_initialize() except when deduplicate_device 557 * is false *and* fd points to a device that was already initialized. 558 * In this case, amdgpu_device_initialize would return the same 559 * amdgpu_device_handle while here amdgpu_device_initialize2 would 560 * return a new handle. 561 * amdgpu_device_initialize() should be preferred in most situations; 562 * the only use-case where not-deduplicating devices make sense is 563 * when one wants to have isolated device handles in the same process. 564 */ 565 int amdgpu_device_initialize2(int fd, bool deduplicate_device, 566 uint32_t *major_version, 567 uint32_t *minor_version, 568 amdgpu_device_handle *device_handle); 569 /** 570 * 571 * When access to such library does not needed any more the special 572 * function must be call giving opportunity to clean up any 573 * resources if needed. 574 * 575 * \param device_handle - \c [in] Context associated with file 576 * descriptor for AMD GPU device 577 * received previously as the 578 * result e.g. of drmOpen() call. 579 * 580 * \return 0 on success\n 581 * <0 - Negative POSIX Error code 582 * 583 * \sa amdgpu_device_initialize() 584 * 585 */ 586 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); 587 588 /** 589 * 590 * /param device_handle - \c [in] Device handle. 591 * See #amdgpu_device_initialize() 592 * 593 * \return Returns the drm fd used for operations on this 594 * device. This is still owned by the library and hence 595 * should not be closed. Guaranteed to be valid until 596 * #amdgpu_device_deinitialize gets called. 597 * 598 */ 599 int amdgpu_device_get_fd(amdgpu_device_handle device_handle); 600 601 /* 602 * Memory Management 603 * 604 */ 605 606 /** 607 * Allocate memory to be used by UMD for GPU related operations 608 * 609 * \param dev - \c [in] Device handle. 610 * See #amdgpu_device_initialize() 611 * \param alloc_buffer - \c [in] Pointer to the structure describing an 612 * allocation request 613 * \param buf_handle - \c [out] Allocated buffer handle 614 * 615 * \return 0 on success\n 616 * <0 - Negative POSIX Error code 617 * 618 * \sa amdgpu_bo_free() 619 */ 620 int amdgpu_bo_alloc(amdgpu_device_handle dev, 621 struct amdgpu_bo_alloc_request *alloc_buffer, 622 amdgpu_bo_handle *buf_handle); 623 624 /** 625 * Associate opaque data with buffer to be queried by another UMD 626 * 627 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 628 * \param buf_handle - \c [in] Buffer handle 629 * \param info - \c [in] Metadata to associated with buffer 630 * 631 * \return 0 on success\n 632 * <0 - Negative POSIX Error code 633 */ 634 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, 635 struct amdgpu_bo_metadata *info); 636 637 /** 638 * Query buffer information including metadata previusly associated with 639 * buffer. 640 * 641 * \param dev - \c [in] Device handle. 642 * See #amdgpu_device_initialize() 643 * \param buf_handle - \c [in] Buffer handle 644 * \param info - \c [out] Structure describing buffer 645 * 646 * \return 0 on success\n 647 * <0 - Negative POSIX Error code 648 * 649 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 650 */ 651 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, 652 struct amdgpu_bo_info *info); 653 654 /** 655 * Allow others to get access to buffer 656 * 657 * \param dev - \c [in] Device handle. 658 * See #amdgpu_device_initialize() 659 * \param buf_handle - \c [in] Buffer handle 660 * \param type - \c [in] Type of handle requested 661 * \param shared_handle - \c [out] Special "shared" handle 662 * 663 * \return 0 on success\n 664 * <0 - Negative POSIX Error code 665 * 666 * \sa amdgpu_bo_import() 667 * 668 */ 669 int amdgpu_bo_export(amdgpu_bo_handle buf_handle, 670 enum amdgpu_bo_handle_type type, 671 uint32_t *shared_handle); 672 673 /** 674 * Request access to "shared" buffer 675 * 676 * \param dev - \c [in] Device handle. 677 * See #amdgpu_device_initialize() 678 * \param type - \c [in] Type of handle requested 679 * \param shared_handle - \c [in] Shared handle received as result "import" 680 * operation 681 * \param output - \c [out] Pointer to structure with information 682 * about imported buffer 683 * 684 * \return 0 on success\n 685 * <0 - Negative POSIX Error code 686 * 687 * \note Buffer must be "imported" only using new "fd" (different from 688 * one used by "exporter"). 689 * 690 * \sa amdgpu_bo_export() 691 * 692 */ 693 int amdgpu_bo_import(amdgpu_device_handle dev, 694 enum amdgpu_bo_handle_type type, 695 uint32_t shared_handle, 696 struct amdgpu_bo_import_result *output); 697 698 /** 699 * Request GPU access to user allocated memory e.g. via "malloc" 700 * 701 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 702 * \param cpu - [in] CPU address of user allocated memory which we 703 * want to map to GPU address space (make GPU accessible) 704 * (This address must be correctly aligned). 705 * \param size - [in] Size of allocation (must be correctly aligned) 706 * \param buf_handle - [out] Buffer handle for the userptr memory 707 * resource on submission and be used in other operations. 708 * 709 * 710 * \return 0 on success\n 711 * <0 - Negative POSIX Error code 712 * 713 * \note 714 * This call doesn't guarantee that such memory will be persistently 715 * "locked" / make non-pageable. The purpose of this call is to provide 716 * opportunity for GPU get access to this resource during submission. 717 * 718 * The maximum amount of memory which could be mapped in this call depends 719 * if overcommit is disabled or not. If overcommit is disabled than the max. 720 * amount of memory to be pinned will be limited by left "free" size in total 721 * amount of memory which could be locked simultaneously ("GART" size). 722 * 723 * Supported (theoretical) max. size of mapping is restricted only by 724 * "GART" size. 725 * 726 * It is responsibility of caller to correctly specify access rights 727 * on VA assignment. 728 */ 729 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 730 void *cpu, uint64_t size, 731 amdgpu_bo_handle *buf_handle); 732 733 /** 734 * Validate if the user memory comes from BO 735 * 736 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 737 * \param cpu - [in] CPU address of user allocated memory which we 738 * want to map to GPU address space (make GPU accessible) 739 * (This address must be correctly aligned). 740 * \param size - [in] Size of allocation (must be correctly aligned) 741 * \param buf_handle - [out] Buffer handle for the userptr memory 742 * if the user memory is not from BO, the buf_handle will be NULL. 743 * \param offset_in_bo - [out] offset in this BO for this user memory 744 * 745 * 746 * \return 0 on success\n 747 * <0 - Negative POSIX Error code 748 * 749 */ 750 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 751 void *cpu, 752 uint64_t size, 753 amdgpu_bo_handle *buf_handle, 754 uint64_t *offset_in_bo); 755 756 /** 757 * Free previously allocated memory 758 * 759 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 760 * \param buf_handle - \c [in] Buffer handle to free 761 * 762 * \return 0 on success\n 763 * <0 - Negative POSIX Error code 764 * 765 * \note In the case of memory shared between different applications all 766 * resources will be physically freed only all such applications 767 * will be terminated 768 * \note If is UMD responsibility to free buffer only when there is no 769 * more GPU access 770 * 771 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 772 * 773 */ 774 int amdgpu_bo_free(amdgpu_bo_handle buf_handle); 775 776 /** 777 * Increase the reference count of a buffer object 778 * 779 * \param bo - \c [in] Buffer object handle to increase the reference count 780 * 781 * \sa amdgpu_bo_alloc(), amdgpu_bo_free() 782 * 783 */ 784 void amdgpu_bo_inc_ref(amdgpu_bo_handle bo); 785 786 /** 787 * Request CPU access to GPU accessible memory 788 * 789 * \param buf_handle - \c [in] Buffer handle 790 * \param cpu - \c [out] CPU address to be used for access 791 * 792 * \return 0 on success\n 793 * <0 - Negative POSIX Error code 794 * 795 * \sa amdgpu_bo_cpu_unmap() 796 * 797 */ 798 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); 799 800 /** 801 * Release CPU access to GPU memory 802 * 803 * \param buf_handle - \c [in] Buffer handle 804 * 805 * \return 0 on success\n 806 * <0 - Negative POSIX Error code 807 * 808 * \sa amdgpu_bo_cpu_map() 809 * 810 */ 811 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); 812 813 /** 814 * Wait until a buffer is not used by the device. 815 * 816 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 817 * \param buf_handle - \c [in] Buffer handle. 818 * \param timeout_ns - Timeout in nanoseconds. 819 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed 820 * and no GPU access is scheduled. 821 * 1 GPU access is in fly or scheduled 822 * 823 * \return 0 - on success 824 * <0 - Negative POSIX Error code 825 */ 826 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, 827 uint64_t timeout_ns, 828 bool *buffer_busy); 829 830 /** 831 * Creates a BO list handle for command submission. 832 * 833 * \param dev - \c [in] Device handle. 834 * See #amdgpu_device_initialize() 835 * \param number_of_buffers - \c [in] Number of BOs in the list 836 * \param buffers - \c [in] List of BO handles 837 * \param result - \c [out] Created BO list handle 838 * 839 * \return 0 on success\n 840 * <0 - Negative POSIX Error code 841 * 842 * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2() 843 */ 844 int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, 845 uint32_t number_of_buffers, 846 struct drm_amdgpu_bo_list_entry *buffers, 847 uint32_t *result); 848 849 /** 850 * Destroys a BO list handle. 851 * 852 * \param bo_list - \c [in] BO list handle. 853 * 854 * \return 0 on success\n 855 * <0 - Negative POSIX Error code 856 * 857 * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2() 858 */ 859 int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list); 860 861 /** 862 * Creates a BO list handle for command submission. 863 * 864 * \param dev - \c [in] Device handle. 865 * See #amdgpu_device_initialize() 866 * \param number_of_resources - \c [in] Number of BOs in the list 867 * \param resources - \c [in] List of BO handles 868 * \param resource_prios - \c [in] Optional priority for each handle 869 * \param result - \c [out] Created BO list handle 870 * 871 * \return 0 on success\n 872 * <0 - Negative POSIX Error code 873 * 874 * \sa amdgpu_bo_list_destroy() 875 */ 876 int amdgpu_bo_list_create(amdgpu_device_handle dev, 877 uint32_t number_of_resources, 878 amdgpu_bo_handle *resources, 879 uint8_t *resource_prios, 880 amdgpu_bo_list_handle *result); 881 882 /** 883 * Destroys a BO list handle. 884 * 885 * \param handle - \c [in] BO list handle. 886 * 887 * \return 0 on success\n 888 * <0 - Negative POSIX Error code 889 * 890 * \sa amdgpu_bo_list_create() 891 */ 892 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle); 893 894 /** 895 * Update resources for existing BO list 896 * 897 * \param handle - \c [in] BO list handle 898 * \param number_of_resources - \c [in] Number of BOs in the list 899 * \param resources - \c [in] List of BO handles 900 * \param resource_prios - \c [in] Optional priority for each handle 901 * 902 * \return 0 on success\n 903 * <0 - Negative POSIX Error code 904 * 905 * \sa amdgpu_bo_list_update() 906 */ 907 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, 908 uint32_t number_of_resources, 909 amdgpu_bo_handle *resources, 910 uint8_t *resource_prios); 911 912 /* 913 * GPU Execution context 914 * 915 */ 916 917 /** 918 * Create GPU execution Context 919 * 920 * For the purpose of GPU Scheduler and GPU Robustness extensions it is 921 * necessary to have information/identify rendering/compute contexts. 922 * It also may be needed to associate some specific requirements with such 923 * contexts. Kernel driver will guarantee that submission from the same 924 * context will always be executed in order (first come, first serve). 925 * 926 * 927 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 928 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* 929 * \param context - \c [out] GPU Context handle 930 * 931 * \return 0 on success\n 932 * <0 - Negative POSIX Error code 933 * 934 * \sa amdgpu_cs_ctx_free() 935 * 936 */ 937 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, 938 uint32_t priority, 939 amdgpu_context_handle *context); 940 /** 941 * Create GPU execution Context 942 * 943 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call 944 * is missing the priority parameter. 945 * 946 * \sa amdgpu_cs_ctx_create2() 947 * 948 */ 949 int amdgpu_cs_ctx_create(amdgpu_device_handle dev, 950 amdgpu_context_handle *context); 951 952 /** 953 * 954 * Destroy GPU execution context when not needed any more 955 * 956 * \param context - \c [in] GPU Context handle 957 * 958 * \return 0 on success\n 959 * <0 - Negative POSIX Error code 960 * 961 * \sa amdgpu_cs_ctx_create() 962 * 963 */ 964 int amdgpu_cs_ctx_free(amdgpu_context_handle context); 965 966 /** 967 * Override the submission priority for the given context using a master fd. 968 * 969 * \param dev - \c [in] device handle 970 * \param context - \c [in] context handle for context id 971 * \param master_fd - \c [in] The master fd to authorize the override. 972 * \param priority - \c [in] The priority to assign to the context. 973 * 974 * \return 0 on success or a a negative Posix error code on failure. 975 */ 976 int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev, 977 amdgpu_context_handle context, 978 int master_fd, 979 unsigned priority); 980 981 /** 982 * Set or query the stable power state for GPU profiling. 983 * 984 * \param dev - \c [in] device handle 985 * \param op - \c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE 986 * \param flags - \c [in] AMDGPU_CTX_STABLE_PSTATE_* 987 * \param out_flags - \c [out] output current stable pstate 988 * 989 * \return 0 on success otherwise POSIX Error code. 990 */ 991 int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context, 992 uint32_t op, 993 uint32_t flags, 994 uint32_t *out_flags); 995 996 /** 997 * Query reset state for the specific GPU Context 998 * 999 * \param context - \c [in] GPU Context handle 1000 * \param state - \c [out] One of AMDGPU_CTX_*_RESET 1001 * \param hangs - \c [out] Number of hangs caused by the context. 1002 * 1003 * \return 0 on success\n 1004 * <0 - Negative POSIX Error code 1005 * 1006 * \sa amdgpu_cs_ctx_create() 1007 * 1008 */ 1009 int amdgpu_cs_query_reset_state(amdgpu_context_handle context, 1010 uint32_t *state, uint32_t *hangs); 1011 1012 /** 1013 * Query reset state for the specific GPU Context. 1014 * 1015 * \param context - \c [in] GPU Context handle 1016 * \param flags - \c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_* 1017 * 1018 * \return 0 on success\n 1019 * <0 - Negative POSIX Error code 1020 * 1021 * \sa amdgpu_cs_ctx_create() 1022 * 1023 */ 1024 int amdgpu_cs_query_reset_state2(amdgpu_context_handle context, 1025 uint64_t *flags); 1026 1027 /* 1028 * Command Buffers Management 1029 * 1030 */ 1031 1032 /** 1033 * Send request to submit command buffers to hardware. 1034 * 1035 * Kernel driver could use GPU Scheduler to make decision when physically 1036 * sent this request to the hardware. Accordingly this request could be put 1037 * in queue and sent for execution later. The only guarantee is that request 1038 * from the same GPU context to the same ip:ip_instance:ring will be executed in 1039 * order. 1040 * 1041 * The caller can specify the user fence buffer/location with the fence_info in the 1042 * cs_request.The sequence number is returned via the 'seq_no' parameter 1043 * in ibs_request structure. 1044 * 1045 * 1046 * \param dev - \c [in] Device handle. 1047 * See #amdgpu_device_initialize() 1048 * \param context - \c [in] GPU Context 1049 * \param flags - \c [in] Global submission flags 1050 * \param ibs_request - \c [in/out] Pointer to submission requests. 1051 * We could submit to the several 1052 * engines/rings simulteniously as 1053 * 'atomic' operation 1054 * \param number_of_requests - \c [in] Number of submission requests 1055 * 1056 * \return 0 on success\n 1057 * <0 - Negative POSIX Error code 1058 * 1059 * \note It is required to pass correct resource list with buffer handles 1060 * which will be accessible by command buffers from submission 1061 * This will allow kernel driver to correctly implement "paging". 1062 * Failure to do so will have unpredictable results. 1063 * 1064 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), 1065 * amdgpu_cs_query_fence_status() 1066 * 1067 */ 1068 int amdgpu_cs_submit(amdgpu_context_handle context, 1069 uint64_t flags, 1070 struct amdgpu_cs_request *ibs_request, 1071 uint32_t number_of_requests); 1072 1073 /** 1074 * Query status of Command Buffer Submission 1075 * 1076 * \param fence - \c [in] Structure describing fence to query 1077 * \param timeout_ns - \c [in] Timeout value to wait 1078 * \param flags - \c [in] Flags for the query 1079 * \param expired - \c [out] If fence expired or not.\n 1080 * 0 if fence is not expired\n 1081 * !0 - otherwise 1082 * 1083 * \return 0 on success\n 1084 * <0 - Negative POSIX Error code 1085 * 1086 * \note If UMD wants only to check operation status and returned immediately 1087 * then timeout value as 0 must be passed. In this case success will be 1088 * returned in the case if submission was completed or timeout error 1089 * code. 1090 * 1091 * \sa amdgpu_cs_submit() 1092 */ 1093 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 1094 uint64_t timeout_ns, 1095 uint64_t flags, 1096 uint32_t *expired); 1097 1098 /** 1099 * Wait for multiple fences 1100 * 1101 * \param fences - \c [in] The fence array to wait 1102 * \param fence_count - \c [in] The fence count 1103 * \param wait_all - \c [in] If true, wait all fences to be signaled, 1104 * otherwise, wait at least one fence 1105 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 1106 * \param status - \c [out] '1' for signaled, '0' for timeout 1107 * \param first - \c [out] the index of the first signaled fence from @fences 1108 * 1109 * \return 0 on success 1110 * <0 - Negative POSIX Error code 1111 * 1112 * \note Currently it supports only one amdgpu_device. All fences come from 1113 * the same amdgpu_device with the same fd. 1114 */ 1115 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 1116 uint32_t fence_count, 1117 bool wait_all, 1118 uint64_t timeout_ns, 1119 uint32_t *status, uint32_t *first); 1120 1121 /* 1122 * Query / Info API 1123 * 1124 */ 1125 1126 /** 1127 * Query allocation size alignments 1128 * 1129 * UMD should query information about GPU VM MC size alignments requirements 1130 * to be able correctly choose required allocation size and implement 1131 * internal optimization if needed. 1132 * 1133 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1134 * \param info - \c [out] Pointer to structure to get size alignment 1135 * requirements 1136 * 1137 * \return 0 on success\n 1138 * <0 - Negative POSIX Error code 1139 * 1140 */ 1141 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, 1142 struct amdgpu_buffer_size_alignments 1143 *info); 1144 1145 /** 1146 * Query firmware versions 1147 * 1148 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1149 * \param fw_type - \c [in] AMDGPU_INFO_FW_* 1150 * \param ip_instance - \c [in] Index of the IP block of the same type. 1151 * \param index - \c [in] Index of the engine. (for SDMA and MEC) 1152 * \param version - \c [out] Pointer to to the "version" return value 1153 * \param feature - \c [out] Pointer to to the "feature" return value 1154 * 1155 * \return 0 on success\n 1156 * <0 - Negative POSIX Error code 1157 * 1158 */ 1159 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, 1160 unsigned ip_instance, unsigned index, 1161 uint32_t *version, uint32_t *feature); 1162 1163 /** 1164 * Query the number of HW IP instances of a certain type. 1165 * 1166 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1167 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1168 * \param count - \c [out] Pointer to structure to get information 1169 * 1170 * \return 0 on success\n 1171 * <0 - Negative POSIX Error code 1172 */ 1173 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, 1174 uint32_t *count); 1175 1176 /** 1177 * Query engine information 1178 * 1179 * This query allows UMD to query information different engines and their 1180 * capabilities. 1181 * 1182 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1183 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1184 * \param ip_instance - \c [in] Index of the IP block of the same type. 1185 * \param info - \c [out] Pointer to structure to get information 1186 * 1187 * \return 0 on success\n 1188 * <0 - Negative POSIX Error code 1189 */ 1190 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, 1191 unsigned ip_instance, 1192 struct drm_amdgpu_info_hw_ip *info); 1193 1194 /** 1195 * Query FW area related information. 1196 * 1197 * The return size is query-specific and depends on the "type" parameter. 1198 * No more than "size" bytes is returned. 1199 * 1200 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1201 * \param type - \c [in] AMDGPU_HW_IP_* 1202 * \param ip_instance - \c [in] HW IP index. 1203 * \param info - \c [out] The pointer to return value 1204 * 1205 * \return 0 on success\n 1206 * <0 - Negative POSIX error code 1207 * 1208 */ 1209 int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev, 1210 unsigned type, 1211 unsigned ip_instance, 1212 struct drm_amdgpu_info_uq_fw_areas *info); 1213 1214 /** 1215 * Query heap information 1216 * 1217 * This query allows UMD to query potentially available memory resources and 1218 * adjust their logic if necessary. 1219 * 1220 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1221 * \param heap - \c [in] Heap type 1222 * \param info - \c [in] Pointer to structure to get needed information 1223 * 1224 * \return 0 on success\n 1225 * <0 - Negative POSIX Error code 1226 * 1227 */ 1228 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, 1229 uint32_t flags, struct amdgpu_heap_info *info); 1230 1231 /** 1232 * Get the CRTC ID from the mode object ID 1233 * 1234 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1235 * \param id - \c [in] Mode object ID 1236 * \param result - \c [in] Pointer to the CRTC ID 1237 * 1238 * \return 0 on success\n 1239 * <0 - Negative POSIX Error code 1240 * 1241 */ 1242 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 1243 int32_t *result); 1244 1245 /** 1246 * Query GPU H/w Info 1247 * 1248 * Query hardware specific information 1249 * 1250 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1251 * \param heap - \c [in] Heap type 1252 * \param info - \c [in] Pointer to structure to get needed information 1253 * 1254 * \return 0 on success\n 1255 * <0 - Negative POSIX Error code 1256 * 1257 */ 1258 int amdgpu_query_gpu_info(amdgpu_device_handle dev, 1259 struct amdgpu_gpu_info *info); 1260 1261 /** 1262 * Query hardware or driver information. 1263 * 1264 * The return size is query-specific and depends on the "info_id" parameter. 1265 * No more than "size" bytes is returned. 1266 * 1267 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1268 * \param info_id - \c [in] AMDGPU_INFO_* 1269 * \param size - \c [in] Size of the returned value. 1270 * \param value - \c [out] Pointer to the return value. 1271 * 1272 * \return 0 on success\n 1273 * <0 - Negative POSIX error code 1274 * 1275 */ 1276 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 1277 unsigned size, void *value); 1278 1279 /** 1280 * Query hardware or driver information. 1281 * 1282 * The return size is query-specific and depends on the "info_id" parameter. 1283 * No more than "size" bytes is returned. 1284 * 1285 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1286 * \param info - \c [in] amdgpu_sw_info_* 1287 * \param value - \c [out] Pointer to the return value. 1288 * 1289 * \return 0 on success\n 1290 * <0 - Negative POSIX error code 1291 * 1292 */ 1293 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, 1294 void *value); 1295 1296 /** 1297 * Query information about GDS 1298 * 1299 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1300 * \param gds_info - \c [out] Pointer to structure to get GDS information 1301 * 1302 * \return 0 on success\n 1303 * <0 - Negative POSIX Error code 1304 * 1305 */ 1306 int amdgpu_query_gds_info(amdgpu_device_handle dev, 1307 struct amdgpu_gds_resource_info *gds_info); 1308 1309 /** 1310 * Query information about sensor. 1311 * 1312 * The return size is query-specific and depends on the "sensor_type" 1313 * parameter. No more than "size" bytes is returned. 1314 * 1315 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1316 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* 1317 * \param size - \c [in] Size of the returned value. 1318 * \param value - \c [out] Pointer to the return value. 1319 * 1320 * \return 0 on success\n 1321 * <0 - Negative POSIX Error code 1322 * 1323 */ 1324 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, 1325 unsigned size, void *value); 1326 1327 /** 1328 * Query information about video capabilities 1329 * 1330 * The return sizeof(struct drm_amdgpu_info_video_caps) 1331 * 1332 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1333 * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) 1334 * \param size - \c [in] Size of the returned value. 1335 * \param value - \c [out] Pointer to the return value. 1336 * 1337 * \return 0 on success\n 1338 * <0 - Negative POSIX Error code 1339 * 1340 */ 1341 int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, 1342 unsigned size, void *value); 1343 1344 /** 1345 * Query information about VM faults 1346 * 1347 * The return sizeof(struct drm_amdgpu_info_gpuvm_fault) 1348 * 1349 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1350 * \param size - \c [in] Size of the returned value. 1351 * \param value - \c [out] Pointer to the return value. 1352 * 1353 * \return 0 on success\n 1354 * <0 - Negative POSIX Error code 1355 * 1356 */ 1357 int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev, unsigned size, 1358 void *value); 1359 1360 /** 1361 * Read a set of consecutive memory-mapped registers. 1362 * Not all registers are allowed to be read by userspace. 1363 * 1364 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( 1365 * \param dword_offset - \c [in] Register offset in dwords 1366 * \param count - \c [in] The number of registers to read starting 1367 * from the offset 1368 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other 1369 * uses. Set it to 0xffffffff if unsure. 1370 * \param flags - \c [in] Flags with additional information. 1371 * \param values - \c [out] The pointer to return values. 1372 * 1373 * \return 0 on success\n 1374 * <0 - Negative POSIX error code 1375 * 1376 */ 1377 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, 1378 unsigned count, uint32_t instance, uint32_t flags, 1379 uint32_t *values); 1380 1381 /** 1382 * Flag to request VA address range in the 32bit address space 1383 */ 1384 #define AMDGPU_VA_RANGE_32_BIT 0x1 1385 #define AMDGPU_VA_RANGE_HIGH 0x2 1386 #define AMDGPU_VA_RANGE_REPLAYABLE 0x4 1387 1388 /** 1389 * Allocate virtual address range 1390 * 1391 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1392 * \param va_range_type - \c [in] Type of MC va range from which to allocate 1393 * \param size - \c [in] Size of range. Size must be correctly* aligned. 1394 * It is client responsibility to correctly aligned size based on the future 1395 * usage of allocated range. 1396 * \param va_base_alignment - \c [in] Overwrite base address alignment 1397 * requirement for GPU VM MC virtual 1398 * address assignment. Must be multiple of size alignments received as 1399 * 'amdgpu_buffer_size_alignments'. 1400 * If 0 use the default one. 1401 * \param va_base_required - \c [in] Specified required va base address. 1402 * If 0 then library choose available one. 1403 * If !0 value will be passed and those value already "in use" then 1404 * corresponding error status will be returned. 1405 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used 1406 * by client. 1407 * \param va_range_handle - \c [out] On return: Handle assigned to allocation 1408 * \param flags - \c [in] flags for special VA range 1409 * 1410 * \return 0 on success\n 1411 * >0 - AMD specific error code\n 1412 * <0 - Negative POSIX Error code 1413 * 1414 * \notes \n 1415 * It is client responsibility to correctly handle VA assignments and usage. 1416 * Neither kernel driver nor libdrm_amdpgu are able to prevent and 1417 * detect wrong va assignment. 1418 * 1419 * It is client responsibility to correctly handle multi-GPU cases and to pass 1420 * the corresponding arrays of all devices handles where corresponding VA will 1421 * be used. 1422 * 1423 */ 1424 int amdgpu_va_range_alloc(amdgpu_device_handle dev, 1425 enum amdgpu_gpu_va_range va_range_type, 1426 uint64_t size, 1427 uint64_t va_base_alignment, 1428 uint64_t va_base_required, 1429 uint64_t *va_base_allocated, 1430 amdgpu_va_handle *va_range_handle, 1431 uint64_t flags); 1432 1433 /** 1434 * Free previously allocated virtual address range 1435 * 1436 * 1437 * \param va_range_handle - \c [in] Handle assigned to VA allocation 1438 * 1439 * \return 0 on success\n 1440 * >0 - AMD specific error code\n 1441 * <0 - Negative POSIX Error code 1442 * 1443 */ 1444 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle); 1445 1446 /** 1447 * Return the starting address of the allocated virtual address range. 1448 */ 1449 uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle); 1450 1451 /** 1452 * Query virtual address range 1453 * 1454 * UMD can query GPU VM range supported by each device 1455 * to initialize its own VAM accordingly. 1456 * 1457 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1458 * \param type - \c [in] Type of virtual address range 1459 * \param offset - \c [out] Start offset of virtual address range 1460 * \param size - \c [out] Size of virtual address range 1461 * 1462 * \return 0 on success\n 1463 * <0 - Negative POSIX Error code 1464 * 1465 */ 1466 1467 int amdgpu_va_range_query(amdgpu_device_handle dev, 1468 enum amdgpu_gpu_va_range type, 1469 uint64_t *start, 1470 uint64_t *end); 1471 1472 /** 1473 * Allocate a amdgpu_va_manager object. 1474 * The returned object has be initialized with the amdgpu_va_manager_init 1475 * before use. 1476 * On release, amdgpu_va_manager_deinit needs to be called, then the memory 1477 * can be released using free(). 1478 */ 1479 amdgpu_va_manager_handle amdgpu_va_manager_alloc(void); 1480 1481 void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr, 1482 uint64_t low_va_offset, uint64_t low_va_max, 1483 uint64_t high_va_offset, uint64_t high_va_max, 1484 uint32_t virtual_address_alignment); 1485 1486 #define AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT 0x1 1487 1488 void amdgpu_va_manager_init2(struct amdgpu_va_manager *va_mgr, 1489 uint64_t low_va_offset, uint64_t low_va_max, 1490 uint64_t high_va_offset, uint64_t high_va_max, 1491 uint32_t virtual_address_alignment, 1492 uint32_t flags); 1493 1494 void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr); 1495 1496 /** 1497 * Similar to #amdgpu_va_range_alloc() but allocates VA 1498 * directly from an amdgpu_va_manager_handle instead of using 1499 * the manager from an amdgpu_device. 1500 */ 1501 1502 int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr, 1503 enum amdgpu_gpu_va_range va_range_type, 1504 uint64_t size, 1505 uint64_t va_base_alignment, 1506 uint64_t va_base_required, 1507 uint64_t *va_base_allocated, 1508 amdgpu_va_handle *va_range_handle, 1509 uint64_t flags); 1510 1511 /** 1512 * Query VA manager information. 1513 * 1514 * \param va_mgr - \c [in] VA manager 1515 * \param info - \c [in] amdgpu_va_manager_sw_info_* 1516 * \param value - \c [out] Pointer to the return value. 1517 * 1518 * \return 0 on success\n 1519 * <0 - Negative POSIX error code 1520 * 1521 */ 1522 int amdgpu_va_manager_query_sw_info(struct amdgpu_va_manager *va_mgr, 1523 enum amdgpu_va_manager_sw_info info, 1524 void *value); 1525 1526 /** 1527 * VA mapping/unmapping for the buffer object 1528 * 1529 * \param bo - \c [in] BO handle 1530 * \param offset - \c [in] Start offset to map 1531 * \param size - \c [in] Size to map 1532 * \param addr - \c [in] Start virtual address. 1533 * \param flags - \c [in] Supported flags for mapping/unmapping 1534 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1535 * 1536 * \return 0 on success\n 1537 * <0 - Negative POSIX Error code 1538 * 1539 */ 1540 1541 int amdgpu_bo_va_op(amdgpu_bo_handle bo, 1542 uint64_t offset, 1543 uint64_t size, 1544 uint64_t addr, 1545 uint64_t flags, 1546 uint32_t ops); 1547 1548 /** 1549 * VA mapping/unmapping for a buffer object or PRT region. 1550 * 1551 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1552 * parameters are treated "raw", i.e. size is not automatically aligned, and 1553 * all flags must be specified explicitly. 1554 * 1555 * \param dev - \c [in] device handle 1556 * \param bo - \c [in] BO handle (may be NULL) 1557 * \param offset - \c [in] Start offset to map 1558 * \param size - \c [in] Size to map 1559 * \param addr - \c [in] Start virtual address. 1560 * \param flags - \c [in] Supported flags for mapping/unmapping 1561 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1562 * 1563 * \return 0 on success\n 1564 * <0 - Negative POSIX Error code 1565 * 1566 */ 1567 1568 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, 1569 amdgpu_bo_handle bo, 1570 uint64_t offset, 1571 uint64_t size, 1572 uint64_t addr, 1573 uint64_t flags, 1574 uint32_t ops); 1575 1576 /** 1577 * VA mapping/unmapping of buffer object for usermode queue. 1578 * 1579 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1580 * parameters are treated "raw2", i.e. size is not automatically aligned, and 1581 * all flags must be specified explicitly. 1582 * 1583 * \param dev - \c [in] device handle 1584 * \param bo - \c [in] BO handle (may be NULL) 1585 * \param offset - \c [in] Start offset to map 1586 * \param size - \c [in] Size to map 1587 * \param addr - \c [in] Start virtual address. 1588 * \param flags - \c [in] Supported flags for mapping/unmapping 1589 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1590 * \param vm_timeline_syncobj_out - \c [out] syncobj handle for PT update fence 1591 * \param vm_timeline_point - \c [in] input timeline point 1592 * \param input_fence_syncobj_handles - \c [in] Array of syncobj handles for bo unmap, 1593 * clear and replace 1594 * \param num_syncobj_handles - \c [in] Number of syncobj handles 1595 * 1596 * \return 0 on success\n 1597 * <0 - Negative POSIX Error code 1598 * 1599 */ 1600 int amdgpu_bo_va_op_raw2(amdgpu_device_handle dev, 1601 amdgpu_bo_handle bo, 1602 uint64_t offset, 1603 uint64_t size, 1604 uint64_t addr, 1605 uint64_t flags, 1606 uint32_t ops, 1607 uint32_t vm_timeline_syncobj_out, 1608 uint64_t vm_timeline_point, 1609 uint64_t input_fence_syncobj_array_in, 1610 uint32_t num_syncobj_handles_in); 1611 1612 /** 1613 * create semaphore 1614 * 1615 * \param sem - \c [out] semaphore handle 1616 * 1617 * \return 0 on success\n 1618 * <0 - Negative POSIX Error code 1619 * 1620 */ 1621 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); 1622 1623 /** 1624 * signal semaphore 1625 * 1626 * \param context - \c [in] GPU Context 1627 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1628 * \param ip_instance - \c [in] Index of the IP block of the same type 1629 * \param ring - \c [in] Specify ring index of the IP 1630 * \param sem - \c [in] semaphore handle 1631 * 1632 * \return 0 on success\n 1633 * <0 - Negative POSIX Error code 1634 * 1635 */ 1636 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, 1637 uint32_t ip_type, 1638 uint32_t ip_instance, 1639 uint32_t ring, 1640 amdgpu_semaphore_handle sem); 1641 1642 /** 1643 * wait semaphore 1644 * 1645 * \param context - \c [in] GPU Context 1646 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1647 * \param ip_instance - \c [in] Index of the IP block of the same type 1648 * \param ring - \c [in] Specify ring index of the IP 1649 * \param sem - \c [in] semaphore handle 1650 * 1651 * \return 0 on success\n 1652 * <0 - Negative POSIX Error code 1653 * 1654 */ 1655 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, 1656 uint32_t ip_type, 1657 uint32_t ip_instance, 1658 uint32_t ring, 1659 amdgpu_semaphore_handle sem); 1660 1661 /** 1662 * destroy semaphore 1663 * 1664 * \param sem - \c [in] semaphore handle 1665 * 1666 * \return 0 on success\n 1667 * <0 - Negative POSIX Error code 1668 * 1669 */ 1670 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); 1671 1672 /** 1673 * Get the ASIC marketing name 1674 * 1675 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1676 * 1677 * \return the constant string of the marketing name 1678 * "NULL" means the ASIC is not found 1679 */ 1680 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); 1681 1682 /** 1683 * Create kernel sync object 1684 * 1685 * \param dev - \c [in] device handle 1686 * \param flags - \c [in] flags that affect creation 1687 * \param syncobj - \c [out] sync object handle 1688 * 1689 * \return 0 on success\n 1690 * <0 - Negative POSIX Error code 1691 * 1692 */ 1693 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, 1694 uint32_t flags, 1695 uint32_t *syncobj); 1696 1697 /** 1698 * Create kernel sync object 1699 * 1700 * \param dev - \c [in] device handle 1701 * \param syncobj - \c [out] sync object handle 1702 * 1703 * \return 0 on success\n 1704 * <0 - Negative POSIX Error code 1705 * 1706 */ 1707 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, 1708 uint32_t *syncobj); 1709 /** 1710 * Destroy kernel sync object 1711 * 1712 * \param dev - \c [in] device handle 1713 * \param syncobj - \c [in] sync object handle 1714 * 1715 * \return 0 on success\n 1716 * <0 - Negative POSIX Error code 1717 * 1718 */ 1719 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, 1720 uint32_t syncobj); 1721 1722 /** 1723 * Reset kernel sync objects to unsignalled state. 1724 * 1725 * \param dev - \c [in] device handle 1726 * \param syncobjs - \c [in] array of sync object handles 1727 * \param syncobj_count - \c [in] number of handles in syncobjs 1728 * 1729 * \return 0 on success\n 1730 * <0 - Negative POSIX Error code 1731 * 1732 */ 1733 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, 1734 const uint32_t *syncobjs, uint32_t syncobj_count); 1735 1736 /** 1737 * Signal kernel sync objects. 1738 * 1739 * \param dev - \c [in] device handle 1740 * \param syncobjs - \c [in] array of sync object handles 1741 * \param syncobj_count - \c [in] number of handles in syncobjs 1742 * 1743 * \return 0 on success\n 1744 * <0 - Negative POSIX Error code 1745 * 1746 */ 1747 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, 1748 const uint32_t *syncobjs, uint32_t syncobj_count); 1749 1750 /** 1751 * Signal kernel timeline sync objects. 1752 * 1753 * \param dev - \c [in] device handle 1754 * \param syncobjs - \c [in] array of sync object handles 1755 * \param points - \c [in] array of timeline points 1756 * \param syncobj_count - \c [in] number of handles in syncobjs 1757 * 1758 * \return 0 on success\n 1759 * <0 - Negative POSIX Error code 1760 * 1761 */ 1762 int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev, 1763 const uint32_t *syncobjs, 1764 uint64_t *points, 1765 uint32_t syncobj_count); 1766 1767 /** 1768 * Wait for one or all sync objects to signal. 1769 * 1770 * \param dev - \c [in] self-explanatory 1771 * \param handles - \c [in] array of sync object handles 1772 * \param num_handles - \c [in] self-explanatory 1773 * \param timeout_nsec - \c [in] self-explanatory 1774 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1775 * \param first_signaled - \c [in] self-explanatory 1776 * 1777 * \return 0 on success\n 1778 * -ETIME - Timeout 1779 * <0 - Negative POSIX Error code 1780 * 1781 */ 1782 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, 1783 uint32_t *handles, unsigned num_handles, 1784 int64_t timeout_nsec, unsigned flags, 1785 uint32_t *first_signaled); 1786 1787 /** 1788 * Wait for one or all sync objects on their points to signal. 1789 * 1790 * \param dev - \c [in] self-explanatory 1791 * \param handles - \c [in] array of sync object handles 1792 * \param points - \c [in] array of sync points to wait 1793 * \param num_handles - \c [in] self-explanatory 1794 * \param timeout_nsec - \c [in] self-explanatory 1795 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1796 * \param first_signaled - \c [in] self-explanatory 1797 * 1798 * \return 0 on success\n 1799 * -ETIME - Timeout 1800 * <0 - Negative POSIX Error code 1801 * 1802 */ 1803 int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev, 1804 uint32_t *handles, uint64_t *points, 1805 unsigned num_handles, 1806 int64_t timeout_nsec, unsigned flags, 1807 uint32_t *first_signaled); 1808 /** 1809 * Query sync objects payloads. 1810 * 1811 * \param dev - \c [in] self-explanatory 1812 * \param handles - \c [in] array of sync object handles 1813 * \param points - \c [out] array of sync points returned, which presents 1814 * syncobj payload. 1815 * \param num_handles - \c [in] self-explanatory 1816 * 1817 * \return 0 on success\n 1818 * -ETIME - Timeout 1819 * <0 - Negative POSIX Error code 1820 * 1821 */ 1822 int amdgpu_cs_syncobj_query(amdgpu_device_handle dev, 1823 uint32_t *handles, uint64_t *points, 1824 unsigned num_handles); 1825 /** 1826 * Query sync objects last signaled or submitted point. 1827 * 1828 * \param dev - \c [in] self-explanatory 1829 * \param handles - \c [in] array of sync object handles 1830 * \param points - \c [out] array of sync points returned, which presents 1831 * syncobj payload. 1832 * \param num_handles - \c [in] self-explanatory 1833 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_* 1834 * 1835 * \return 0 on success\n 1836 * -ETIME - Timeout 1837 * <0 - Negative POSIX Error code 1838 * 1839 */ 1840 int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev, 1841 uint32_t *handles, uint64_t *points, 1842 unsigned num_handles, uint32_t flags); 1843 1844 /** 1845 * Export kernel sync object to shareable fd. 1846 * 1847 * \param dev - \c [in] device handle 1848 * \param syncobj - \c [in] sync object handle 1849 * \param shared_fd - \c [out] shared file descriptor. 1850 * 1851 * \return 0 on success\n 1852 * <0 - Negative POSIX Error code 1853 * 1854 */ 1855 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, 1856 uint32_t syncobj, 1857 int *shared_fd); 1858 /** 1859 * Import kernel sync object from shareable fd. 1860 * 1861 * \param dev - \c [in] device handle 1862 * \param shared_fd - \c [in] shared file descriptor. 1863 * \param syncobj - \c [out] sync object handle 1864 * 1865 * \return 0 on success\n 1866 * <0 - Negative POSIX Error code 1867 * 1868 */ 1869 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, 1870 int shared_fd, 1871 uint32_t *syncobj); 1872 1873 /** 1874 * Export kernel sync object to a sync_file. 1875 * 1876 * \param dev - \c [in] device handle 1877 * \param syncobj - \c [in] sync object handle 1878 * \param sync_file_fd - \c [out] sync_file file descriptor. 1879 * 1880 * \return 0 on success\n 1881 * <0 - Negative POSIX Error code 1882 * 1883 */ 1884 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, 1885 uint32_t syncobj, 1886 int *sync_file_fd); 1887 1888 /** 1889 * Import kernel sync object from a sync_file. 1890 * 1891 * \param dev - \c [in] device handle 1892 * \param syncobj - \c [in] sync object handle 1893 * \param sync_file_fd - \c [in] sync_file file descriptor. 1894 * 1895 * \return 0 on success\n 1896 * <0 - Negative POSIX Error code 1897 * 1898 */ 1899 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, 1900 uint32_t syncobj, 1901 int sync_file_fd); 1902 /** 1903 * Export kernel timeline sync object to a sync_file. 1904 * 1905 * \param dev - \c [in] device handle 1906 * \param syncobj - \c [in] sync object handle 1907 * \param point - \c [in] timeline point 1908 * \param flags - \c [in] flags 1909 * \param sync_file_fd - \c [out] sync_file file descriptor. 1910 * 1911 * \return 0 on success\n 1912 * <0 - Negative POSIX Error code 1913 * 1914 */ 1915 int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev, 1916 uint32_t syncobj, 1917 uint64_t point, 1918 uint32_t flags, 1919 int *sync_file_fd); 1920 1921 /** 1922 * Import kernel timeline sync object from a sync_file. 1923 * 1924 * \param dev - \c [in] device handle 1925 * \param syncobj - \c [in] sync object handle 1926 * \param point - \c [in] timeline point 1927 * \param sync_file_fd - \c [in] sync_file file descriptor. 1928 * 1929 * \return 0 on success\n 1930 * <0 - Negative POSIX Error code 1931 * 1932 */ 1933 int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev, 1934 uint32_t syncobj, 1935 uint64_t point, 1936 int sync_file_fd); 1937 1938 /** 1939 * transfer between syncbojs. 1940 * 1941 * \param dev - \c [in] device handle 1942 * \param dst_handle - \c [in] sync object handle 1943 * \param dst_point - \c [in] timeline point, 0 presents dst is binary 1944 * \param src_handle - \c [in] sync object handle 1945 * \param src_point - \c [in] timeline point, 0 presents src is binary 1946 * \param flags - \c [in] flags 1947 * 1948 * \return 0 on success\n 1949 * <0 - Negative POSIX Error code 1950 * 1951 */ 1952 int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev, 1953 uint32_t dst_handle, 1954 uint64_t dst_point, 1955 uint32_t src_handle, 1956 uint64_t src_point, 1957 uint32_t flags); 1958 1959 /** 1960 * Export an amdgpu fence as a handle (syncobj or fd). 1961 * 1962 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD} 1963 * \param out_handle returned handle 1964 * 1965 * \return 0 on success\n 1966 * <0 - Negative POSIX Error code 1967 */ 1968 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, 1969 struct amdgpu_cs_fence *fence, 1970 uint32_t what, 1971 uint32_t *out_handle); 1972 1973 /** 1974 * Submit raw command submission to kernel 1975 * 1976 * \param dev - \c [in] device handle 1977 * \param context - \c [in] context handle for context id 1978 * \param bo_list_handle - \c [in] request bo list handle (0 for none) 1979 * \param num_chunks - \c [in] number of CS chunks to submit 1980 * \param chunks - \c [in] array of CS chunks 1981 * \param seq_no - \c [out] output sequence number for submission. 1982 * 1983 * \return 0 on success\n 1984 * <0 - Negative POSIX Error code 1985 * 1986 */ 1987 struct drm_amdgpu_cs_chunk; 1988 struct drm_amdgpu_cs_chunk_dep; 1989 struct drm_amdgpu_cs_chunk_data; 1990 1991 int amdgpu_cs_submit_raw(amdgpu_device_handle dev, 1992 amdgpu_context_handle context, 1993 amdgpu_bo_list_handle bo_list_handle, 1994 int num_chunks, 1995 struct drm_amdgpu_cs_chunk *chunks, 1996 uint64_t *seq_no); 1997 1998 /** 1999 * Submit raw command submission to the kernel with a raw BO list handle. 2000 * 2001 * \param dev - \c [in] device handle 2002 * \param context - \c [in] context handle for context id 2003 * \param bo_list_handle - \c [in] raw bo list handle (0 for none) 2004 * \param num_chunks - \c [in] number of CS chunks to submit 2005 * \param chunks - \c [in] array of CS chunks 2006 * \param seq_no - \c [out] output sequence number for submission. 2007 * 2008 * \return 0 on success\n 2009 * <0 - Negative POSIX Error code 2010 * 2011 * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw() 2012 */ 2013 int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, 2014 amdgpu_context_handle context, 2015 uint32_t bo_list_handle, 2016 int num_chunks, 2017 struct drm_amdgpu_cs_chunk *chunks, 2018 uint64_t *seq_no); 2019 2020 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, 2021 struct drm_amdgpu_cs_chunk_dep *dep); 2022 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, 2023 struct drm_amdgpu_cs_chunk_data *data); 2024 2025 /** 2026 * Reserve VMID 2027 * \param context - \c [in] GPU Context 2028 * \param flags - \c [in] TBD 2029 * 2030 * \return 0 on success otherwise POSIX Error code 2031 */ 2032 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); 2033 2034 /** 2035 * Free reserved VMID 2036 * \param context - \c [in] GPU Context 2037 * \param flags - \c [in] TBD 2038 * 2039 * \return 0 on success otherwise POSIX Error code 2040 */ 2041 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); 2042 2043 /** 2044 * Create USERQUEUE 2045 * \param dev - \c [in] device handle 2046 * \param ip_type - \c [in] ip type 2047 * \param doorbell_handle - \c [in] doorbell handle 2048 * \param doorbell_offset - \c [in] doorbell index 2049 * \param mqd_in - \c [in] MQD data 2050 * \param queue_va - \c [in] Virtual address of queue 2051 * \param queue_size - \c [in] userqueue size 2052 * \param wptr_va - \c [in] Virtual address of wptr 2053 * \param rptr_va - \c [in] Virtual address of rptr 2054 * \param queue_id - \c [out] queue id 2055 * 2056 * \return 0 on success otherwise POSIX Error code 2057 */ 2058 2059 int amdgpu_create_userqueue(amdgpu_device_handle dev, 2060 uint32_t ip_type, 2061 uint32_t doorbell_handle, 2062 uint32_t doorbell_offset, 2063 uint64_t queue_va, 2064 uint64_t queue_size, 2065 uint64_t wptr_va, 2066 uint64_t rptr_va, 2067 void *mqd_in, 2068 uint32_t flags, 2069 uint32_t *queue_id); 2070 2071 /** 2072 * Free USERQUEUE 2073 * \param dev - \c [in] device handle 2074 * \param queue_id - \c [in] queue id 2075 * 2076 * \return 0 on success otherwise POSIX Error code 2077 */ 2078 int amdgpu_free_userqueue(amdgpu_device_handle dev, uint32_t queue_id); 2079 2080 /** 2081 * Signal USERQUEUE 2082 * \param dev - \c [in] device handle 2083 * \param signal_data - \c [in] pointer to struct drm_amdgpu_userq_signal 2084 * to be filled by the caller 2085 * 2086 * \return 0 on success otherwise POSIX Error code 2087 */ 2088 int amdgpu_userq_signal(amdgpu_device_handle dev, 2089 struct drm_amdgpu_userq_signal *signal_data); 2090 2091 /** 2092 * Wait USERQUEUE 2093 * \param dev - \c [in] device handle 2094 * \param wait_data - \c [in/out] pointer to struct drm_amdgpu_userq_wait 2095 * to be filled by the caller 2096 * 2097 * \return 0 on success otherwise POSIX Error code 2098 */ 2099 int amdgpu_userq_wait(amdgpu_device_handle dev, 2100 struct drm_amdgpu_userq_wait *wait_data); 2101 2102 #ifdef __cplusplus 2103 } 2104 #endif 2105 #endif /* #ifdef _AMDGPU_H_ */ 2106
Indexes created Mon Aug 03 00:25:36 UTC 2026