1 /* $NetBSD: kfd_dbgdev.h,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef KFD_DBGDEV_H_ 26 #define KFD_DBGDEV_H_ 27 28 enum { 29 SQ_CMD_VMID_OFFSET = 28, 30 ADDRESS_WATCH_CNTL_OFFSET = 24 31 }; 32 33 enum { 34 PRIV_QUEUE_SYNC_TIME_MS = 200 35 }; 36 37 /* CONTEXT reg space definition */ 38 enum { 39 CONTEXT_REG_BASE = 0xA000, 40 CONTEXT_REG_END = 0xA400, 41 CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE 42 }; 43 44 /* USER CONFIG reg space definition */ 45 enum { 46 USERCONFIG_REG_BASE = 0xC000, 47 USERCONFIG_REG_END = 0x10000, 48 USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE 49 }; 50 51 /* CONFIG reg space definition */ 52 enum { 53 AMD_CONFIG_REG_BASE = 0x2000, /* in dwords */ 54 AMD_CONFIG_REG_END = 0x2B00, 55 AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE 56 }; 57 58 /* SH reg space definition */ 59 enum { 60 SH_REG_BASE = 0x2C00, 61 SH_REG_END = 0x3000, 62 SH_REG_SIZE = SH_REG_END - SH_REG_BASE 63 }; 64 65 /* SQ_CMD definitions */ 66 #define SQ_CMD 0x8DEC 67 68 enum SQ_IND_CMD_CMD { 69 SQ_IND_CMD_CMD_NULL = 0x00000000, 70 SQ_IND_CMD_CMD_HALT = 0x00000001, 71 SQ_IND_CMD_CMD_RESUME = 0x00000002, 72 SQ_IND_CMD_CMD_KILL = 0x00000003, 73 SQ_IND_CMD_CMD_DEBUG = 0x00000004, 74 SQ_IND_CMD_CMD_TRAP = 0x00000005, 75 }; 76 77 enum SQ_IND_CMD_MODE { 78 SQ_IND_CMD_MODE_SINGLE = 0x00000000, 79 SQ_IND_CMD_MODE_BROADCAST = 0x00000001, 80 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, 81 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, 82 SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, 83 }; 84 85 union SQ_IND_INDEX_BITS { 86 struct { 87 uint32_t wave_id:4; 88 uint32_t simd_id:2; 89 uint32_t thread_id:6; 90 uint32_t:1; 91 uint32_t force_read:1; 92 uint32_t read_timeout:1; 93 uint32_t unindexed:1; 94 uint32_t index:16; 95 96 } bitfields, bits; 97 uint32_t u32All; 98 signed int i32All; 99 float f32All; 100 }; 101 102 union SQ_IND_CMD_BITS { 103 struct { 104 uint32_t data:32; 105 } bitfields, bits; 106 uint32_t u32All; 107 signed int i32All; 108 float f32All; 109 }; 110 111 union SQ_CMD_BITS { 112 struct { 113 uint32_t cmd:3; 114 uint32_t:1; 115 uint32_t mode:3; 116 uint32_t check_vmid:1; 117 uint32_t trap_id:3; 118 uint32_t:5; 119 uint32_t wave_id:4; 120 uint32_t simd_id:2; 121 uint32_t:2; 122 uint32_t queue_id:3; 123 uint32_t:1; 124 uint32_t vm_id:4; 125 } bitfields, bits; 126 uint32_t u32All; 127 signed int i32All; 128 float f32All; 129 }; 130 131 union SQ_IND_DATA_BITS { 132 struct { 133 uint32_t data:32; 134 } bitfields, bits; 135 uint32_t u32All; 136 signed int i32All; 137 float f32All; 138 }; 139 140 union GRBM_GFX_INDEX_BITS { 141 struct { 142 uint32_t instance_index:8; 143 uint32_t sh_index:8; 144 uint32_t se_index:8; 145 uint32_t:5; 146 uint32_t sh_broadcast_writes:1; 147 uint32_t instance_broadcast_writes:1; 148 uint32_t se_broadcast_writes:1; 149 } bitfields, bits; 150 uint32_t u32All; 151 signed int i32All; 152 float f32All; 153 }; 154 155 union TCP_WATCH_ADDR_H_BITS { 156 struct { 157 uint32_t addr:16; 158 uint32_t:16; 159 160 } bitfields, bits; 161 uint32_t u32All; 162 signed int i32All; 163 float f32All; 164 }; 165 166 union TCP_WATCH_ADDR_L_BITS { 167 struct { 168 uint32_t:6; 169 uint32_t addr:26; 170 } bitfields, bits; 171 uint32_t u32All; 172 signed int i32All; 173 float f32All; 174 }; 175 176 enum { 177 QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */ 178 QUEUESTATE__ACTIVE_COMPLETION_PENDING, 179 QUEUESTATE__ACTIVE 180 }; 181 182 union ULARGE_INTEGER { 183 struct { 184 uint32_t low_part; 185 uint32_t high_part; 186 } u; 187 unsigned long long quad_part; 188 }; 189 190 191 #define KFD_CIK_VMID_START_OFFSET (8) 192 #define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8)) 193 194 195 void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, 196 enum DBGDEV_TYPE type); 197 198 union TCP_WATCH_CNTL_BITS { 199 struct { 200 uint32_t mask:24; 201 uint32_t vmid:4; 202 uint32_t atc:1; 203 uint32_t mode:2; 204 uint32_t valid:1; 205 } bitfields, bits; 206 uint32_t u32All; 207 signed int i32All; 208 float f32All; 209 }; 210 211 enum { 212 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, 213 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, 214 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, 215 /* extend the mask to 26 bits in order to match the low address field */ 216 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, 217 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF 218 }; 219 220 enum { 221 MAX_TRAPID = 8, /* 3 bits in the bitfield. */ 222 MAX_WATCH_ADDRESSES = 4 223 }; 224 225 enum { 226 ADDRESS_WATCH_REG_ADDR_HI = 0, 227 ADDRESS_WATCH_REG_ADDR_LO, 228 ADDRESS_WATCH_REG_CNTL, 229 ADDRESS_WATCH_REG_MAX 230 }; 231 232 #endif /* KFD_DBGDEV_H_ */ 233
Indexes created Sun Sep 21 20:09:37 GMT 2025