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      1 //===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
      2 //
      3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
      4 // See https://llvm.org/LICENSE.txt for license information.
      5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
      6 //
      7 //===----------------------------------------------------------------------===//
      8 //
      9 // This file defines the ARM subclass for SelectionDAGTargetInfo.
     10 //
     11 //===----------------------------------------------------------------------===//
     12 
     13 #ifndef LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
     14 #define LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
     15 
     16 #include "MCTargetDesc/ARMAddressingModes.h"
     17 #include "llvm/CodeGen/RuntimeLibcalls.h"
     18 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
     19 
     20 namespace llvm {
     21 
     22 namespace ARM_AM {
     23   static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
     24     switch (Opcode) {
     25     default:          return ARM_AM::no_shift;
     26     case ISD::SHL:    return ARM_AM::lsl;
     27     case ISD::SRL:    return ARM_AM::lsr;
     28     case ISD::SRA:    return ARM_AM::asr;
     29     case ISD::ROTR:   return ARM_AM::ror;
     30     //case ISD::ROTL:  // Only if imm -> turn into ROTR.
     31     // Can't handle RRX here, because it would require folding a flag into
     32     // the addressing mode.  :(  This causes us to miss certain things.
     33     //case ARMISD::RRX: return ARM_AM::rrx;
     34     }
     35   }
     36 }  // end namespace ARM_AM
     37 
     38 class ARMSelectionDAGInfo : public SelectionDAGTargetInfo {
     39 public:
     40   SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
     41                                   SDValue Chain, SDValue Dst, SDValue Src,
     42                                   SDValue Size, Align Alignment,
     43                                   bool isVolatile, bool AlwaysInline,
     44                                   MachinePointerInfo DstPtrInfo,
     45                                   MachinePointerInfo SrcPtrInfo) const override;
     46 
     47   SDValue
     48   EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
     49                            SDValue Dst, SDValue Src, SDValue Size,
     50                            Align Alignment, bool isVolatile,
     51                            MachinePointerInfo DstPtrInfo,
     52                            MachinePointerInfo SrcPtrInfo) const override;
     53 
     54   // Adjust parameters for memset, see RTABI section 4.3.4
     55   SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
     56                                   SDValue Chain, SDValue Op1, SDValue Op2,
     57                                   SDValue Op3, Align Alignment, bool isVolatile,
     58                                   MachinePointerInfo DstPtrInfo) const override;
     59 
     60   SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl,
     61                                  SDValue Chain, SDValue Dst, SDValue Src,
     62                                  SDValue Size, unsigned Align,
     63                                  RTLIB::Libcall LC) const;
     64 };
     65 
     66 }
     67 
     68 #endif
     69