1 /* $NetBSD: advlib.h,v 1.22 2019/12/27 09:48:35 msaitoh Exp $ */ 2 3 /* 4 * Definitions for low level routines and data structures 5 * for the Advanced Systems Inc. SCSI controllers chips. 6 * 7 * Copyright (c) 1998 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante (at) mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from: 35 */ 36 /* 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-1996 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 */ 47 48 #ifndef _ADVANSYS_NARROW_LIBRARY_H_ 49 #define _ADVANSYS_NARROW_LIBRARY_H_ 50 51 52 struct adv_ccb; 53 54 /******************************************************************************/ 55 56 #define ADV_VERSION "3.1E" /* AdvanSys Driver Version */ 57 58 #define ASC_LIB_VERSION_MAJOR 1 59 #define ASC_LIB_VERSION_MINOR 22 60 #define ASC_LIB_SERIAL_NUMBER 113 61 62 63 #define ASC_NOERROR 1 64 #define ASC_BUSY 0 65 #define ASC_ERROR -1 66 67 68 #if BYTE_ORDER == BIG_ENDIAN 69 #define LO_BYTE(x) (*((u_int8_t *)(&(x))+1)) 70 #define HI_BYTE(x) (*((u_int8_t *)&(x))) 71 #define LO_WORD(x) (*((u_int16_t *)(&(x))+1)) 72 #define HI_WORD(x) (*((u_int16_t *)&(x))) 73 #else 74 #define HI_BYTE(x) (*((u_int8_t *)(&(x))+1)) 75 #define LO_BYTE(x) (*((u_int8_t *)&(x))) 76 #define HI_WORD(x) (*((u_int16_t *)(&(x))+1)) 77 #define LO_WORD(x) (*((u_int16_t *)&(x))) 78 #endif 79 80 #define MAKEWORD(lo, hi) ((u_int16_t) (((u_int16_t) (lo)) | \ 81 ((u_int16_t) (hi) << 8))) 82 83 #define MAKELONG(lo, hi) ((u_int32_t) (((u_int32_t) (lo)) | \ 84 ((u_int32_t) (hi) << 16))) 85 86 #define SWAPWORDS(dWord) ((u_int32_t) ((dWord) >> 16) | ((dWord) << 16)) 87 #define SWAPBYTES(word) ((u_int16_t) ((word) >> 8) | ((word) << 8)) 88 #define BIGTOLITTLE(dWord) (u_int32_t)(SWAPBYTES(SWAPWORDS(dWord) >> 16 ) << 16) | \ 89 SWAPBYTES(SWAPWORDS(dWord) & 0xFFFF) 90 #define LITTLETOBIG(dWord) BIGTOLITTLE(dWord) 91 92 93 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF) 94 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F) 95 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7) 96 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | \ 97 (((func) & 0x7) << 8) | ((bus) & 0xFF)) 98 #define ASC_PCI_REVISION_3150 0x02 99 #define ASC_PCI_REVISION_3050 0x03 100 101 102 #define ASC_MAX_SG_QUEUE 7 103 #define ASC_SG_LIST_PER_Q ASC_MAX_SG_QUEUE 104 #define ASC_MAX_SG_LIST (1 + ((ASC_SG_LIST_PER_Q) * \ 105 (ASC_MAX_SG_QUEUE))) /* SG_ALL */ 106 107 108 #define ASC_IS_ISA 0x0001 109 #define ASC_IS_ISAPNP 0x0081 110 #define ASC_IS_EISA 0x0002 111 #define ASC_IS_PCI 0x0004 112 #define ASC_IS_PCI_ULTRA 0x0104 113 #define ASC_IS_PCMCIA 0x0008 114 #define ASC_IS_MCA 0x0020 115 #define ASC_IS_VL 0x0040 116 117 118 #define ASC_ISA_PNP_PORT_ADDR 0x279 119 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800) 120 121 #define ASC_IS_WIDESCSI_16 0x0100 122 #define ASC_IS_WIDESCSI_32 0x0200 123 #define ASC_IS_BIG_ENDIAN 0x8000 124 125 126 #define ASC_CHIP_MIN_VER_VL 0x01 127 #define ASC_CHIP_MAX_VER_VL 0x07 128 #define ASC_CHIP_MIN_VER_PCI 0x09 129 #define ASC_CHIP_MAX_VER_PCI 0x0F 130 #define ASC_CHIP_VER_PCI_BIT 0x08 131 #define ASC_CHIP_MIN_VER_ISA 0x11 132 #define ASC_CHIP_MIN_VER_ISA_PNP 0x21 133 #define ASC_CHIP_MAX_VER_ISA 0x27 134 #define ASC_CHIP_VER_ISA_BIT 0x30 135 #define ASC_CHIP_VER_ISAPNP_BIT 0x20 136 #define ASC_CHIP_VER_ASYN_BUG 0x21 137 #define ASC_CHIP_VER_PCI 0x08 138 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) 139 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) 140 #define ASC_CHIP_MIN_VER_EISA 0x41 141 #define ASC_CHIP_MAX_VER_EISA 0x47 142 #define ASC_CHIP_VER_EISA_BIT 0x40 143 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) 144 145 146 #define ASC_MAX_VL_DMA_ADDR 0x07FFFFFFL 147 #define ASC_MAX_VL_DMA_COUNT 0x07FFFFFFL 148 #define ASC_MAX_PCI_DMA_ADDR 0xFFFFFFFFL 149 #define ASC_MAX_PCI_DMA_COUNT 0xFFFFFFFFL 150 #define ASC_MAX_ISA_DMA_ADDR 0x00FFFFFFL 151 #define ASC_MAX_ISA_DMA_COUNT 0x00FFFFFFL 152 #define ASC_MAX_EISA_DMA_ADDR 0x07FFFFFFL 153 #define ASC_MAX_EISA_DMA_COUNT 0x07FFFFFFL 154 155 156 #define ASC_SCSI_ID_BITS 3 157 #define ASC_SCSI_TIX_TYPE u_int8_t 158 159 #define ASC_ALL_DEVICE_BIT_SET 0xFF 160 161 #ifdef ASC_WIDESCSI_16 162 #undef ASC_SCSI_ID_BITS 163 #define ASC_SCSI_ID_BITS 4 164 #define ASC_ALL_DEVICE_BIT_SET 0xFFFF 165 #endif 166 167 #ifdef ASC_WIDESCSI_32 168 #undef ASC_SCSI_ID_BITS 169 #define ASC_SCSI_ID_BITS 5 170 #define ASC_ALL_DEVICE_BIT_SET 0xFFFFFFFFL 171 #endif 172 173 #if ASC_SCSI_ID_BITS == 3 174 #define ASC_SCSI_BIT_ID_TYPE u_int8_t 175 #define ASC_MAX_TID 7 176 #define ASC_MAX_LUN 7 177 #define ASC_SCSI_WIDTH_BIT_SET 0xFF 178 #elif ASC_SCSI_ID_BITS == 4 179 #define ASC_SCSI_BIT_ID_TYPE u_int16_t 180 #define ASC_MAX_TID 15 181 #define ASC_MAX_LUN 7 182 #define ASC_SCSI_WIDTH_BIT_SET 0xFFFF 183 #elif ASC_SCSI_ID_BITS == 5 184 #define ASC_SCSI_BIT_ID_TYPE u_int32_t 185 #define ASC_MAX_TID 31 186 #define ASC_MAX_LUN 7 187 #define ASC_SCSI_WIDTH_BIT_SET 0xFFFFFFFF 188 #else 189 #error ASC_SCSI_ID_BITS definition is wrong 190 #endif 191 192 193 #define ASC_MAX_SENSE_LEN 32 194 #define ASC_MIN_SENSE_LEN 14 195 #define ASC_MAX_CDB_LEN 12 196 197 #define ASC_SCSI_RESET_HOLD_TIME_US 60 198 199 200 #define SCSICMD_TestUnitReady 0x00 201 #define SCSICMD_Rewind 0x01 202 #define SCSICMD_Rezero 0x01 203 #define SCSICMD_RequestSense 0x03 204 #define SCSICMD_Format 0x04 205 #define SCSICMD_FormatUnit 0x04 206 #define SCSICMD_Read6 0x08 207 #define SCSICMD_Write6 0x0A 208 #define SCSICMD_Seek6 0x0B 209 #define SCSICMD_Inquiry 0x12 210 #define SCSICMD_Verify6 0x13 211 #define SCSICMD_ModeSelect6 0x15 212 #define SCSICMD_ModeSense6 0x1A 213 #define SCSICMD_StartStopUnit 0x1B 214 #define SCSICMD_LoadUnloadTape 0x1B 215 #define SCSICMD_ReadCapacity 0x25 216 #define SCSICMD_Read10 0x28 217 #define SCSICMD_Write10 0x2A 218 #define SCSICMD_Seek10 0x2B 219 #define SCSICMD_Erase10 0x2C 220 #define SCSICMD_WriteAndVerify10 0x2E 221 #define SCSICMD_Verify10 0x2F 222 #define SCSICMD_WriteBuffer 0x3B 223 #define SCSICMD_ReadBuffer 0x3C 224 #define SCSICMD_ReadLong 0x3E 225 #define SCSICMD_WriteLong 0x3F 226 #define SCSICMD_ReadTOC 0x43 227 #define SCSICMD_ReadHeader 0x44 228 #define SCSICMD_ModeSelect10 0x55 229 #define SCSICMD_ModeSense10 0x5A 230 231 232 #define SCSI_TYPE_DASD 0x00 233 #define SCSI_TYPE_SASD 0x01 234 #define SCSI_TYPE_PRN 0x02 235 #define SCSI_TYPE_PROC 0x03 236 #define SCSI_TYPE_WORM 0x04 237 #define SCSI_TYPE_CDROM 0x05 238 #define SCSI_TYPE_SCANNER 0x06 239 #define SCSI_TYPE_OPTMEM 0x07 240 #define SCSI_TYPE_MED_CHG 0x08 241 #define SCSI_TYPE_COMM 0x09 242 #define SCSI_TYPE_UNKNOWN 0x1F 243 #define SCSI_TYPE_NO_DVC 0xFF 244 245 246 #define ASC_SCSIDIR_NOCHK 0x00 247 #define ASC_SCSIDIR_T2H 0x08 248 #define ASC_SCSIDIR_H2T 0x10 249 #define ASC_SCSIDIR_NODATA 0x18 250 251 252 #define SCSI_SENKEY_NO_SENSE 0x00 253 #define SCSI_SENKEY_UNDEFINED 0x01 254 #define SCSI_SENKEY_NOT_READY 0x02 255 #define SCSI_SENKEY_MEDIUM_ERR 0x03 256 #define SCSI_SENKEY_HW_ERR 0x04 257 #define SCSI_SENKEY_ILLEGAL 0x05 258 #define SCSI_SENKEY_ATTENTION 0x06 259 #define SCSI_SENKEY_PROTECTED 0x07 260 #define SCSI_SENKEY_BLANK 0x08 261 #define SCSI_SENKEY_V_UNIQUE 0x09 262 #define SCSI_SENKEY_CPY_ABORT 0x0A 263 #define SCSI_SENKEY_ABORT 0x0B 264 #define SCSI_SENKEY_EQUAL 0x0C 265 #define SCSI_SENKEY_VOL_OVERFLOW 0x0D 266 #define SCSI_SENKEY_MISCOMP 0x0E 267 #define SCSI_SENKEY_RESERVED 0x0F 268 #define SCSI_ASC_NOMEDIA 0x3A 269 270 271 #define ASC_CCB_HOST(x) ((u_int8_t)((u_int8_t)(x) >> 4)) 272 #define ASC_CCB_TID(x) ((u_int8_t)((u_int8_t)(x) & (u_int8_t)0x0F)) 273 #define ASC_CCB_LUN(x) ((u_int8_t)((uint)(x) >> 13)) 274 275 276 #define SS_GOOD 0x00 277 #define SS_CHK_CONDITION 0x02 278 #define SS_CONDITION_MET 0x04 279 #define SS_TARGET_BUSY 0x08 280 #define SS_INTERMID 0x10 281 #define SS_INTERMID_COND_MET 0x14 282 #define SS_RSERV_CONFLICT 0x18 283 #define SS_CMD_TERMINATED 0x22 284 #define SS_QUEUE_FULL 0x28 285 286 287 #define MS_CMD_DONE 0x00 288 #define MS_EXTEND 0x01 289 #define MS_SDTR_LEN 0x03 290 #define MS_SDTR_CODE 0x01 291 #define MS_WDTR_LEN 0x02 292 #define MS_WDTR_CODE 0x03 293 #define MS_MDP_LEN 0x05 294 #define MS_MDP_CODE 0x00 295 296 297 #define M1_SAVE_DATA_PTR 0x02 298 #define M1_RESTORE_PTRS 0x03 299 #define M1_DISCONNECT 0x04 300 #define M1_INIT_DETECTED_ERR 0x05 301 #define M1_ABORT 0x06 302 #define M1_MSG_REJECT 0x07 303 #define M1_NO_OP 0x08 304 #define M1_MSG_PARITY_ERR 0x09 305 #define M1_LINK_CMD_DONE 0x0A 306 #define M1_LINK_CMD_DONE_WFLAG 0x0B 307 #define M1_BUS_DVC_RESET 0x0C 308 #define M1_ABORT_TAG 0x0D 309 #define M1_CLR_QUEUE 0x0E 310 #define M1_INIT_RECOVERY 0x0F 311 #define M1_RELEASE_RECOVERY 0x10 312 #define M1_KILL_IO_PROC 0x11 313 #define M2_QTAG_MSG_SIMPLE 0x20 314 #define M2_QTAG_MSG_HEAD 0x21 315 #define M2_QTAG_MSG_ORDERED 0x22 316 #define M2_IGNORE_WIDE_RESIDUE 0x23 317 318 319 /* 320 * SCSI Inquiry structure 321 */ 322 323 typedef struct 324 { 325 u_int8_t peri_dvc_type:5; 326 u_int8_t peri_qualifier:3; 327 } ASC_SCSI_INQ0; 328 329 typedef struct 330 { 331 u_int8_t dvc_type_modifier:7; 332 u_int8_t rmb:1; 333 } ASC_SCSI_INQ1; 334 335 typedef struct 336 { 337 u_int8_t ansi_apr_ver:3; 338 u_int8_t ecma_ver:3; 339 u_int8_t iso_ver:2; 340 } ASC_SCSI_INQ2; 341 342 typedef struct 343 { 344 u_int8_t rsp_data_fmt:4; 345 u_int8_t res:2; 346 u_int8_t TemIOP:1; 347 u_int8_t aenc:1; 348 } ASC_SCSI_INQ3; 349 350 typedef struct 351 { 352 u_int8_t StfRe:1; 353 u_int8_t CmdQue:1; 354 u_int8_t Reserved:1; 355 u_int8_t Linked:1; 356 u_int8_t Sync:1; 357 u_int8_t WBus16:1; 358 u_int8_t WBus32:1; 359 u_int8_t RelAdr:1; 360 } ASC_SCSI_INQ7; 361 362 typedef struct 363 { 364 ASC_SCSI_INQ0 byte0; 365 ASC_SCSI_INQ1 byte1; 366 ASC_SCSI_INQ2 byte2; 367 ASC_SCSI_INQ3 byte3; 368 u_int8_t add_len; 369 u_int8_t res1; 370 u_int8_t res2; 371 ASC_SCSI_INQ7 byte7; 372 u_int8_t vendor_id[8]; 373 u_int8_t product_id[16]; 374 u_int8_t product_rev_level[4]; 375 } ASC_SCSI_INQUIRY; 376 377 378 /* 379 * SCSIQ Microcode offsets 380 */ 381 #define ASC_SCSIQ_CPY_BEG 4 382 #define ASC_SCSIQ_SGHD_CPY_BEG 2 383 #define ASC_SCSIQ_B_FWD 0 384 #define ASC_SCSIQ_B_BWD 1 385 #define ASC_SCSIQ_B_STATUS 2 386 #define ASC_SCSIQ_B_QNO 3 387 #define ASC_SCSIQ_B_CNTL 4 388 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5 389 #define ASC_SCSIQ_D_DATA_ADDR 8 390 #define ASC_SCSIQ_D_DATA_CNT 12 391 #define ASC_SCSIQ_B_SENSE_LEN 20 392 #define ASC_SCSIQ_DONE_INFO_BEG 22 393 #define ASC_SCSIQ_D_CCBPTR 22 394 #define ASC_SCSIQ_B_TARGET_IX 26 395 #define ASC_SCSIQ_B_CDB_LEN 28 396 #define ASC_SCSIQ_B_TAG_CODE 29 397 #define ASC_SCSIQ_W_VM_ID 30 398 #define ASC_SCSIQ_DONE_STATUS 32 399 #define ASC_SCSIQ_HOST_STATUS 33 400 #define ASC_SCSIQ_SCSI_STATUS 34 401 #define ASC_SCSIQ_CDB_BEG 36 402 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 403 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 404 #define ASC_SCSIQ_B_SG_WK_QP 49 405 #define ASC_SCSIQ_B_SG_WK_IX 50 406 #define ASC_SCSIQ_W_REQ_COUNT 52 407 #define ASC_SCSIQ_B_LIST_CNT 6 408 #define ASC_SCSIQ_B_CUR_LIST_CNT 7 409 410 411 #define ASC_DEF_SCSI1_QNG 4 412 #define ASC_MAX_SCSI1_QNG 4 413 #define ASC_DEF_SCSI2_QNG 16 414 #define ASC_MAX_SCSI2_QNG 32 415 416 #define ASC_TAG_CODE_MASK 0x23 417 418 #define ASC_STOP_REQ_RISC_STOP 0x01 419 #define ASC_STOP_ACK_RISC_STOP 0x03 420 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 421 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20 422 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40 423 424 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) 425 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) 426 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) 427 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) 428 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) 429 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) 430 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) 431 432 433 /* 434 * Structures used to dialog with the RISC engine 435 */ 436 437 typedef struct asc_scisq_1 438 { 439 u_int8_t status; /* see below status values */ 440 u_int8_t q_no; /* Queue ID of the first queue for this transaction */ 441 u_int8_t cntl; /* see below cntl values */ 442 u_int8_t sg_queue_cnt; /* number of SG entries */ 443 u_int8_t target_id; 444 u_int8_t target_lun; 445 u_int32_t data_addr; /* physical address of first segment to transfer */ 446 u_int32_t data_cnt; /* byte count of first segment to transfer */ 447 u_int32_t sense_addr; /* physical address of the sense buffer */ 448 u_int8_t sense_len; /* length of sense buffer */ 449 u_int8_t extra_bytes; 450 } ASC_SCSIQ_1; 451 452 /* status values */ 453 #define ASC_QS_FREE 0x00 454 #define ASC_QS_READY 0x01 455 #define ASC_QS_DISC1 0x02 456 #define ASC_QS_DISC2 0x04 457 #define ASC_QS_BUSY 0x08 458 #define ASC_QS_ABORTED 0x40 459 #define ASC_QS_DONE 0x80 460 461 /* cntl values */ 462 #define ASC_QC_NO_CALLBACK 0x01 463 #define ASC_QC_SG_SWAP_QUEUE 0x02 464 #define ASC_QC_SG_HEAD 0x04 465 #define ASC_QC_DATA_IN 0x08 466 #define ASC_QC_DATA_OUT 0x10 467 #define ASC_QC_URGENT 0x20 468 #define ASC_QC_MSG_OUT 0x40 469 #define ASC_QC_REQ_SENSE 0x80 470 471 472 typedef struct asc_scisq_2 473 { 474 u_int32_t ccb_ptr; /* physical pointer to our CCB */ 475 u_int8_t target_ix; /* combined TID and LUN */ 476 u_int8_t flag; 477 u_int8_t cdb_len; /* bytes of Command Descriptor Block */ 478 u_int8_t tag_code; /* type of this transaction. see below */ 479 u_int16_t vm_id; 480 } ASC_SCSIQ_2; 481 482 /* tag_code values */ 483 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10 484 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 485 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 486 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 487 488 489 typedef struct asc_scsiq_3 490 { 491 u_int8_t done_stat; /* see below done_stat values */ 492 u_int8_t host_stat; /* see below host_stat values */ 493 u_int8_t scsi_stat; 494 u_int8_t scsi_msg; 495 } ASC_SCSIQ_3; 496 497 /* done_stat values */ 498 #define ASC_QD_IN_PROGRESS 0x00 499 #define ASC_QD_NO_ERROR 0x01 500 #define ASC_QD_ABORTED_BY_HOST 0x02 501 #define ASC_QD_WITH_ERROR 0x04 502 #define ASC_QD_INVALID_REQUEST 0x80 503 #define ASC_QD_INVALID_HOST_NUM 0x81 504 #define ASC_QD_INVALID_DEVICE 0x82 505 #define ASC_QD_ERR_INTERNAL 0xFF 506 507 /* host_stat values */ 508 #define ASC_QHSTA_NO_ERROR 0x00 509 #define ASC_QHSTA_M_SEL_TIMEOUT 0x11 510 #define ASC_QHSTA_M_DATA_OVER_RUN 0x12 511 #define ASC_QHSTA_M_DATA_UNDER_RUN 0x12 512 #define ASC_QHSTA_M_UNEXPECTED_BUS_FREE 0x13 513 #define ASC_QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 514 #define ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 515 #define ASC_QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 516 #define ASC_QHSTA_D_HOST_ABORT_FAILED 0x23 517 #define ASC_QHSTA_D_EXE_SCSI_Q_FAILED 0x24 518 #define ASC_QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 519 #define ASC_QHSTA_D_ASPI_NO_BUF_POOL 0x26 520 #define ASC_QHSTA_M_WTM_TIMEOUT 0x41 521 #define ASC_QHSTA_M_BAD_CMPL_STATUS_IN 0x42 522 #define ASC_QHSTA_M_NO_AUTO_REQ_SENSE 0x43 523 #define ASC_QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 524 #define ASC_QHSTA_M_TARGET_STATUS_BUSY 0x45 525 #define ASC_QHSTA_M_BAD_TAG_CODE 0x46 526 #define ASC_QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 527 #define ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 528 #define ASC_QHSTA_D_LRAM_CMP_ERROR 0x81 529 #define ASC_QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 530 531 532 typedef struct asc_scsiq_4 533 { 534 u_int8_t cdb[ASC_MAX_CDB_LEN]; 535 u_int8_t y_first_sg_list_qp; 536 u_int8_t y_working_sg_qp; 537 u_int8_t y_working_sg_ix; 538 u_int8_t y_res; 539 u_int16_t x_req_count; 540 u_int16_t x_reconnect_rtn; 541 u_int32_t x_saved_data_addr; 542 u_int32_t x_saved_data_cnt; 543 } ASC_SCSIQ_4; 544 545 typedef struct asc_q_done_info 546 { 547 ASC_SCSIQ_2 d2; 548 ASC_SCSIQ_3 d3; 549 u_int8_t q_status; 550 u_int8_t q_no; 551 u_int8_t cntl; 552 u_int8_t sense_len; 553 u_int8_t extra_bytes; 554 u_int8_t res; 555 u_int32_t remain_bytes; 556 } ASC_QDONE_INFO; 557 558 typedef struct asc_sg_list 559 { 560 u_int32_t addr; 561 u_int32_t bytes; 562 } ASC_SG_LIST; 563 564 typedef struct asc_sg_head 565 { 566 u_int16_t entry_cnt; /* number of SG entries */ 567 u_int16_t queue_cnt; /* number of queues required to store SG entries */ 568 u_int16_t entry_to_copy; /* number of SG entries to copy to the board */ 569 u_int16_t res; 570 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST]; 571 } ASC_SG_HEAD; 572 573 #define ASC_MIN_SG_LIST 2 574 575 typedef struct asc_min_sg_head 576 { 577 u_int16_t entry_cnt; 578 u_int16_t queue_cnt; 579 u_int16_t entry_to_copy; 580 u_int16_t res; 581 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST]; 582 } ASC_MIN_SG_HEAD; 583 584 #define ASC_QCX_SORT 0x0001 585 #define ASC_QCX_COALEASE 0x0002 586 587 typedef struct asc_scsi_q 588 { 589 ASC_SCSIQ_1 q1; 590 ASC_SCSIQ_2 q2; 591 u_int8_t *cdbptr; /* pointer to CDB to execute */ 592 ASC_SG_HEAD *sg_head; /* pointer to SG list */ 593 } ASC_SCSI_Q; 594 595 typedef struct asc_scsi_req_q 596 { 597 ASC_SCSIQ_1 q1; 598 ASC_SCSIQ_2 q2; 599 u_int8_t *cdbptr; 600 ASC_SG_HEAD *sg_head; 601 u_int8_t *sense_ptr; 602 ASC_SCSIQ_3 q3; 603 u_int8_t cdb[ASC_MAX_CDB_LEN]; 604 u_int8_t sense[ASC_MIN_SENSE_LEN]; 605 } ASC_SCSI_REQ_Q; 606 607 typedef struct asc_scsi_bios_req_q 608 { 609 ASC_SCSIQ_1 q1; 610 ASC_SCSIQ_2 q2; 611 u_int8_t *cdbptr; 612 ASC_SG_HEAD *sg_head; 613 u_int8_t *sense_ptr; 614 ASC_SCSIQ_3 q3; 615 u_int8_t cdb[ASC_MAX_CDB_LEN]; 616 u_int8_t sense[ASC_MIN_SENSE_LEN]; 617 } ASC_SCSI_BIOS_REQ_Q; 618 619 typedef struct asc_risc_q 620 { 621 u_int8_t fwd; 622 u_int8_t bwd; 623 ASC_SCSIQ_1 i1; 624 ASC_SCSIQ_2 i2; 625 ASC_SCSIQ_3 i3; 626 ASC_SCSIQ_4 i4; 627 } ASC_RISC_Q; 628 629 typedef struct asc_sg_list_q 630 { 631 u_int8_t seq_no; 632 u_int8_t q_no; 633 u_int8_t cntl; /* see below cntl values */ 634 u_int8_t sg_head_qp; 635 u_int8_t sg_list_cnt; 636 u_int8_t sg_cur_list_cnt; 637 } ASC_SG_LIST_Q; 638 639 /* cntl values */ 640 #define ASC_QCSG_SG_XFER_LIST 0x02 641 #define ASC_QCSG_SG_XFER_MORE 0x04 642 #define ASC_QCSG_SG_XFER_END 0x08 643 644 #define ASC_SGQ_B_SG_CNTL 4 645 #define ASC_SGQ_B_SG_HEAD_QP 5 646 #define ASC_SGQ_B_SG_LIST_CNT 6 647 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7 648 #define ASC_SGQ_LIST_BEG 8 649 650 651 typedef struct asc_risc_sg_list_q 652 { 653 u_int8_t fwd; 654 u_int8_t bwd; 655 ASC_SG_LIST_Q sg; 656 ASC_SG_LIST sg_list[7]; 657 } ASC_RISC_SG_LIST_Q; 658 659 660 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL 661 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024 662 663 #define ASCQ_ERR_NO_ERROR 0x00 664 #define ASCQ_ERR_IO_NOT_FOUND 0x01 665 #define ASCQ_ERR_LOCAL_MEM 0x02 666 #define ASCQ_ERR_CHKSUM 0x03 667 #define ASCQ_ERR_START_CHIP 0x04 668 #define ASCQ_ERR_INT_TARGET_ID 0x05 669 #define ASCQ_ERR_INT_LOCAL_MEM 0x06 670 #define ASCQ_ERR_HALT_RISC 0x07 671 #define ASCQ_ERR_GET_ASPI_ENTRY 0x08 672 #define ASCQ_ERR_CLOSE_ASPI 0x09 673 #define ASCQ_ERR_HOST_INQUIRY 0x0A 674 #define ASCQ_ERR_SAVED_CCB_BAD 0x0B 675 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C 676 #define ASCQ_ERR_Q_STATUS 0x0D 677 #define ASCQ_ERR_WR_SCSIQ 0x0E 678 #define ASCQ_ERR_PC_ADDR 0x0F 679 #define ASCQ_ERR_SYN_OFFSET 0x10 680 #define ASCQ_ERR_SYN_XFER_TIME 0x11 681 #define ASCQ_ERR_LOCK_DMA 0x12 682 #define ASCQ_ERR_UNLOCK_DMA 0x13 683 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14 684 #define ASCQ_ERR_MICRO_CODE_HALT 0x15 685 #define ASCQ_ERR_SET_LRAM_ADDR 0x16 686 #define ASCQ_ERR_CUR_QNG 0x17 687 #define ASCQ_ERR_SG_Q_LINKS 0x18 688 #define ASCQ_ERR_SCSIQ_PTR 0x19 689 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A 690 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B 691 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C 692 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D 693 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E 694 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F 695 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20 696 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21 697 #define ASCQ_ERR_SEND_SCSI_Q 0x22 698 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23 699 #define ASCQ_ERR_RESET_SDTR 0x24 700 701 #define ASC_WARN_NO_ERROR 0x0000 702 #define ASC_WARN_IO_PORT_ROTATE 0x0001 703 #define ASC_WARN_EEPROM_CHKSUM 0x0002 704 #define ASC_WARN_IRQ_MODIFIED 0x0004 705 #define ASC_WARN_AUTO_CONFIG 0x0008 706 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010 707 #define ASC_WARN_EEPROM_RECOVER 0x0020 708 #define ASC_WARN_CFG_MSW_RECOVER 0x0040 709 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 710 711 #define ASC_IERR_WRITE_EEPROM 0x0001 712 #define ASC_IERR_MCODE_CHKSUM 0x0002 713 #define ASC_IERR_SET_PC_ADDR 0x0004 714 #define ASC_IERR_START_STOP_CHIP 0x0008 715 #define ASC_IERR_IRQ_NO 0x0010 716 #define ASC_IERR_SET_IRQ_NO 0x0020 717 #define ASC_IERR_CHIP_VERSION 0x0040 718 #define ASC_IERR_SET_SCSI_ID 0x0080 719 #define ASC_IERR_GET_PHY_ADDR 0x0100 720 #define ASC_IERR_BAD_SIGNATURE 0x0200 721 #define ASC_IERR_NO_BUS_TYPE 0x0400 722 #define ASC_IERR_SCAM 0x0800 723 #define ASC_IERR_SET_SDTR 0x1000 724 #define ASC_IERR_RW_LRAM 0x8000 725 726 #define ASC_DEF_IRQ_NO 10 727 #define ASC_MAX_IRQ_NO 15 728 #define ASC_MIN_IRQ_NO 10 729 #define ASC_MIN_REMAIN_Q 0x02 730 #define ASC_DEF_MAX_TOTAL_QNG 0xF0 731 #define ASC_MIN_TAG_Q_PER_DVC 0x04 732 #define ASC_DEF_TAG_Q_PER_DVC 0x04 733 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q 734 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) 735 #define ASC_MAX_TOTAL_QNG 240 736 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 737 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 738 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 739 #define ASC_MAX_INRAM_TAG_QNG 16 740 #define ASC_IOADR_TABLE_MAX_IX 11 741 #define ASC_IOADR_GAP 0x10 742 #define ASC_SEARCH_IOP_GAP 0x10 743 #define ASC_MIN_IOP_ADDR 0x0100 744 #define ASC_MAX_IOP_ADDR 0x03F0 745 746 #define ASC_IOADR_1 0x0110 747 #define ASC_IOADR_2 0x0130 748 #define ASC_IOADR_3 0x0150 749 #define ASC_IOADR_4 0x0190 750 #define ASC_IOADR_5 0x0210 751 #define ASC_IOADR_6 0x0230 752 #define ASC_IOADR_7 0x0250 753 #define ASC_IOADR_8 0x0330 754 755 #define ASC_IOADR_DEF ASC_IOADR_8 756 #define ASC_LIB_SCSIQ_WK_SP 256 757 #define ASC_MAX_SYN_XFER_NO 16 758 #define ASC_SYN_MAX_OFFSET 0x0F 759 #define ASC_DEF_SDTR_OFFSET 0x0F 760 #define ASC_DEF_SDTR_INDEX 0x00 761 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 762 763 764 /* 765 * This structure is used to handle internal messages 766 * during interrupt handling routine 767 */ 768 typedef struct ext_msg 769 { 770 u_int8_t msg_type; 771 u_int8_t msg_len; 772 u_int8_t msg_req; 773 774 union 775 { 776 struct 777 { 778 u_int8_t sdtr_xfer_period; 779 u_int8_t sdtr_req_ack_offset; 780 } sdtr; 781 782 struct 783 { 784 u_int8_t wdtr_width; 785 } wdtr; 786 787 struct 788 { 789 u_int8_t mdp_b3; 790 u_int8_t mdp_b2; 791 u_int8_t mdp_b1; 792 u_int8_t mdp_b0; 793 } mdp; 794 } u_ext_msg; 795 796 u_int8_t res; 797 } EXT_MSG; 798 799 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period 800 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset 801 #define wdtr_width u_ext_msg.wdtr.wdtr_width 802 #define mdp_b3 u_ext_msg.mdp_b3 803 #define mdp_b2 u_ext_msg.mdp_b2 804 #define mdp_b1 u_ext_msg.mdp_b1 805 #define mdp_b0 u_ext_msg.mdp_b0 806 807 808 #define ASC_DEF_DVC_CNTL 0xFFFF 809 #define ASC_DEF_CHIP_SCSI_ID 7 810 #define ASC_DEF_ISA_DMA_SPEED 4 811 812 #define ASC_PCI_DEVICE_ID_REV_A 0x1100 813 #define ASC_PCI_DEVICE_ID_REV_B 0x1200 814 815 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001 816 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 817 818 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 819 820 #define ASC_MIN_TAGGED_CMD 7 821 822 #define ASC_MAX_SCSI_RESET_WAIT 30 823 824 825 #define CCB_HASH_SIZE 32 /* hash table size for phystokv */ 826 #define CCB_HASH_SHIFT 9 827 #define CCB_HASH(x) ((((long)(x))>>CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1)) 828 829 typedef struct asc_softc 830 { 831 device_t sc_dev; 832 833 device_t sc_child; 834 835 bus_space_tag_t sc_iot; 836 bus_space_handle_t sc_ioh; 837 bus_dma_tag_t sc_dmat; 838 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 839 void *sc_ih; 840 841 struct adv_control *sc_control; /* control structures */ 842 843 bus_dma_segment_t sc_control_seg; 844 int sc_control_nsegs; 845 846 struct adv_ccb *sc_ccbhash[CCB_HASH_SIZE]; 847 TAILQ_HEAD(, adv_ccb) sc_free_ccb, sc_waiting_ccb; 848 849 struct scsipi_adapter sc_adapter; 850 struct scsipi_channel sc_channel; 851 852 bus_addr_t overrun_buf; 853 854 u_int16_t sc_flags; /* see below sc_flags values */ 855 856 u_int16_t dvc_cntl; 857 u_int16_t bug_fix_cntl; 858 u_int16_t bus_type; 859 860 void (*isr_callback)(struct asc_softc *, ASC_QDONE_INFO *); 861 862 ASC_SCSI_BIT_ID_TYPE init_sdtr; 863 ASC_SCSI_BIT_ID_TYPE sdtr_done; 864 ASC_SCSI_BIT_ID_TYPE use_tagged_qng; 865 ASC_SCSI_BIT_ID_TYPE unit_not_ready; 866 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; 867 ASC_SCSI_BIT_ID_TYPE start_motor; 868 869 ASC_SCSI_BIT_ID_TYPE can_tagged_qng; 870 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; 871 ASC_SCSI_BIT_ID_TYPE disc_enable; 872 ASC_SCSI_BIT_ID_TYPE sdtr_enable; 873 u_int8_t irq_no; 874 u_int8_t chip_scsi_id; 875 u_int8_t isa_dma_speed; 876 u_int8_t isa_dma_channel; 877 u_int8_t chip_version; 878 u_int16_t pci_device_id; 879 u_int16_t lib_serial_no; 880 u_int16_t lib_version; 881 u_int16_t mcode_date; 882 u_int16_t mcode_version; 883 u_int8_t max_tag_qng[ASC_MAX_TID + 1]; 884 u_int8_t sdtr_period_offset[ASC_MAX_TID + 1]; 885 u_int8_t adapter_info[6]; 886 887 u_int8_t scsi_reset_wait; 888 u_int8_t max_total_qng; 889 u_int8_t cur_total_qng; 890 u_int8_t last_q_shortage; 891 892 u_int8_t cur_dvc_qng[ASC_MAX_TID + 1]; 893 u_int8_t max_dvc_qng[ASC_MAX_TID + 1]; 894 u_int8_t sdtr_period_tbl[ASC_MAX_SYN_XFER_NO]; 895 u_int8_t sdtr_period_tbl_size; /* see below */ 896 u_int8_t sdtr_data[ASC_MAX_TID+1]; 897 898 u_int16_t reqcnt[ASC_MAX_TID+1]; /* Starvation request count */ 899 900 u_int32_t max_dma_count; 901 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 902 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 903 u_int8_t max_sdtr_index; 904 u_int8_t host_init_sdtr_index; 905 } ASC_SOFTC; 906 907 /* sc_flags values */ 908 #define ASC_HOST_IN_RESET 0x01 909 #define ASC_HOST_IN_ABORT 0x02 910 #define ASC_WIDE_BOARD 0x04 911 #define ASC_SELECT_QUEUE_DEPTHS 0x08 912 913 /* sdtr_period_tbl_size values */ 914 #define SYN_XFER_NS_0 25 915 #define SYN_XFER_NS_1 30 916 #define SYN_XFER_NS_2 35 917 #define SYN_XFER_NS_3 40 918 #define SYN_XFER_NS_4 50 919 #define SYN_XFER_NS_5 60 920 #define SYN_XFER_NS_6 70 921 #define SYN_XFER_NS_7 85 922 923 #define SYN_ULTRA_XFER_NS_0 12 924 #define SYN_ULTRA_XFER_NS_1 19 925 #define SYN_ULTRA_XFER_NS_2 25 926 #define SYN_ULTRA_XFER_NS_3 32 927 #define SYN_ULTRA_XFER_NS_4 38 928 #define SYN_ULTRA_XFER_NS_5 44 929 #define SYN_ULTRA_XFER_NS_6 50 930 #define SYN_ULTRA_XFER_NS_7 57 931 #define SYN_ULTRA_XFER_NS_8 63 932 #define SYN_ULTRA_XFER_NS_9 69 933 #define SYN_ULTRA_XFER_NS_10 75 934 #define SYN_ULTRA_XFER_NS_11 82 935 #define SYN_ULTRA_XFER_NS_12 88 936 #define SYN_ULTRA_XFER_NS_13 94 937 #define SYN_ULTRA_XFER_NS_14 100 938 #define SYN_ULTRA_XFER_NS_15 107 939 940 941 #define ASC_MCNTL_NO_SEL_TIMEOUT 0x0001 942 #define ASC_MCNTL_NULL_TARGET 0x0002 943 944 #define ASC_CNTL_INITIATOR 0x0001 945 #define ASC_CNTL_BIOS_GT_1GB 0x0002 946 #define ASC_CNTL_BIOS_GT_2_DISK 0x0004 947 #define ASC_CNTL_BIOS_REMOVABLE 0x0008 948 #define ASC_CNTL_NO_SCAM 0x0010 949 #define ASC_CNTL_INT_MULTI_Q 0x0080 950 #define ASC_CNTL_NO_LUN_SUPPORT 0x0040 951 #define ASC_CNTL_NO_VERIFY_COPY 0x0100 952 #define ASC_CNTL_RESET_SCSI 0x0200 953 #define ASC_CNTL_INIT_INQUIRY 0x0400 954 #define ASC_CNTL_INIT_VERBOSE 0x0800 955 #define ASC_CNTL_SCSI_PARITY 0x1000 956 #define ASC_CNTL_BURST_MODE 0x2000 957 #define ASC_CNTL_SDTR_ENABLE_ULTRA 0x4000 958 959 #define ASC_EEP_DVC_CFG_BEG_VL 2 960 #define ASC_EEP_MAX_DVC_ADDR_VL 15 961 #define ASC_EEP_DVC_CFG_BEG 32 962 #define ASC_EEP_MAX_DVC_ADDR 45 963 #define ASC_EEP_DEFINED_WORDS 10 964 #define ASC_EEP_MAX_ADDR 63 965 #define ASC_EEP_RES_WORDS 0 966 #define ASC_EEP_MAX_RETRY 20 967 #define ASC_MAX_INIT_BUSY_RETRY 8 968 #define ASC_EEP_ISA_PNP_WSIZE 16 969 970 971 /* 972 * This structure is used to read/write EEProm configuration 973 */ 974 typedef struct asceep_config 975 { 976 u_int16_t cfg_lsw; 977 u_int16_t cfg_msw; 978 #if BYTE_ORDER == BIG_ENDIAN 979 u_int8_t disc_enable; 980 u_int8_t init_sdtr; 981 u_int8_t start_motor; 982 u_int8_t use_cmd_qng; 983 u_int8_t max_tag_qng; 984 u_int8_t max_total_qng; 985 u_int8_t power_up_wait; 986 u_int8_t bios_scan; 987 u_int8_t isa_dma_speed:4; 988 u_int8_t chip_scsi_id:4; 989 u_int8_t no_scam; 990 #else 991 u_int8_t init_sdtr; 992 u_int8_t disc_enable; 993 u_int8_t use_cmd_qng; 994 u_int8_t start_motor; 995 u_int8_t max_total_qng; 996 u_int8_t max_tag_qng; 997 u_int8_t bios_scan; 998 u_int8_t power_up_wait; 999 u_int8_t no_scam; 1000 u_int8_t chip_scsi_id:4; 1001 u_int8_t isa_dma_speed:4; 1002 #endif 1003 u_int8_t dos_int13_table[ASC_MAX_TID + 1]; 1004 u_int8_t adapter_info[6]; 1005 u_int16_t cntl; 1006 u_int16_t chksum; 1007 } ASCEEP_CONFIG; 1008 1009 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800 1010 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080 1011 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020 1012 1013 #define ASC_EEP_CMD_READ 0x80 1014 #define ASC_EEP_CMD_WRITE 0x40 1015 #define ASC_EEP_CMD_WRITE_ABLE 0x30 1016 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 1017 1018 #define ASC_OVERRUN_BSIZE 0x00000048UL 1019 1020 #define ASC_CTRL_BREAK_ONCE 0x0001 1021 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002 1022 1023 #define ASCV_MSGOUT_BEG 0x0000 1024 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) 1025 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) 1026 #define ASCV_BREAK_SAVED_CODE 0x0006 1027 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) 1028 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) 1029 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) 1030 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) 1031 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) 1032 #define ASCV_MAX_DVC_QNG_BEG 0x0020 1033 #define ASCV_BREAK_ADDR 0x0028 1034 #define ASCV_BREAK_NOTIFY_COUNT 0x002A 1035 #define ASCV_BREAK_CONTROL 0x002C 1036 #define ASCV_BREAK_HIT_COUNT 0x002E 1037 1038 #define ASCV_ASCDVC_ERR_CODE_W 0x0030 1039 #define ASCV_MCODE_CHKSUM_W 0x0032 1040 #define ASCV_MCODE_SIZE_W 0x0034 1041 #define ASCV_STOP_CODE_B 0x0036 1042 #define ASCV_DVC_ERR_CODE_B 0x0037 1043 #define ASCV_OVERRUN_PADDR_D 0x0038 1044 #define ASCV_OVERRUN_BSIZE_D 0x003C 1045 #define ASCV_HALTCODE_W 0x0040 1046 #define ASCV_CHKSUM_W 0x0042 1047 #define ASCV_MC_DATE_W 0x0044 1048 #define ASCV_MC_VER_W 0x0046 1049 #define ASCV_NEXTRDY_B 0x0048 1050 #define ASCV_DONENEXT_B 0x0049 1051 #define ASCV_USE_TAGGED_QNG_B 0x004A 1052 #define ASCV_SCSIBUSY_B 0x004B 1053 #define ASCV_Q_DONE_IN_PROGRESS_B 0x004C 1054 #define ASCV_CURCDB_B 0x004D 1055 #define ASCV_RCLUN_B 0x004E 1056 #define ASCV_BUSY_QHEAD_B 0x004F 1057 #define ASCV_DISC1_QHEAD_B 0x0050 1058 #define ASCV_DISC_ENABLE_B 0x0052 1059 #define ASCV_CAN_TAGGED_QNG_B 0x0053 1060 #define ASCV_HOSTSCSI_ID_B 0x0055 1061 #define ASCV_MCODE_CNTL_B 0x0056 1062 #define ASCV_NULL_TARGET_B 0x0057 1063 #define ASCV_FREE_Q_HEAD_W 0x0058 1064 #define ASCV_DONE_Q_TAIL_W 0x005A 1065 #define ASCV_FREE_Q_HEAD_B (ASCV_FREE_Q_HEAD_W+1) 1066 #define ASCV_DONE_Q_TAIL_B (ASCV_DONE_Q_TAIL_W+1) 1067 #define ASCV_HOST_FLAG_B 0x005D 1068 #define ASCV_TOTAL_READY_Q_B 0x0064 1069 #define ASCV_VER_SERIAL_B 0x0065 1070 #define ASCV_HALTCODE_SAVED_W 0x0066 1071 #define ASCV_WTM_FLAG_B 0x0068 1072 #define ASCV_RISC_FLAG_B 0x006A 1073 #define ASCV_REQ_SG_LIST_QP 0x006B 1074 1075 #define ASC_HOST_FLAG_IN_ISR 0x01 1076 #define ASC_HOST_FLAG_ACK_INT 0x02 1077 #define ASC_RISC_FLAG_GEN_INT 0x01 1078 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02 1079 1080 #define ASC_IOP_CTRL 0x0F 1081 #define ASC_IOP_STATUS 0x0E 1082 #define ASC_IOP_INT_ACK ASC_IOP_STATUS 1083 #define ASC_IOP_REG_IFC 0x0D 1084 #define ASC_IOP_SYN_OFFSET 0x0B 1085 #define ASC_IOP_EXTRA_CONTROL 0x0D 1086 #define ASC_IOP_REG_PC 0x0C 1087 #define ASC_IOP_RAM_ADDR 0x0A 1088 #define ASC_IOP_RAM_DATA 0x08 1089 #define ASC_IOP_EEP_DATA 0x06 1090 #define ASC_IOP_EEP_CMD 0x07 1091 #define ASC_IOP_VERSION 0x03 1092 #define ASC_IOP_CONFIG_HIGH 0x04 1093 #define ASC_IOP_CONFIG_LOW 0x02 1094 #define ASC_IOP_SIG_BYTE 0x01 1095 #define ASC_IOP_SIG_WORD 0x00 1096 #define ASC_IOP_REG_DC1 0x0E 1097 #define ASC_IOP_REG_DC0 0x0C 1098 #define ASC_IOP_REG_SB 0x0B 1099 #define ASC_IOP_REG_DA1 0x0A 1100 #define ASC_IOP_REG_DA0 0x08 1101 #define ASC_IOP_REG_SC 0x09 1102 #define ASC_IOP_DMA_SPEED 0x07 1103 #define ASC_IOP_REG_FLAG 0x07 1104 #define ASC_IOP_FIFO_H 0x06 1105 #define ASC_IOP_FIFO_L 0x04 1106 #define ASC_IOP_REG_ID 0x05 1107 #define ASC_IOP_REG_QP 0x03 1108 #define ASC_IOP_REG_IH 0x02 1109 #define ASC_IOP_REG_IX 0x01 1110 #define ASC_IOP_REG_AX 0x00 1111 1112 #define ASC_IFC_REG_LOCK 0x00 1113 #define ASC_IFC_REG_UNLOCK 0x09 1114 #define ASC_IFC_WR_EN_FILTER 0x10 1115 #define ASC_IFC_RD_NO_EEPROM 0x10 1116 #define ASC_IFC_SLEW_RATE 0x20 1117 #define ASC_IFC_ACT_NEG 0x40 1118 #define ASC_IFC_INP_FILTER 0x80 1119 #define ASC_IFC_INIT_DEFAULT (ASC_IFC_ACT_NEG | ASC_IFC_REG_UNLOCK) 1120 1121 #define SC_SEL 0x80 1122 #define SC_BSY 0x40 1123 #define SC_ACK 0x20 1124 #define SC_REQ 0x10 1125 #define SC_ATN 0x08 1126 #define SC_IO 0x04 1127 #define SC_CD 0x02 1128 #define SC_MSG 0x01 1129 1130 #define SEC_SCSI_CTL 0x80 1131 #define SEC_ACTIVE_NEGATE 0x40 1132 #define SEC_SLEW_RATE 0x20 1133 #define SEC_ENABLE_FILTER 0x10 1134 1135 #define ASC_HALT_EXTMSG_IN 0x8000 1136 #define ASC_HALT_CHK_CONDITION 0x8100 1137 #define ASC_HALT_SS_QUEUE_FULL 0x8200 1138 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300 1139 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400 1140 #define ASC_HALT_SDTR_REJECTED 0x4000 1141 1142 #define ASC_MAX_QNO 0xF8 1143 1144 #define ASC_DATA_SEC_BEG 0x0080 1145 #define ASC_DATA_SEC_END 0x0080 1146 #define ASC_CODE_SEC_BEG 0x0080 1147 #define ASC_CODE_SEC_END 0x0080 1148 #define ASC_QADR_BEG (0x4000) 1149 #define ASC_QADR_USED (ASC_MAX_QNO * 64) 1150 #define ASC_QADR_END 0x7FFF 1151 #define ASC_QLAST_ADR 0x7FC0 1152 #define ASC_QBLK_SIZE 0x40 1153 #define ASC_BIOS_DATA_QBEG 0xF8 1154 #define ASC_MIN_ACTIVE_QNO 0x01 1155 #define ASC_QLINK_END 0xFF 1156 #define ASC_EEPROM_WORDS 0x10 1157 #define ASC_MAX_MGS_LEN 0x10 1158 1159 #define ASC_BIOS_ADDR_DEF 0xDC00 1160 #define ASC_BIOS_SIZE 0x3800 1161 #define ASC_BIOS_RAM_OFF 0x3800 1162 #define ASC_BIOS_RAM_SIZE 0x800 1163 #define ASC_BIOS_MIN_ADDR 0xC000 1164 #define ASC_BIOS_MAX_ADDR 0xEC00 1165 #define ASC_BIOS_BANK_SIZE 0x0400 1166 1167 #define ASC_MCODE_START_ADDR 0x0080 1168 1169 #define ASC_CFG0_HOST_INT_ON 0x0020 1170 #define ASC_CFG0_BIOS_ON 0x0040 1171 #define ASC_CFG0_VERA_BURST_ON 0x0080 1172 #define ASC_CFG0_SCSI_PARITY_ON 0x0800 1173 #define ASC_CFG1_SCSI_TARGET_ON 0x0080 1174 #define ASC_CFG1_LRAM_8BITS_ON 0x0800 1175 #define ASC_CFG_MSW_CLR_MASK 0x3080 1176 1177 #define ASC_CSW_TEST1 0x8000 1178 #define ASC_CSW_AUTO_CONFIG 0x4000 1179 #define ASC_CSW_RESERVED1 0x2000 1180 #define ASC_CSW_IRQ_WRITTEN 0x1000 1181 #define ASC_CSW_33MHZ_SELECTED 0x0800 1182 #define ASC_CSW_TEST2 0x0400 1183 #define ASC_CSW_TEST3 0x0200 1184 #define ASC_CSW_RESERVED2 0x0100 1185 #define ASC_CSW_DMA_DONE 0x0080 1186 #define ASC_CSW_FIFO_RDY 0x0040 1187 #define ASC_CSW_EEP_READ_DONE 0x0020 1188 #define ASC_CSW_HALTED 0x0010 1189 #define ASC_CSW_SCSI_RESET_ACTIVE 0x0008 1190 #define ASC_CSW_PARITY_ERR 0x0004 1191 #define ASC_CSW_SCSI_RESET_LATCH 0x0002 1192 #define ASC_CSW_INT_PENDING 0x0001 1193 1194 #define ASC_CIW_CLR_SCSI_RESET_INT 0x1000 1195 #define ASC_CIW_INT_ACK 0x0100 1196 #define ASC_CIW_TEST1 0x0200 1197 #define ASC_CIW_TEST2 0x0400 1198 #define ASC_CIW_SEL_33MHZ 0x0800 1199 #define ASC_CIW_IRQ_ACT 0x1000 1200 1201 #define ASC_CC_CHIP_RESET 0x80 1202 #define ASC_CC_SCSI_RESET 0x40 1203 #define ASC_CC_HALT 0x20 1204 #define ASC_CC_SINGLE_STEP 0x10 1205 #define ASC_CC_DMA_ABLE 0x08 1206 #define ASC_CC_TEST 0x04 1207 #define ASC_CC_BANK_ONE 0x02 1208 #define ASC_CC_DIAG 0x01 1209 1210 #define ASC_1000_ID0W 0x04C1 1211 #define ASC_1000_ID0W_FIX 0x00C1 1212 #define ASC_1000_ID1B 0x25 1213 1214 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50) 1215 #define ASC_EISA_SMALL_IOP_GAP (0x0020) 1216 #define ASC_EISA_MIN_IOP_ADDR (0x0C30) 1217 #define ASC_EISA_MAX_IOP_ADDR (0xFC50) 1218 #define ASC_EISA_REV_IOP_MASK (0x0C83) 1219 #define ASC_EISA_PID_IOP_MASK (0x0C80) 1220 #define ASC_EISA_CFG_IOP_MASK (0x0C86) 1221 1222 #define ASC_GET_EISA_SLOT(port_base) ((port_base) & 0xF000) 1223 1224 #define ASC_EISA_ID_740 0x01745004UL 1225 #define ASC_EISA_ID_750 0x01755004UL 1226 1227 #define ASC_INS_HALTINT 0x6281 1228 #define ASC_INS_HALT 0x6280 1229 #define ASC_INS_SINT 0x6200 1230 #define ASC_INS_RFLAG_WTM 0x7380 1231 1232 1233 /******************************************************************************/ 1234 /* Macro */ 1235 /******************************************************************************/ 1236 1237 /* 1238 * These Macros are used to deal with board CPU Registers and LRAM 1239 */ 1240 1241 #define ASC_GET_QDONE_IN_PROGRESS(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B) 1242 #define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val) 1243 #define ASC_GET_VAR_FREE_QHEAD(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W) 1244 #define ASC_GET_VAR_DONE_QTAIL(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W) 1245 #define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val) 1246 #define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val) 1247 #define ASC_GET_RISC_VAR_FREE_QHEAD(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_NEXTRDY_B) 1248 #define ASC_GET_RISC_VAR_DONE_QTAIL(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_DONENEXT_B) 1249 #define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val) 1250 #define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val) 1251 #define ASC_PUT_MCODE_SDTR_DONE_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id), (data)) ; 1252 #define ASC_GET_MCODE_SDTR_DONE_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id)) ; 1253 #define ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id), data) ; 1254 #define ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id)) ; 1255 #define ASC_SYN_INDEX_TO_PERIOD(sc, index) (u_int8_t)((sc)->sdtr_period_tbl[ (index) ]) 1256 #define ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SIG_BYTE) 1257 #define ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_SIG_WORD) 1258 #define ASC_GET_CHIP_VER_NO(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_VERSION) 1259 #define ASC_GET_CHIP_CFG_LSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_LOW) 1260 #define ASC_GET_CHIP_CFG_MSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_HIGH) 1261 #define ASC_SET_CHIP_CFG_LSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_LOW, data) 1262 #define ASC_SET_CHIP_CFG_MSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_HIGH, data) 1263 #define ASC_GET_CHIP_EEP_CMD(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EEP_CMD) 1264 #define ASC_SET_CHIP_EEP_CMD(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EEP_CMD, data) 1265 #define ASC_GET_CHIP_EEP_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_EEP_DATA) 1266 #define ASC_SET_CHIP_EEP_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_EEP_DATA, data) 1267 #define ASC_GET_CHIP_LRAM_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_ADDR) 1268 #define ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_ADDR, addr) 1269 #define ASC_GET_CHIP_LRAM_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA) 1270 #define ASC_SET_CHIP_LRAM_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data) 1271 #if BYTE_ORDER == BIG_ENDIAN 1272 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) SWAPBYTES(bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)) 1273 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, SWAPBYTES(data)) 1274 #else 1275 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA) 1276 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data) 1277 #endif 1278 #define ASC_GET_CHIP_IFC(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IFC) 1279 #define ASC_SET_CHIP_IFC(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IFC, data) 1280 #define ASC_GET_CHIP_STATUS(iot, ioh) (u_int16_t)bus_space_read_2((iot), (ioh), ASC_IOP_STATUS) 1281 #define ASC_SET_CHIP_STATUS(iot, ioh, cs_val) bus_space_write_2((iot), (ioh), ASC_IOP_STATUS, cs_val) 1282 #define ASC_GET_CHIP_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_CTRL) 1283 #define ASC_SET_CHIP_CONTROL(iot, ioh, cc_val) bus_space_write_1((iot), (ioh), ASC_IOP_CTRL, cc_val) 1284 #define ASC_GET_CHIP_SYN(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SYN_OFFSET) 1285 #define ASC_SET_CHIP_SYN(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_SYN_OFFSET, data) 1286 #define ASC_SET_PC_ADDR(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_PC, data) 1287 #define ASC_GET_PC_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_PC) 1288 #define ASC_IS_INT_PENDING(iot, ioh) (ASC_GET_CHIP_STATUS((iot), (ioh)) & (ASC_CSW_INT_PENDING | ASC_CSW_SCSI_RESET_LATCH)) 1289 #define ASC_GET_CHIP_SCSI_ID(iot, ioh) ((ASC_GET_CHIP_CFG_LSW((iot), (ioh)) >> 8) & ASC_MAX_TID) 1290 #define ASC_GET_EXTRA_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL) 1291 #define ASC_SET_EXTRA_CONTROL(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL, data) 1292 #define ASC_READ_CHIP_AX(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_AX) 1293 #define ASC_WRITE_CHIP_AX(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_AX, data) 1294 #define ASC_READ_CHIP_IX(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IX) 1295 #define ASC_WRITE_CHIP_IX(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IX, data) 1296 #define ASC_READ_CHIP_IH(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_IH) 1297 #define ASC_WRITE_CHIP_IH(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_IH, data) 1298 #define ASC_READ_CHIP_QP(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_QP) 1299 #define ASC_WRITE_CHIP_QP(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_QP, data) 1300 #define ASC_READ_CHIP_FIFO_L(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_L) 1301 #define ASC_WRITE_CHIP_FIFO_L(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_L, data) 1302 #define ASC_READ_CHIP_FIFO_H(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_H) 1303 #define ASC_WRITE_CHIP_FIFO_H(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_H, data) 1304 #define ASC_READ_CHIP_DMA_SPEED(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_DMA_SPEED) 1305 #define ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_DMA_SPEED, data) 1306 #define ASC_READ_CHIP_DA0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA0) 1307 #define ASC_WRITE_CHIP_DA0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA0, data) 1308 #define ASC_READ_CHIP_DA1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA1) 1309 #define ASC_WRITE_CHIP_DA1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA1, data) 1310 #define ASC_READ_CHIP_DC0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC0) 1311 #define ASC_WRITE_CHIP_DC0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC0, data) 1312 #define ASC_READ_CHIP_DC1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC1) 1313 #define ASC_WRITE_CHIP_DC1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC1, data) 1314 #define ASC_READ_CHIP_DVC_ID(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_ID) 1315 #define ASC_WRITE_CHIP_DVC_ID(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_ID, data) 1316 1317 1318 /******************************************************************************/ 1319 /* Exported functions */ 1320 /******************************************************************************/ 1321 1322 1323 void AscInitASC_SOFTC(ASC_SOFTC *); 1324 int16_t AscInitFromEEP(ASC_SOFTC *); 1325 u_int16_t AscInitFromASC_SOFTC(ASC_SOFTC *); 1326 int AscInitDriver(ASC_SOFTC *); 1327 void AscReInitLram(ASC_SOFTC *); 1328 int AscFindSignature(bus_space_tag_t, bus_space_handle_t); 1329 u_int8_t AscGetChipIRQ(bus_space_tag_t, bus_space_handle_t, u_int16_t); 1330 u_int16_t AscGetIsaDmaChannel(bus_space_tag_t, bus_space_handle_t); 1331 int AscISR(ASC_SOFTC *); 1332 int AscExeScsiQueue(ASC_SOFTC *, ASC_SCSI_Q *); 1333 void AscInquiryHandling(ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *); 1334 int AscAbortCCB(ASC_SOFTC *, struct adv_ccb *); 1335 int AscResetBus(ASC_SOFTC *); 1336 int AscResetDevice(ASC_SOFTC *, u_char); 1337 1338 1339 /******************************************************************************/ 1340 #endif /* _ADVANSYS_NARROW_LIBRARY_H_ */ 1341
Indexes created Sat Sep 20 22:09:52 GMT 2025