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      1 /*	$NetBSD: dal_asic_id.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012-15 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: AMD
     25  *
     26  */
     27 
     28 #ifndef __DAL_ASIC_ID_H__
     29 #define __DAL_ASIC_ID_H__
     30 
     31 /*
     32  * ASIC internal revision ID
     33  */
     34 
     35 /* DCE80 (based on ci_id.h in Perforce) */
     36 #define	CI_BONAIRE_M_A0 0x14
     37 #define	CI_BONAIRE_M_A1	0x15
     38 #define	CI_HAWAII_P_A0	0x28
     39 
     40 #define CI_UNKNOWN	0xFF
     41 
     42 #define ASIC_REV_IS_BONAIRE_M(rev) \
     43 	((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
     44 
     45 #define ASIC_REV_IS_HAWAII_P(rev) \
     46 	(rev >= CI_HAWAII_P_A0)
     47 
     48 /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
     49 #define KV_SPECTRE_A0 0x01
     50 
     51 /* KV2 with Spooky GFX core, including downgraded from Spectre core,
     52  * 3-4-1-1 (CU-Pix-Primitive-RB) */
     53 #define KV_SPOOKY_A0 0x41
     54 
     55 /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
     56 #define KB_KALINDI_A0 0x81
     57 
     58 /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
     59 #define KB_KALINDI_A1 0x82
     60 
     61 /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
     62 #define BV_KALINDI_A2 0x85
     63 
     64 /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
     65 #define ML_GODAVARI_A0 0xA1
     66 
     67 /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
     68 #define ML_GODAVARI_A1 0xA2
     69 
     70 #define KV_UNKNOWN 0xFF
     71 
     72 #define ASIC_REV_IS_KALINDI(rev) \
     73 	((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
     74 
     75 #define ASIC_REV_IS_BHAVANI(rev) \
     76 	((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
     77 
     78 #define ASIC_REV_IS_GODAVARI(rev) \
     79 	((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
     80 
     81 /* VI Family */
     82 /* DCE10 */
     83 #define VI_TONGA_P_A0 20
     84 #define VI_TONGA_P_A1 21
     85 #define VI_FIJI_P_A0 60
     86 
     87 /* DCE112 */
     88 #define VI_POLARIS10_P_A0 80
     89 #define VI_POLARIS11_M_A0 90
     90 #define VI_POLARIS12_V_A0 100
     91 #define VI_VEGAM_A0 110
     92 
     93 #define VI_UNKNOWN 0xFF
     94 
     95 #define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
     96 		(eChipRev < 40))
     97 #define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
     98 		(eChipRev < 80))
     99 
    100 #define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
    101 		(eChipRev < VI_POLARIS11_M_A0))
    102 #define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) &&  \
    103 		(eChipRev < VI_POLARIS12_V_A0))
    104 #define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \
    105 		(eChipRev < VI_VEGAM_A0))
    106 #define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0)
    107 
    108 /* DCE11 */
    109 #define CZ_CARRIZO_A0 0x01
    110 
    111 #define STONEY_A0 0x61
    112 #define CZ_UNKNOWN 0xFF
    113 
    114 #define ASIC_REV_IS_STONEY(rev) \
    115 	((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
    116 
    117 /* DCE12 */
    118 #define AI_UNKNOWN 0xFF
    119 
    120 #define AI_GREENLAND_P_A0 1
    121 #define AI_GREENLAND_P_A1 2
    122 #define AI_UNKNOWN 0xFF
    123 
    124 #define AI_VEGA12_P_A0 20
    125 #define AI_VEGA20_P_A0 40
    126 #define ASICREV_IS_GREENLAND_M(eChipRev)  (eChipRev < AI_VEGA12_P_A0)
    127 #define ASICREV_IS_GREENLAND_P(eChipRev)  (eChipRev < AI_VEGA12_P_A0)
    128 
    129 #define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_VEGA20_P_A0))
    130 #define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN))
    131 
    132 /* DCN1_0 */
    133 #define INTERNAL_REV_RAVEN_A0             0x00    /* First spin of Raven */
    134 #define RAVEN_A0 0x01
    135 #define RAVEN_B0 0x21
    136 #define PICASSO_A0 0x41
    137 /* DCN1_01 */
    138 #define RAVEN2_A0 0x81
    139 #define RAVEN2_15D8_REV_94 0x94
    140 #define RAVEN2_15D8_REV_95 0x95
    141 #define RAVEN2_15D8_REV_E3 0xE3
    142 #define RAVEN2_15D8_REV_E4 0xE4
    143 #define RAVEN2_15D8_REV_E9 0xE9
    144 #define RAVEN2_15D8_REV_EA 0xEA
    145 #define RAVEN2_15D8_REV_EB 0xEB
    146 #define RAVEN1_F0 0xF0
    147 #define RAVEN_UNKNOWN 0xFF
    148 #ifndef ASICREV_IS_RAVEN
    149 #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
    150 #endif
    151 
    152 #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
    153 #ifndef ASICREV_IS_RAVEN2
    154 #define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RAVEN1_F0))
    155 #endif
    156 #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
    157 #define ASICREV_IS_DALI(eChipRev) ((eChipRev == RAVEN2_15D8_REV_E3) \
    158 		|| (eChipRev == RAVEN2_15D8_REV_E4))
    159 #define ASICREV_IS_POLLOCK(eChipRev) (eChipRev == RAVEN2_15D8_REV_94 \
    160 		|| eChipRev == RAVEN2_15D8_REV_95 \
    161 			|| eChipRev == RAVEN2_15D8_REV_E9 \
    162 				|| eChipRev == RAVEN2_15D8_REV_EA \
    163 					|| eChipRev == RAVEN2_15D8_REV_EB)
    164 
    165 #define FAMILY_RV 142 /* DCN 1*/
    166 
    167 
    168 #define FAMILY_NV 143 /* DCN 2*/
    169 
    170 enum {
    171 	NV_NAVI10_P_A0      = 1,
    172 	NV_NAVI12_P_A0      = 10,
    173 	NV_NAVI14_M_A0      = 20,
    174 	NV_UNKNOWN          = 0xFF
    175 };
    176 
    177 #define ASICREV_IS_NAVI10_P(eChipRev)        (eChipRev < NV_NAVI12_P_A0)
    178 #define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
    179 #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
    180 #define RENOIR_A0 0x91
    181 #define DEVICE_ID_RENOIR_1636 0x1636   // Renoir
    182 #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 0xFF))
    183 
    184 /*
    185  * ASIC chip ID
    186  */
    187 /* DCE80 */
    188 #define DEVICE_ID_KALINDI_9834 0x9834
    189 #define DEVICE_ID_TEMASH_9839 0x9839
    190 #define DEVICE_ID_TEMASH_983D 0x983D
    191 
    192 /* Asic Family IDs for different asic family. */
    193 #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
    194 #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
    195 #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
    196 #define FAMILY_CZ 135 /* Carrizo */
    197 
    198 #define FAMILY_AI 141
    199 
    200 #define	FAMILY_UNKNOWN 0xFF
    201 
    202 
    203 
    204 #endif /* __DAL_ASIC_ID_H__ */
    205