1 /* $NetBSD: disasm.h,v 1.3 2016/08/05 16:45:50 scole Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2006 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: releng/10.1/sys/ia64/disasm/disasm.h 172689 2007-10-16 02:49:40Z marcel $ 29 */ 30 31 #ifndef _DISASM_H_ 32 #define _DISASM_H_ 33 34 #ifndef _DISASM_INT_H_ 35 #define ASM_ADDITIONAL_OPCODES ASM_OP_NUMBER_OF_OPCODES 36 #endif 37 38 /* Application registers. */ 39 #define AR_K0 0 40 #define AR_K1 1 41 #define AR_K2 2 42 #define AR_K3 3 43 #define AR_K4 4 44 #define AR_K5 5 45 #define AR_K6 6 46 #define AR_K7 7 47 #define AR_RSC 16 48 #define AR_BSP 17 49 #define AR_BSPSTORE 18 50 #define AR_RNAT 19 51 #define AR_FCR 21 52 #define AR_EFLAG 24 53 #define AR_CSD 25 54 #define AR_SSD 26 55 #define AR_CFLG 27 56 #define AR_FSR 28 57 #define AR_FIR 29 58 #define AR_FDR 30 59 #define AR_CCV 32 60 #define AR_UNAT 36 61 #define AR_FPSR 40 62 #define AR_ITC 44 63 #define AR_PFS 64 64 #define AR_LC 65 65 #define AR_EC 66 66 67 /* Control registers. */ 68 #define CR_DCR 0 69 #define CR_ITM 1 70 #define CR_IVA 2 71 #define CR_PTA 8 72 #define CR_IPSR 16 73 #define CR_ISR 17 74 #define CR_IIP 19 75 #define CR_IFA 20 76 #define CR_ITIR 21 77 #define CR_IIPA 22 78 #define CR_IFS 23 79 #define CR_IIM 24 80 #define CR_IHA 25 81 #define CR_LID 64 82 #define CR_IVR 65 83 #define CR_TPR 66 84 #define CR_EOI 67 85 #define CR_IRR0 68 86 #define CR_IRR1 69 87 #define CR_IRR2 70 88 #define CR_IRR3 71 89 #define CR_ITV 72 90 #define CR_PMV 73 91 #define CR_CMCV 74 92 #define CR_LRR0 80 93 #define CR_LRR1 81 94 95 enum asm_cmpltr_class { 96 ASM_CC_NONE, 97 ASM_CC_ACLR, 98 ASM_CC_BSW, ASM_CC_BTYPE, ASM_CC_BWH, 99 ASM_CC_CHK, ASM_CC_CLRRRB, ASM_CC_CREL, ASM_CC_CTYPE, 100 ASM_CC_DEP, ASM_CC_DH, 101 ASM_CC_FC, ASM_CC_FCREL, ASM_CC_FCTYPE, ASM_CC_FCVT, ASM_CC_FLDTYPE, 102 ASM_CC_FMERGE, ASM_CC_FREL, ASM_CC_FSWAP, 103 ASM_CC_GETF, 104 ASM_CC_IH, ASM_CC_INVALA, ASM_CC_IPWH, ASM_CC_ITC, ASM_CC_ITR, 105 ASM_CC_LDHINT, ASM_CC_LDTYPE, ASM_CC_LFETCH, ASM_CC_LFHINT, 106 ASM_CC_LFTYPE, ASM_CC_LR, 107 ASM_CC_MF, ASM_CC_MOV, ASM_CC_MWH, 108 ASM_CC_PAVG, ASM_CC_PC, ASM_CC_PH, ASM_CC_PREL, ASM_CC_PRTYPE, 109 ASM_CC_PTC, ASM_CC_PTR, ASM_CC_PVEC, 110 ASM_CC_SAT, ASM_CC_SEM, ASM_CC_SETF, ASM_CC_SF, ASM_CC_SRLZ, 111 ASM_CC_STHINT, ASM_CC_STTYPE, ASM_CC_SYNC, 112 ASM_CC_RW, 113 ASM_CC_TREL, ASM_CC_TRUNC, 114 ASM_CC_UNIT, ASM_CC_UNPACK, ASM_CC_UNS, 115 ASM_CC_VMSW, 116 ASM_CC_XMA 117 }; 118 119 enum asm_cmpltr_type { 120 ASM_CT_NONE, 121 ASM_CT_COND = ASM_CT_NONE, 122 123 ASM_CT_0, ASM_CT_1, 124 ASM_CT_A, ASM_CT_ACQ, ASM_CT_AND, 125 ASM_CT_B, ASM_CT_BIAS, 126 ASM_CT_C_CLR, ASM_CT_C_CLR_ACQ, ASM_CT_C_NC, ASM_CT_CALL, 127 ASM_CT_CEXIT, ASM_CT_CLOOP, ASM_CT_CLR, ASM_CT_CTOP, 128 ASM_CT_D, ASM_CT_DC_DC, ASM_CT_DC_NT, ASM_CT_DPNT, ASM_CT_DPTK, 129 ASM_CT_E, ASM_CT_EQ, ASM_CT_EXCL, ASM_CT_EXIT, ASM_CT_EXP, 130 ASM_CT_F, ASM_CT_FAULT, ASM_CT_FEW, ASM_CT_FILL, ASM_CT_FX, ASM_CT_FXU, 131 ASM_CT_G, ASM_CT_GA, ASM_CT_GE, ASM_CT_GT, 132 ASM_CT_H, ASM_CT_HU, 133 ASM_CT_I, ASM_CT_IA, ASM_CT_IMP, 134 ASM_CT_L, ASM_CT_LE, ASM_CT_LOOP, ASM_CT_LR, ASM_CT_LT, ASM_CT_LTU, 135 ASM_CT_M, ASM_CT_MANY, 136 ASM_CT_NC, ASM_CT_NE, ASM_CT_NEQ, ASM_CT_NL, ASM_CT_NLE, ASM_CT_NLT, 137 ASM_CT_NM, ASM_CT_NR, ASM_CT_NS, ASM_CT_NT_DC, ASM_CT_NT_NT, 138 ASM_CT_NT_TK, ASM_CT_NT1, ASM_CT_NT2, ASM_CT_NTA, ASM_CT_NZ, 139 ASM_CT_OR, ASM_CT_OR_ANDCM, ASM_CT_ORD, 140 ASM_CT_PR, 141 ASM_CT_R, ASM_CT_RAZ, ASM_CT_REL, ASM_CT_RET, ASM_CT_RW, 142 ASM_CT_S, ASM_CT_S0, ASM_CT_S1, ASM_CT_S2, ASM_CT_S3, ASM_CT_SA, 143 ASM_CT_SE, ASM_CT_SIG, ASM_CT_SPILL, ASM_CT_SPNT, ASM_CT_SPTK, 144 ASM_CT_SSS, 145 ASM_CT_TK_DC, ASM_CT_TK_NT, ASM_CT_TK_TK, ASM_CT_TRUNC, 146 ASM_CT_U, ASM_CT_UNC, ASM_CT_UNORD, ASM_CT_USS, ASM_CT_UUS, ASM_CT_UUU, 147 ASM_CT_W, ASM_CT_WEXIT, ASM_CT_WTOP, 148 ASM_CT_X, ASM_CT_XF, 149 ASM_CT_Z, 150 }; 151 152 /* Completer. */ 153 struct asm_cmpltr { 154 enum asm_cmpltr_class c_class; 155 enum asm_cmpltr_type c_type; 156 }; 157 158 /* Operand types. */ 159 enum asm_oper_type { 160 ASM_OPER_NONE, 161 ASM_OPER_AREG, /* = ar# */ 162 ASM_OPER_BREG, /* = b# */ 163 ASM_OPER_CPUID, /* = cpuid[r#] */ 164 ASM_OPER_CREG, /* = cr# */ 165 ASM_OPER_DBR, /* = dbr[r#] */ 166 ASM_OPER_DISP, /* IP relative displacement. */ 167 ASM_OPER_DTR, /* = dtr[r#] */ 168 ASM_OPER_FREG, /* = f# */ 169 ASM_OPER_GREG, /* = r# */ 170 ASM_OPER_IBR, /* = ibr[r#] */ 171 ASM_OPER_IMM, /* Immediate */ 172 ASM_OPER_IP, /* = ip */ 173 ASM_OPER_ITR, /* = itr[r#] */ 174 ASM_OPER_MEM, /* = [r#] */ 175 ASM_OPER_MSR, /* = msr[r#] */ 176 ASM_OPER_PKR, /* = pkr[r#] */ 177 ASM_OPER_PMC, /* = pmc[r#] */ 178 ASM_OPER_PMD, /* = pmd[r#] */ 179 ASM_OPER_PR, /* = pr */ 180 ASM_OPER_PR_ROT, /* = pr.rot */ 181 ASM_OPER_PREG, /* = p# */ 182 ASM_OPER_PSR, /* = psr */ 183 ASM_OPER_PSR_L, /* = psr.l */ 184 ASM_OPER_PSR_UM, /* = psr.um */ 185 ASM_OPER_RR /* = rr[r#] */ 186 }; 187 188 /* Operand */ 189 struct asm_oper { 190 enum asm_oper_type o_type; 191 uint64_t o_value; 192 }; 193 194 /* Instruction formats. */ 195 enum asm_fmt { 196 ASM_FMT_NONE, 197 ASM_FMT_A = 0x0100, 198 ASM_FMT_A1, ASM_FMT_A2, ASM_FMT_A3, ASM_FMT_A4, 199 ASM_FMT_A5, ASM_FMT_A6, ASM_FMT_A7, ASM_FMT_A8, 200 ASM_FMT_A9, ASM_FMT_A10, 201 ASM_FMT_B = 0x0200, 202 ASM_FMT_B1, ASM_FMT_B2, ASM_FMT_B3, ASM_FMT_B4, 203 ASM_FMT_B5, ASM_FMT_B6, ASM_FMT_B7, ASM_FMT_B8, 204 ASM_FMT_B9, 205 ASM_FMT_F = 0x0300, 206 ASM_FMT_F1, ASM_FMT_F2, ASM_FMT_F3, ASM_FMT_F4, 207 ASM_FMT_F5, ASM_FMT_F6, ASM_FMT_F7, ASM_FMT_F8, 208 ASM_FMT_F9, ASM_FMT_F10, ASM_FMT_F11, ASM_FMT_F12, 209 ASM_FMT_F13, ASM_FMT_F14, ASM_FMT_F15, ASM_FMT_F16, 210 ASM_FMT_I = 0x0400, 211 ASM_FMT_I1, ASM_FMT_I2, ASM_FMT_I3, ASM_FMT_I4, 212 ASM_FMT_I5, ASM_FMT_I6, ASM_FMT_I7, ASM_FMT_I8, 213 ASM_FMT_I9, ASM_FMT_I10, ASM_FMT_I11, ASM_FMT_I12, 214 ASM_FMT_I13, ASM_FMT_I14, ASM_FMT_I15, ASM_FMT_I16, 215 ASM_FMT_I17, ASM_FMT_I18, ASM_FMT_I19, ASM_FMT_I20, 216 ASM_FMT_I21, ASM_FMT_I22, ASM_FMT_I23, ASM_FMT_I24, 217 ASM_FMT_I25, ASM_FMT_I26, ASM_FMT_I27, ASM_FMT_I28, 218 ASM_FMT_I29, ASM_FMT_I30, 219 ASM_FMT_M = 0x0500, 220 ASM_FMT_M1, ASM_FMT_M2, ASM_FMT_M3, ASM_FMT_M4, 221 ASM_FMT_M5, ASM_FMT_M6, ASM_FMT_M7, ASM_FMT_M8, 222 ASM_FMT_M9, ASM_FMT_M10, ASM_FMT_M11, ASM_FMT_M12, 223 ASM_FMT_M13, ASM_FMT_M14, ASM_FMT_M15, ASM_FMT_M16, 224 ASM_FMT_M17, ASM_FMT_M18, ASM_FMT_M19, ASM_FMT_M20, 225 ASM_FMT_M21, ASM_FMT_M22, ASM_FMT_M23, ASM_FMT_M24, 226 ASM_FMT_M25, ASM_FMT_M26, ASM_FMT_M27, ASM_FMT_M28, 227 ASM_FMT_M29, ASM_FMT_M30, ASM_FMT_M31, ASM_FMT_M32, 228 ASM_FMT_M33, ASM_FMT_M34, ASM_FMT_M35, ASM_FMT_M36, 229 ASM_FMT_M37, ASM_FMT_M38, ASM_FMT_M39, ASM_FMT_M40, 230 ASM_FMT_M41, ASM_FMT_M42, ASM_FMT_M43, ASM_FMT_M44, 231 ASM_FMT_M45, ASM_FMT_M46, ASM_FMT_M47, ASM_FMT_M48, 232 ASM_FMT_X = 0x0600, 233 ASM_FMT_X1, ASM_FMT_X2, ASM_FMT_X3, ASM_FMT_X4, 234 ASM_FMT_X5 235 }; 236 237 /* Instruction opcodes. */ 238 enum asm_op { 239 ASM_OP_NONE, 240 ASM_OP_ADD, ASM_OP_ADDL, ASM_OP_ADDP4, ASM_OP_ADDS, ASM_OP_ALLOC, 241 ASM_OP_AND, ASM_OP_ANDCM, 242 ASM_OP_BR, ASM_OP_BREAK, ASM_OP_BRL, ASM_OP_BRP, ASM_OP_BSW, 243 ASM_OP_CHK, ASM_OP_CLRRRB, ASM_OP_CMP, ASM_OP_CMP4, ASM_OP_CMP8XCHG16, 244 ASM_OP_CMPXCHG1, ASM_OP_CMPXCHG2, ASM_OP_CMPXCHG4, ASM_OP_CMPXCHG8, 245 ASM_OP_COVER, ASM_OP_CZX1, ASM_OP_CZX2, 246 ASM_OP_DEP, 247 ASM_OP_EPC, ASM_OP_EXTR, 248 ASM_OP_FAMAX, ASM_OP_FAMIN, ASM_OP_FAND, ASM_OP_FANDCM, ASM_OP_FC, 249 ASM_OP_FCHKF, ASM_OP_FCLASS, ASM_OP_FCLRF, ASM_OP_FCMP, ASM_OP_FCVT, 250 ASM_OP_FETCHADD4, ASM_OP_FETCHADD8, ASM_OP_FLUSHRS, ASM_OP_FMA, 251 ASM_OP_FMAX, ASM_OP_FMERGE, ASM_OP_FMIN, ASM_OP_FMIX, ASM_OP_FMS, 252 ASM_OP_FNMA, ASM_OP_FOR, ASM_OP_FPACK, ASM_OP_FPAMAX, ASM_OP_FPAMIN, 253 ASM_OP_FPCMP, ASM_OP_FPCVT, ASM_OP_FPMA, ASM_OP_FPMAX, ASM_OP_FPMERGE, 254 ASM_OP_FPMIN, ASM_OP_FPMS, ASM_OP_FPNMA, ASM_OP_FPRCPA, 255 ASM_OP_FPRSQRTA, ASM_OP_FRCPA, ASM_OP_FRSQRTA, ASM_OP_FSELECT, 256 ASM_OP_FSETC, ASM_OP_FSWAP, ASM_OP_FSXT, ASM_OP_FWB, ASM_OP_FXOR, 257 ASM_OP_GETF, 258 ASM_OP_HINT, 259 ASM_OP_INVALA, ASM_OP_ITC, ASM_OP_ITR, 260 ASM_OP_LD1, ASM_OP_LD16, ASM_OP_LD2, ASM_OP_LD4, ASM_OP_LD8, 261 ASM_OP_LDF, ASM_OP_LDF8, ASM_OP_LDFD, ASM_OP_LDFE, ASM_OP_LDFP8, 262 ASM_OP_LDFPD, ASM_OP_LDFPS, ASM_OP_LDFS, ASM_OP_LFETCH, ASM_OP_LOADRS, 263 ASM_OP_MF, ASM_OP_MIX1, ASM_OP_MIX2, ASM_OP_MIX4, ASM_OP_MOV, 264 ASM_OP_MOVL, ASM_OP_MUX1, ASM_OP_MUX2, 265 ASM_OP_NOP, 266 ASM_OP_OR, 267 ASM_OP_PACK2, ASM_OP_PACK4, ASM_OP_PADD1, ASM_OP_PADD2, ASM_OP_PADD4, 268 ASM_OP_PAVG1, ASM_OP_PAVG2, ASM_OP_PAVGSUB1, ASM_OP_PAVGSUB2, 269 ASM_OP_PCMP1, ASM_OP_PCMP2, ASM_OP_PCMP4, ASM_OP_PMAX1, ASM_OP_PMAX2, 270 ASM_OP_PMIN1, ASM_OP_PMIN2, ASM_OP_PMPY2, ASM_OP_PMPYSHR2, 271 ASM_OP_POPCNT, ASM_OP_PROBE, ASM_OP_PSAD1, ASM_OP_PSHL2, ASM_OP_PSHL4, 272 ASM_OP_PSHLADD2, ASM_OP_PSHR2, ASM_OP_PSHR4, ASM_OP_PSHRADD2, 273 ASM_OP_PSUB1, ASM_OP_PSUB2, ASM_OP_PSUB4, ASM_OP_PTC, ASM_OP_PTR, 274 ASM_OP_RFI, ASM_OP_RSM, ASM_OP_RUM, 275 ASM_OP_SETF, ASM_OP_SHL, ASM_OP_SHLADD, ASM_OP_SHLADDP4, ASM_OP_SHR, 276 ASM_OP_SHRP, ASM_OP_SRLZ, ASM_OP_SSM, ASM_OP_ST1, ASM_OP_ST16, 277 ASM_OP_ST2, ASM_OP_ST4, ASM_OP_ST8, ASM_OP_STF, ASM_OP_STF8, 278 ASM_OP_STFD, ASM_OP_STFE, ASM_OP_STFS, ASM_OP_SUB, ASM_OP_SUM, 279 ASM_OP_SXT1, ASM_OP_SXT2, ASM_OP_SXT4, ASM_OP_SYNC, 280 ASM_OP_TAK, ASM_OP_TBIT, ASM_OP_TF, ASM_OP_THASH, ASM_OP_TNAT, 281 ASM_OP_TPA, ASM_OP_TTAG, 282 ASM_OP_UNPACK1, ASM_OP_UNPACK2, ASM_OP_UNPACK4, 283 ASM_OP_VMSW, 284 ASM_OP_XCHG1, ASM_OP_XCHG2, ASM_OP_XCHG4, ASM_OP_XCHG8, ASM_OP_XMA, 285 ASM_OP_XOR, 286 ASM_OP_ZXT1, ASM_OP_ZXT2, ASM_OP_ZXT4, 287 /* Additional opcodes used only internally. */ 288 ASM_ADDITIONAL_OPCODES 289 }; 290 291 /* Instruction. */ 292 struct asm_inst { 293 uint64_t i_bits; 294 struct asm_oper i_oper[7]; 295 struct asm_cmpltr i_cmpltr[5]; 296 enum asm_fmt i_format; 297 enum asm_op i_op; 298 int i_ncmpltrs; 299 int i_srcidx; 300 }; 301 302 struct asm_bundle { 303 const char *b_templ; 304 struct asm_inst b_inst[3]; 305 }; 306 307 /* Functional units. */ 308 enum asm_unit { 309 ASM_UNIT_NONE, 310 ASM_UNIT_A = 0x0100, /* A unit. */ 311 ASM_UNIT_B = 0x0200, /* B unit. */ 312 ASM_UNIT_F = 0x0300, /* F unit. */ 313 ASM_UNIT_I = 0x0400, /* I unit. */ 314 ASM_UNIT_M = 0x0500, /* M unit. */ 315 ASM_UNIT_X = 0x0600 /* X unit. */ 316 }; 317 318 #ifdef _DISASM_INT_H_ 319 int asm_extract(enum asm_op, enum asm_fmt, uint64_t, struct asm_bundle *, int); 320 #endif 321 322 int asm_decode(uint64_t, struct asm_bundle *); 323 324 void asm_completer(const struct asm_cmpltr *, char *, size_t); 325 void asm_mnemonic(const enum asm_op, char *, size_t); 326 void asm_operand(const struct asm_oper *, char *, size_t, uint64_t); 327 void asm_print_bundle(const struct asm_bundle *, uint64_t); 328 void asm_print_inst(const struct asm_bundle *, int, uint64_t); 329 330 #endif /* _DISASM_H_ */ 331
Indexes created Sat Sep 20 22:09:52 GMT 2025