1 /* $NetBSD: sequoia.h,v 1.6 2021/12/05 07:21:59 msaitoh Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 ** 38 ** MODULE DESCRIPTION: 39 ** 40 ** National Sequoia-1 and Sequoia-2 Definitions 41 ** 42 ** Initial Register Write Values are identified by _INIT 43 ** 44 ** CREATION DATE: 45 ** 46 ** 22-Jan-1997 47 ** 48 ** AUTHOR: 49 ** 50 ** Madeleine D. Robert 51 ** 52 ** MODIFICATION HISTORY: 53 ** 54 ** 27-Jan-1997 Maddy Added additional initial values. 55 ** 56 ** 24-Jan-1997 Maddy Initial Entry. 57 */ 58 59 60 #ifndef SEQUOIAH 61 #define SEQUOIAH 62 63 /**************************************************** 64 ** SEQUOIA ** 65 *****************************************************/ 66 #define SEQUOIA_BASE 0x24 67 #define SEQUOIA_NPORTS 0x4 68 69 #define SEQUOIA_INDEX 0x24 70 #define SEQUOIA_INDEX_OFFSET 0x0 71 72 #define SEQUOIA_DATA 0x26 73 #define SEQUOIA_DATA_OFFSET 0x2 74 75 76 /**************************************************** 77 ** SEQUOIA-1 ** 78 *****************************************************/ 79 80 /* 81 ** Power Management Control Registers 82 ** 83 */ 84 85 /* 86 ** 87 ** PMC Clock Control Register (CCR) - Index 0x000 88 ** 89 ** Loc Size Name Function 90 ** ----- ---- ---- --------------------------------- 91 ** <0> 1 CNCLKSEL0 Conserve Clock Select 0 92 ** <1> 1 CNCLKSEL1 Conserve Clock Select 1 93 ** <2> 1 CNCLKSEL2 Conserve Clock Select 2 94 ** <3> 1 CNSRVEN Conserve Mode Enable 95 ** <4> 1 SLCLKSEL0 Slow Clock Select 0 96 ** <5> 1 SLCLKSEL1 Slow Clock Select 1 97 ** <6> 1 SLCLKSEL2 Slow Clock Select 2 98 ** <7> 1 SLWCLKEN Slow Clock Enable 99 ** <8> 1 SLPSLWEN Sleep Mode, Slow Clock Enable 100 ** <9> 1 DZSLWEN Doze Mode, Slow Clock Enable 101 ** <10> 1 SPNDSLWEN Suspend Mode, Slow Clock Enable 102 ** <11> 1 LBSLWEN Low Battery Slow Enable 103 ** <12> 1 DZONHALT Doze on HALT 104 ** <14> 1 LBST Low Battery Status 105 ** <15> 1 VLBST Very Low Battery Status 106 ** 107 ** <13> Reserved 108 */ 109 #define PMC_CCR_REG 0x000 110 #define PMC_CCR_INIT 0x000 111 #define CCR_V_CNCLKSEL 0 112 #define CCR_M_CNCLKSEL (0x7 << CCR_V_CNCLKSEL) 113 #define CCR_V_CNCLKSEL0 0 114 #define CCR_M_CNCLKSEL0 (1 << CCR_V_CNCLKSEL0) 115 #define CCR_V_CNCLKSEL1 1 116 #define CCR_M_CNCLKSEL1 (1 << CCR_V_CNCLKSEL1) 117 #define CCR_V_CNCLKSEL2 2 118 #define CCR_M_CNCLKSEL2 (1 << CCR_V_CNCLKSEL2) 119 #define CCR_V_CNSRVEN 3 120 #define CCR_M_CNSRVEN (1 << CCR_V_CNSRVEN) 121 #define CCR_V_SLCLKSEL 4 122 #define CCR_M_SLCLKSEL (0x7 << CCR_V_SLCLKSEL) 123 #define CCR_V_SLCLKSEL0 4 124 #define CCR_M_SLCLKSEL0 (1 << CCR_V_SLCLKSEL0) 125 #define CCR_V_SLCLKSEL1 5 126 #define CCR_M_SLCLKSEL1 (1 << CCR_V_SLCLKSEL1) 127 #define CCR_V_SLCLKSEL2 6 128 #define CCR_M_SLCLKSEL2 (1 << CCR_V_SLCLKSEL2) 129 #define CCR_V_SLWCLKEN 7 130 #define CCR_M_SLWCLKEN (1 << CCR_V_SLWCLKEN) 131 #define CCR_V_SLPSLWEN 8 132 #define CCR_M_SLPSLWEN (1 << CCR_V_SLPSLWEN) 133 #define CCR_V_DZSLWEN 9 134 #define CCR_M_DZSLWEN (1 << CCR_V_DZSLWEN) 135 #define CCR_V_SPNDSLWEN 10 136 #define CCR_M_SPNDSLWEN (1 << CCR_V_SPNDSLWEN) 137 #define CCR_V_LBSLWEN 11 138 #define CCR_M_LBSLWEN (1 << CCR_V_LBSLWEN) 139 #define CCR_V_DZONHALT 12 140 #define CCR_M_DZONHALT (1 << CCR_V_DZONHALT) 141 #define CCR_V_LBST 14 142 #define CCR_M_LBST (1 << CCR_V_LBST) 143 #define CCR_V_VLBST 15 144 #define CCR_M_VLBST (1 << CCR_V_VLBST) 145 146 /* 147 ** Conserve Clock Selects 148 */ 149 #define CNCLKSEL_DIV1 0x000 150 #define CNCLKSEL_DIV2 CCR_M_CNCLKSEL0 151 #define CNCLKSEL_DIV4 CCR_M_CNCLKSEL1 152 #define CNCLKSEL_DIV8 (CCR_M_CNCLKSEL0 | CCR_M_CNCLKSEL1) 153 #define CNCLKSEL_DIV16 CCR_M_CNCLKSEL2 154 #define CNCLKSEL_DIV32 (CCR_M_CNCLKSEL0 | CCR_M_CNCLKSEL2) 155 #define CNCLKSEL_DIV64 (CCR_M_CNCLKSEL1 | CCR_M_CNCLKSEL2) 156 157 /* 158 ** Slow Clock Selects 159 */ 160 #define SLCLKSEL_DIV1 0x000 161 #define SLCLKSEL_DIV2 CCR_M_SLCLKSEL0 162 #define SLCLKSEL_DIV4 CCR_M_SLCLKSEL1 163 #define SLCLKSEL_DIV8 (CCR_M_SLCLKSEL0 | CCR_M_SLCLKSEL1) 164 #define SLCLKSEL_DIV16 CCR_M_SLCLKSEL2 165 #define SLCLKSEL_DIV32 (CCR_M_SLCLKSEL0 | CCR_M_SLCLKSEL2) 166 #define SLCLKSEL_DIV64 (CCR_M_SLCLKSEL1 | CCR_M_SLCLKSEL2) 167 #define SLCLKSEL_STOPPED (CCR_M_SLCLKSEL0 | CCR_M_SLCLKSEL1 | CCR_M_SLCLKSEL2) 168 169 /* 170 ** 171 ** Power Management Status Register (PMSR) - Index 0x001 172 ** 173 ** Loc Size Name Function 174 ** ----- ---- ---- --------------------------------- 175 ** <0> 1 WAKESRC0 Wake-up Source 0 176 ** <1> 1 WAKESRC1 Wake-up Source 1 177 ** <2> 1 WAKESRC2 Wake-up Source 2 178 ** <3> 1 ACPWR AC Power 179 ** <4> 1 PMISRC0 Power Management Interrupt 0 180 ** <5> 1 PMISRC1 Power Management Interrupt 1 181 ** <6> 1 PMISRC2 Power Management Interrupt 2 182 ** <7> 1 PMISRC3 Power Management Interrupt 3 183 ** <8> 1 PMISRC4 Power Management Interrupt 4 184 ** <9> 1 RESUME Resume 185 ** <10> 1 WAKE0STATUS Wake 0 Status 186 ** <11> 1 WAKE1STATUS Wake 1 Status 187 ** <13> 1 PMMD0 Power Management Mode 0 188 ** <14> 1 PMMD1 Power Management Mode 1 189 ** <15> 1 PMMD2 Power Management Mode 2 190 ** 191 ** <12> Reserved 192 */ 193 #define PMC_PMSR_REG 0x001 194 #define PMC_PMSR_INIT ( PMSR_M_WAKESRC | PMSR_M_PMISRC | PMMD_ON ) 195 #define PMSR_V_WAKESRC 0 196 #define PMSR_M_WAKESRC (0x7 << PMSR_V_WAKESRC) 197 #define PMSR_V_WAKESRC0 0 198 #define PMSR_M_WAKESRC0 (1 << PMSR_V_WAKESRC0) 199 #define PMSR_V_WAKESRC1 1 200 #define PMSR_M_WAKESRC1 (1 << PMSR_V_WAKESRC1) 201 #define PMSR_V_WAKESRC2 2 202 #define PMSR_M_WAKESRC2 (1 << PMSR_V_WAKESRC2) 203 #define PMSR_V_ACPWR 3 204 #define PMSR_M_ACPWR (1 << PMSR_V_ACPWR) 205 #define PMSR_V_PMISRC 4 206 #define PMSR_M_PMISRC (0x1F << PMSR_V_PMISRC) 207 #define PMSR_V_PMISRC0 4 208 #define PMSR_M_PMISRC0 (1 << PMSR_V_PMISRC0) 209 #define PMSR_V_PMISRC1 5 210 #define PMSR_M_PMISRC1 (1 << PMSR_V_PMISRC1) 211 #define PMSR_V_PMISRC2 6 212 #define PMSR_M_PMISRC2 (1 << PMSR_V_PMISRC2) 213 #define PMSR_V_PMISRC3 7 214 #define PMSR_M_PMISRC3 (1 << PMSR_V_PMISRC3) 215 #define PMSR_V_PMISRC4 8 216 #define PMSR_M_PMISRC4 (1 << PMSR_V_PMISRC4) 217 #define PMSR_V_RESUME 9 218 #define PMSR_M_RESUME (1 << PMSR_V_RESUME) 219 #define PMSR_V_WAKE0STATUS 10 220 #define PMSR_M_WAKE0STATUS (1 << PMSR_V_WAKE0STATUS) 221 #define PMSR_V_WAKE1STATUS 11 222 #define PMSR_M_WAKE1STATUS (1 << PMSR_V_WAKE1STATUS) 223 #define PMSR_V_PMMD 13 224 #define PMSR_M_PMMD (0x7 << PMSR_V_PMMD) 225 #define PMSR_V_PMMD0 13 226 #define PMSR_M_PMMD0 (1 << PMSR_V_PMMD0) 227 #define PMSR_V_PMMD1 14 228 #define PMSR_M_PMMD1 (1 << PMSR_V_PMMD1) 229 #define PMSR_V_PMMD2 15 230 #define PMSR_M_PMMD2 (1 << PMSR_V_PMMD2) 231 232 /* 233 ** Wake-up Source 234 */ 235 #define WAKESRC_NONE 0x000 236 #define WAKESRC_RING PMSR_M_WAKESRC0 237 #define WAKESRC_RTCI PMSR_M_WAKESRC1 238 #define WAKESRC_SWTCH (PMSR_M_WAKESRC0 | PMSR_M_WAKESRC1) 239 #define WAKESRC_GPTC PMSR_M_WAKESRC2 240 #define WAKESRC_WAKE0 (PMSR_M_WAKESRC0 | PMSR_M_WAKESRC2) 241 #define WAKESRC_WAKE1 (PMSR_M_WAKESRC1 | PMSR_M_WAKESRC2) 242 #define WAKESRC_WAKECLR (PMSR_M_WAKESRC0 | PMSR_M_WAKESRC1 | PMSR_M_WAKESRC2) 243 244 /* 245 ** Power Management Interrupt Source 246 */ 247 #define PMISRC_NONE 0x000 248 #define PMISRC_IRQI PMSR_M_PMISRC0 249 #define PMISRC_LBC PMSR_M_PMISRC1 250 #define PMISRC_SUSTO (PMSR_M_PMISRC0 | PMSR_M_PMISRC1) 251 #define PMISRC_SLPTO PMSR_M_PMISRC2 252 #define PMISRC_DZTO (PMSR_M_PMISRC0 | PMSR_M_PMISRC2) 253 #define PMISRC_GENTO (PMSR_M_PMISRC1 | PMSR_M_PMISRC2) 254 #define PMISRC_GENACT (PMSR_M_PMISRC0 | PMSR_M_PMISRC1 | PMSR_M_PMISRC2) 255 #define PMISRC_PRIACT PMSR_M_PMISRC3 256 #define PMISRC_SCDACT (PMSR_M_PMISRC0 | PMSR_M_PMISRC3) 257 #define PMISRC_SCDACTTO (PMSR_M_PMISRC1 | PMSR_M_PMISRC3) 258 #define PMISRC_SWTCH (PMSR_M_PMISRC0 | PMSR_M_PMISRC1 | PMSR_M_PMISRC3) 259 #define PMISRC_ACPWR (PMSR_M_PMISRC2 | PMSR_M_PMISRC3) 260 #define PMISRC_PRGTTO (PMSR_M_PMISRC0 | PMSR_M_PMISRC2 | PMSR_M_PMISRC3) 261 #define PMISRC_GPTCOMP (PMSR_M_PMISRC1 | PMSR_M_PMISRC2 | PMSR_M_PMISRC3) 262 #define PMISRC_RTC (PMSR_M_PMISRC0 | PMSR_M_PMISRC4) 263 #define PMISRC_RESCHPMI (PMSR_M_PMISRC1 | PMSR_M_PMISRC4) 264 #define PMISRC_SWSMI (PMSR_M_PMISRC0 | PMSR_M_PMISRC1 | PMSR_M_PMISRC4) 265 266 /* 267 ** Power Management Mode 268 */ 269 #define PMMD_STDBY 0x000 270 #define PMMD_ON PMSR_M_PMMD0 271 #define PMMD_CONSERVE PMSR_M_PMMD1 272 #define PMMD_DOZE (PMSR_M_PMMD0 | PMSR_M_PMMD1) 273 #define PMMD_SLEEP PMSR_M_PMMD2 274 #define PMMD_SUSPEND (PMSR_M_PMMD0 | PMSR_M_PMMD2) 275 276 277 /* 278 ** 279 ** Activity Source Register (ASR) - Index 0x002 280 ** 281 ** Loc Size Name Function 282 ** ----- ---- ---- --------------------------------- 283 ** <0> 1 VIDACTV Video Active 284 ** <1> 1 HDACTV Hard Disk Active 285 ** <2> 1 FLPACTV Floppy Disk Active 286 ** <3> 1 KBDACTV Keyboard Active 287 ** <4> 1 SIOACTV Serial I/O Active 288 ** <5> 1 PIOACTV Parallel I/O Active 289 ** <6> 1 PROG0ACTV PRM 0 Active 290 ** <7> 1 PROG1ACTV PRM 1 Active 291 ** <8> 1 PROG2ACTV PRM 2 Active 292 ** <9> 1 PROG3ACTV PRM 3 Active 293 ** <12> 1 EXT0ACTV Primary Activity Mask EXTACT0 294 ** <13> 1 EXT1ACTV Primary Activity Mask EXTACT1 295 ** <14> 1 EXT2ACTV Primary Activity Mask EXTACT2 296 ** <15> 1 EXT3ACTV Primary Activity Mask EXTACT3 297 ** 298 ** <10:11> Reserved 299 */ 300 #define PMC_ASR_REG 0x002 301 #define PMC_ASR_INIT 0x0000 302 #define ASR_V_VIDACTV 0 303 #define ASR_M_VIDACTV (1 << ASR_V_VIDACTV) 304 #define ASR_V_HDACTV 1 305 #define ASR_M_HDACTV (1 << ASR_V_HDACTV) 306 #define ASR_V_FLPACTV 2 307 #define ASR_M_FLPACTV (1 << ASR_V_FLPACTV) 308 #define ASR_V_KBDACTV 3 309 #define ASR_M_KBDACTV (1 << ASR_V_KBDACTV) 310 #define ASR_V_SIOACTV 4 311 #define ASR_M_SIOACTV (1 << ASR_V_SIOACTV) 312 #define ASR_V_PIOACTV 5 313 #define ASR_M_PIOACTV (1 << ASR_V_PIOACTV) 314 #define ASR_V_PROG0ACTV 6 315 #define ASR_M_PROG0ACTV (1 << ASR_V_PROG0ACTV) 316 #define ASR_V_PROG1ACTV 7 317 #define ASR_M_PROG1ACTV (1 << ASR_V_PROG1ACTV) 318 #define ASR_V_PROG2ACTV 8 319 #define ASR_M_PROG2ACTV (1 << ASR_V_PROG2ACTV) 320 #define ASR_V_PROG3ACTV 9 321 #define ASR_M_PROG3ACTV (1 << ASR_V_PROG3ACTV) 322 #define ASR_V_EXT0ACTV 12 323 #define ASR_M_EXT0ACTV (1 << ASR_V_EXT0ACTV) 324 #define ASR_V_EXT1ACTV 13 325 #define ASR_M_EXT1ACTV (1 << ASR_V_EXT1ACTV) 326 #define ASR_V_EXT2ACTV 14 327 #define ASR_M_EXT2ACTV (1 << ASR_V_EXT2ACTV) 328 #define ASR_V_EXT3ACTV 15 329 #define ASR_M_EXT3ACTV (1 << ASR_V_EXT3ACTV) 330 331 /* 332 ** 333 ** Primary Activity Mask Register (PAMR) - Index 0x003 334 ** 335 ** Loc Size Name Function 336 ** ----- ---- ---- --------------------------------- 337 ** <0> 1 PAMSKVID PAM Video Accesses 338 ** <1> 1 PAMSKHD PAM Hard Disk Accesses 339 ** <2> 1 PAMSKFLP PAM Floppy Accesses 340 ** <3> 1 PAMSKKDB PAM Keyboard Accesses 341 ** <4> 1 PAMSKSIO PAM Serial I/O Accesses 342 ** <5> 1 PAMSKPIO PAM Parallel I/O Accesses 343 ** <6> 1 PAMSKPROG0 PAM Programmable Range 0 344 ** <7> 1 PAMSKPROG1 PAM Programmable Range 1 345 ** <8> 1 PAMSKPROG2 PAM Programmable Range 2 346 ** <9> 1 PAMSKPROG3 PAM Programmable Range 3 347 ** <12> 1 PAMSKEACT0 PAM EXTACT0 348 ** <13> 1 PAMSKEACT1 PAM EXTACT1 349 ** <14> 1 PAMSKEACT2 PAM EXTACT2 350 ** <15> 1 PAMSKEACT3 PAM EXTACT3 351 ** 352 ** <10:11> Reserved 353 */ 354 #define PMC_PAMR_REG 0x003 355 #define PMC_PAMR_INIT 0x0000 356 #define PAMR_V_PAMSKVID 0 357 #define PAMR_M_PAMSKVID (1 << PAMR_V_PAMSKVID) 358 #define PAMR_V_PAMSKHD 1 359 #define PAMR_M_PAMSKHD (1 << PAMR_V_PAMSKHD) 360 #define PAMR_V_PAMSKFLP 2 361 #define PAMR_M_PAMSKFLP (1 << PAMR_V_PAMSKFLP) 362 #define PAMR_V_PAMSKKDB 3 363 #define PAMR_M_PAMSKKDB (1 << PAMR_V_PAMSKKDB) 364 #define PAMR_V_PAMSKSIO 4 365 #define PAMR_M_PAMSKSIO (1 << PAMR_V_PAMSKSIO) 366 #define PAMR_V_PAMSKPIO 5 367 #define PAMR_M_PAMSKPIO (1 << PAMR_V_PAMSKPIO) 368 #define PAMR_V_PAMSKPROG0 6 369 #define PAMR_M_PAMSKPROG0 (1 << PAMR_V_PAMSKPROG0) 370 #define PAMR_V_PAMSKPROG1 7 371 #define PAMR_M_PAMSKPROG1 (1 << PAMR_V_PAMSKPROG1) 372 #define PAMR_V_PAMSKPROG2 8 373 #define PAMR_M_PAMSKPROG2 (1 << PAMR_V_PAMSKPROG2) 374 #define PAMR_V_PAMSKPROG3 9 375 #define PAMR_M_PAMSKPROG3 (1 << PAMR_V_PAMSKPROG3) 376 #define PAMR_V_PAMSKEACT0 12 377 #define PAMR_M_PAMSKEACT0 (1 << PAMR_V_PAMSKEACT0) 378 #define PAMR_V_PAMSKEACT1 13 379 #define PAMR_M_PAMSKEACT1 (1 << PAMR_V_PAMSKEACT1) 380 #define PAMR_V_PAMSKEACT2 14 381 #define PAMR_M_PAMSKEACT2 (1 << PAMR_V_PAMSKEACT2) 382 #define PAMR_V_PAMSKEACT3 15 383 #define PAMR_M_PAMSKEACT3 (1 << PAMR_V_PAMSKEACT3) 384 385 /* 386 ** 387 ** PMI Mask Register (PMIMR) - Index 0x004 388 ** 389 ** Loc Size Name Function 390 ** ----- ---- ---- --------------------------------- 391 ** <0> 1 IMSKVID PMI Mask Video Accesses 392 ** <1> 1 IMSKHD PMI Mask Hard Disk Accesses 393 ** <2> 1 IMSKFLP PMI Mask Floppy Accesses 394 ** <3> 1 IMSKKDB PMI Mask Keyboard Accesses 395 ** <4> 1 IMSKSIO PMI Mask Serial I/O Accesses 396 ** <5> 1 IMSKPIO PMI Mask Parallel I/O Accesses 397 ** <6> 1 IMSKPROG0 PMI Mask Programmable Range 0 398 ** <7> 1 IMSKPROG1 PMI Mask Programmable Range 1 399 ** <8> 1 IMSKPROG2 PMI Mask Programmable Range 2 400 ** <9> 1 IMSKPROG3 PMI Mask Programmable Range 3 401 ** <12> 1 IMSKEACT0 PMI Mask EXTACT0 402 ** <13> 1 IMSKEACT1 PMI Mask EXTACT1 403 ** <14> 1 IMSKEACT2 PMI Mask EXTACT2 404 ** <15> 1 IMSKEACT3 PMI Mask EXTACT3 405 ** 406 ** <10:11> Reserved 407 */ 408 #define PMC_PMIMR_REG 0x004 409 #define PMC_PMIMR_INIT ( PMIMR_M_IMSKVID | PMIMR_M_IMSKHD | \ 410 PMIMR_M_IMSKFLP | PMIMR_M_IMSKKDB | \ 411 PMIMR_M_IMSKSIO | PMIMR_M_IMSKPIO | \ 412 PMIMR_M_IMSKPROG0 | PMIMR_M_IMSKPROG1 | \ 413 PMIMR_M_IMSKPROG2 | PMIMR_M_IMSKPROG3 | \ 414 PMIMR_M_IMSKEACT0 | PMIMR_M_IMSKEACT1 | \ 415 PMIMR_M_IMSKEACT2 | PMIMR_M_IMSKEACT3 ) 416 #define PMIMR_V_IMSKVID 0 417 #define PMIMR_M_IMSKVID (1 << PMIMR_V_IMSKVID) 418 #define PMIMR_V_IMSKHD 1 419 #define PMIMR_M_IMSKHD (1 << PMIMR_V_IMSKHD) 420 #define PMIMR_V_IMSKFLP 2 421 #define PMIMR_M_IMSKFLP (1 << PMIMR_V_IMSKFLP) 422 #define PMIMR_V_IMSKKDB 3 423 #define PMIMR_M_IMSKKDB (1 << PMIMR_V_IMSKKDB) 424 #define PMIMR_V_IMSKSIO 4 425 #define PMIMR_M_IMSKSIO (1 << PMIMR_V_IMSKSIO) 426 #define PMIMR_V_IMSKPIO 5 427 #define PMIMR_M_IMSKPIO (1 << PMIMR_V_IMSKPIO) 428 #define PMIMR_V_IMSKPROG0 6 429 #define PMIMR_M_IMSKPROG0 (1 << PMIMR_V_IMSKPROG0) 430 #define PMIMR_V_IMSKPROG1 7 431 #define PMIMR_M_IMSKPROG1 (1 << PMIMR_V_IMSKPROG1) 432 #define PMIMR_V_IMSKPROG2 8 433 #define PMIMR_M_IMSKPROG2 (1 << PMIMR_V_IMSKPROG2) 434 #define PMIMR_V_IMSKPROG3 9 435 #define PMIMR_M_IMSKPROG3 (1 << PMIMR_V_IMSKPROG3) 436 #define PMIMR_V_IMSKEACT0 12 437 #define PMIMR_M_IMSKEACT0 (1 << PMIMR_V_IMSKEACT0) 438 #define PMIMR_V_IMSKEACT1 13 439 #define PMIMR_M_IMSKEACT1 (1 << PMIMR_V_IMSKEACT1) 440 #define PMIMR_V_IMSKEACT2 14 441 #define PMIMR_M_IMSKEACT2 (1 << PMIMR_V_IMSKEACT2) 442 #define PMIMR_V_IMSKEACT3 15 443 #define PMIMR_M_IMSKEACT3 (1 << PMIMR_V_IMSKEACT3) 444 445 /* 446 ** 447 ** Heat Regulator Control Register (HRCR) - Index 0x005 448 ** 449 ** Loc Size Name Function 450 ** ----- ---- ---- --------------------------------- 451 ** <0> 1 HTRGDLY0 Heat Regulator Delay 0 452 ** <1> 1 HTRGDLY1 Heat Regulator Delay 1 453 ** <2> 1 HTRGDLY2 Heat Regulator Delay 2 454 ** <3> 1 HTRGRAT0 Heat Regulator Ratio 0 455 ** <4> 1 HTRGRAT1 Heat Regulator Ratio 1 456 ** <5> 1 HTRGRAT2 Heat Regulator Ratio 2 457 ** <6> 1 HTRGEN Heat Regulator Enable 458 ** <7> 1 HTRGLOCK Heat Regulator Configuration Lock 459 ** <14> 1 FRCSLWEN Force SLOW Enable 460 ** <15> 1 FRCSLWLOCK Force Slow Lock 461 ** 462 ** <8:13> Reserved 463 */ 464 #define PMC_HRCR_REG 0x005 465 #define PMC_HRCR_INIT 0x0000 466 #define HRCR_V_HTRGDLY 0 467 #define HRCR_M_HTRGDLY (0x7 << HRCR_V_HTRGDLY) 468 #define HRCR_V_HTRGDLY0 0 469 #define HRCR_M_HTRGDLY0 (1 << HRCR_V_HTRGDLY0) 470 #define HRCR_V_HTRGDLY1 1 471 #define HRCR_M_HTRGDLY1 (1 << HRCR_V_HTRGDLY1) 472 #define HRCR_V_HTRGDLY2 2 473 #define HRCR_M_HTRGDLY2 (1 << HRCR_V_HTRGDLY2) 474 #define HRCR_V_HTRGRAT 3 475 #define HRCR_M_HTRGRAT (0x7 << HRCR_V_HTRGRAT) 476 #define HRCR_V_HTRGRAT0 3 477 #define HRCR_M_HTRGRAT0 (1 << HRCR_V_HTRGRAT0) 478 #define HRCR_V_HTRGRAT1 4 479 #define HRCR_M_HTRGRAT1 (1 << HRCR_V_HTRGRAT1) 480 #define HRCR_V_HTRGRAT2 5 481 #define HRCR_M_HTRGRAT2 (1 << HRCR_V_HTRGRAT2) 482 #define HRCR_V_HTRGEN 6 483 #define HRCR_M_HTRGEN (1 << HRCR_V_HTRGEN) 484 #define HRCR_V_HTRGLOCK 7 485 #define HRCR_M_HTRGLOCK (1 << HRCR_V_HTRGLOCK) 486 #define HRCR_V_FRCSLWEN 14 487 #define HRCR_M_FRCSLWEN (1 << HRCR_V_FRCSLWEN) 488 #define HRCR_V_FRCSLWLOCK 15 489 #define HRCR_M_FRCSLWLOCK (1 << HRCR_V_FRCSLWLOCK) 490 491 /* 492 ** Heater Regulator Delay 493 */ 494 #define HTRGDLY_16SEC 0x000 495 #define HTRGDLY_32SEC HRCR_M_HTRGDLY0 496 #define HTRGDLY_60SEC HRCR_M_HTRGDLY1 497 #define HTRGDLY_120SEC HRCR_M_HTRGDLY2 498 #define HTRGDLY_240SEC (HRCR_M_HTRGDLY1 | HRCR_M_HTRGDLY2) 499 #define HTRGDLY_480SEC (HRCR_M_HTRGDLY0 | HRCR_M_HTRGDLY1 | HRCR_M_HTRGDLY2) 500 501 /* 502 ** Heater Regulator Ratio (Percent) 503 */ 504 #define HTRGRAT_50 0x000 505 #define HTRGRAT_66 HRCR_M_HTRGRAT0 506 #define HTRGRAT_80 HRCR_M_HTRGRAT1 507 #define HTRGRAT_90 (HRCR_M_HTRGRAT0 | HRCR_M_HTRGRAT1) 508 509 /* 510 ** 511 ** PMI Mask and Control Register (PMIMCR) - Index 0x006 512 ** 513 ** Loc Size Name Function 514 ** ----- ---- ---- --------------------------------- 515 ** <0> 1 IMSKSQ2PMI Mask SEQUOIA-2 Source from PMI 516 ** <1> 1 IMSKLB Mask Low Battery from PMI 517 ** <2> 1 IMSKSPNDTO Mask Suspend Time-out from PMI 518 ** <3> 1 IMSKSLPTO Mask Sleep Time-out from PMI 519 ** <4> 1 IMSKDZTO Mask Doze Time-out from PMI 520 ** <5> 1 IMSKGENTO Mask Generic Time-out from PMI 521 ** <6> 1 IMSKACTV Mask Generic Activity from PMI 522 ** <7> 1 IMSKPACTV Mask Primary Activity from PMI 523 ** <8> 1 IMSKSACTV Mask Secondary Activity from PMI 524 ** <10> 1 IMSKSWSTBY Mask SWTCH from PMI 525 ** <11> 1 IMSKACPWR Mask ACPWR from PMI 526 ** <12> 1 IMSKPROGTO Mask Programmable Time-out from PMI 527 ** <13> 1 IMSKGPTMR Mask GP Timer from PMI 528 ** 529 ** <9><14:15> Reserved 530 */ 531 #define PMC_PMIMCR_REG 0x006 532 #define PMC_PMIMCR_INIT ( PMIMCR_M_IMSKSQ2PMI | PMIMCR_M_IMSKLB | \ 533 PMIMCR_M_IMSKSPNDTO | PMIMCR_M_IMSKSLPTO | \ 534 PMIMCR_M_IMSKDZTO | PMIMCR_M_IMSKGENTO | \ 535 PMIMCR_M_IMSKACTV | PMIMCR_M_IMSKPACTV | \ 536 PMIMCR_M_IMSKSACTV | PMIMCR_M_IMSKSWSTBY | \ 537 PMIMCR_M_IMSKACPWR | PMIMCR_M_IMSKPROGTO | \ 538 PMIMCR_M_IMSKGPTMR ) 539 #define PMIMCR_V_IMSKSQ2PMI 0 540 #define PMIMCR_M_IMSKSQ2PMI (1 << PMIMCR_V_IMSKSQ2PMI) 541 #define PMIMCR_V_IMSKLB 1 542 #define PMIMCR_M_IMSKLB (1 << PMIMCR_V_IMSKLB) 543 #define PMIMCR_V_IMSKSPNDTO 2 544 #define PMIMCR_M_IMSKSPNDTO (1 << PMIMCR_V_IMSKSPNDTO) 545 #define PMIMCR_V_IMSKSLPTO 3 546 #define PMIMCR_M_IMSKSLPTO (1 << PMIMCR_V_IMSKSLPTO) 547 #define PMIMCR_V_IMSKDZTO 4 548 #define PMIMCR_M_IMSKDZTO (1 << PMIMCR_V_IMSKDZTO) 549 #define PMIMCR_V_IMSKGENTO 5 550 #define PMIMCR_M_IMSKGENTO (1 << PMIMCR_V_IMSKGENTO) 551 #define PMIMCR_V_IMSKACTV 6 552 #define PMIMCR_M_IMSKACTV (1 << PMIMCR_V_IMSKACTV) 553 #define PMIMCR_V_IMSKPACTV 7 554 #define PMIMCR_M_IMSKPACTV (1 << PMIMCR_V_IMSKPACTV) 555 #define PMIMCR_V_IMSKSACTV 8 556 #define PMIMCR_M_IMSKSACTV (1 << PMIMCR_V_IMSKSACTV) 557 #define PMIMCR_V_IMSKSWSTBY 10 558 #define PMIMCR_M_IMSKSWSTBY (1 << PMIMCR_V_IMSKSWSTBY) 559 #define PMIMCR_V_IMSKACPWR 11 560 #define PMIMCR_M_IMSKACPWR (1 << PMIMCR_V_IMSKACPWR) 561 #define PMIMCR_V_IMSKPROGTO 12 562 #define PMIMCR_M_IMSKPROGTO (1 << PMIMCR_V_IMSKPROGTO) 563 #define PMIMCR_V_IMSKGPTMR 13 564 #define PMIMCR_M_IMSKGPTMR (1 << PMIMCR_V_IMSKGPTMR) 565 566 /* 567 ** 568 ** General Purpose Control Register (GPCR) - Index 0x007 569 ** 570 ** Loc Size Name Function 571 ** ----- ---- ---- --------------------------------- 572 ** <0> 1 ACDISCNSRV ACPWR Disable Conserve Mode 573 ** <1> 1 ACON ACPWR On 574 ** <2> 1 REFRPRD0 Refresh Period 0 575 ** <3> 1 REFRPRD1 Refresh Period 1 576 ** <4> 1 REFRPRD2 Refresh Period 2 577 ** <5> 1 SLFREFEN Self Refresh Enable 578 ** <6> 1 RINGS0 Modem RING Select 0 579 ** <7> 1 RINGS1 Modem RING Select 1 580 ** <8> 1 GPIODATA0 General Purpose I/O Data 0 581 ** <9> 1 GPIODATA1 General Purpose I/O Data 1 582 ** <10> 1 GPIODATA2 General Purpose I/O Data 2 583 ** <11> 1 GPIODATA3 General Purpose I/O Data 3 584 ** <12> 1 GPIODIR0 General Purpose I/O Direction 0 585 ** <13> 1 GPIODIR1 General Purpose I/O Direction 1 586 ** <14> 1 GPIODIR2 General Purpose I/O Direction 2 587 ** <15> 1 GPIODIR3 General Purpose I/O Direction 3 588 ** 589 */ 590 #define PMC_GPCR_REG 0x007 591 #define PMC_GPCR_INIT ( REFRPRD_STOPPED | GPCR_M_GPIODIR0 | \ 592 GPCR_M_GPIODIR1 ) 593 #define GPCR_V_ACDISCNSRV 0 594 #define GPCR_M_ACDISCNSRV (1 << GPCR_V_ACDISCNSRV) 595 #define GPCR_V_ACON 1 596 #define GPCR_M_ACON (1 << GPCR_V_ACON) 597 #define GPCR_V_REFRPRD 2 598 #define GPCR_M_REFRPRD (0x7 << GPCR_V_REFRPRD) 599 #define GPCR_V_REFRPRD0 2 600 #define GPCR_M_REFRPRD0 (1 << GPCR_V_REFRPRD0) 601 #define GPCR_V_REFRPRD1 3 602 #define GPCR_M_REFRPRD1 (1 << GPCR_V_REFRPRD1) 603 #define GPCR_V_REFRPRD2 4 604 #define GPCR_M_REFRPRD2 (1 << GPCR_V_REFRPRD2) 605 #define GPCR_V_SLFREFEN 5 606 #define GPCR_M_SLFREFEN (1 << GPCR_V_SLFREFEN) 607 #define GPCR_V_RINGS 6 608 #define GPCR_M_RINGS (0x3 << GPCR_V_RINGS) 609 #define GPCR_V_GPIODATA 8 610 #define GPCR_M_GPIODATA (0xF << GPCR_V_GPIODATA) 611 #define GPCR_V_GPIODATA0 8 612 #define GPCR_M_GPIODATA0 (1 << GPCR_V_GPIODATA0) 613 #define GPCR_V_GPIODATA1 9 614 #define GPCR_M_GPIODATA1 (1 << GPCR_V_GPIODATA1) 615 #define GPCR_V_GPIODATA2 10 616 #define GPCR_M_GPIODATA2 (1 << GPCR_V_GPIODATA2) 617 #define GPCR_V_GPIODATA3 11 618 #define GPCR_M_GPIODATA3 (1 << GPCR_V_GPIODATA3) 619 #define GPCR_V_GPIODIR 12 620 #define GPCR_M_GPIODIR (0xF << GPCR_V_GPIODIR) 621 #define GPCR_V_GPIODIR0 12 622 #define GPCR_M_GPIODIR0 (1 << GPCR_V_GPIODIR0) 623 #define GPCR_V_GPIODIR1 13 624 #define GPCR_M_GPIODIR1 (1 << GPCR_V_GPIODIR1) 625 #define GPCR_V_GPIODIR2 14 626 #define GPCR_M_GPIODIR2 (1 << GPCR_V_GPIODIR2) 627 #define GPCR_V_GPIODIR3 15 628 #define GPCR_M_GPIODIR3 (1 << GPCR_V_GPIODIR3) 629 630 /* 631 ** Refresh Period 632 */ 633 #define REFRPRD_15US 0x000 634 #define REFRPRD_30US GPCR_M_REFRPRD0 635 #define REFRPRD_120US GPCR_M_REFRPRD1 636 #define REFRPRD_STOPPED GPCR_M_REFRPRD2 637 #define REFRPRD_60US (GPCR_M_REFRPRD1 | GPCR_M_REFRPRD2) 638 639 /* 640 ** 641 ** Stop Clock Control Register (SCCR) - Index 0x008 642 ** 643 ** Loc Size Name Function 644 ** ----- ---- ---- --------------------------------- 645 ** <0> 1 STPGLBEN Stop Clock Global Enable 646 ** <1> 1 MORESTOP More Stop Enable 647 ** <2> 1 STPRELDLY0 STPCLK Release Delay 0 648 ** <3> 1 STPRELDLY1 STPCLK Release Delay 1 649 ** <4> 1 GRNTDLY0 STPCLK Latency Delay Select 0 650 ** <5> 1 GRNTDLY1 STPCLK Latency Delay Select 1 651 ** <6> 1 WMSKINTR Wake Mask INTR 652 ** <7> 1 WAIT4GRNT Wait for Stop Grant 653 ** <9> 1 IOTRAPDIS I/O Trap Disable 654 ** <10> 1 SVNCLKPLS SMI PULSE Width Select 655 ** <11> 1 PCSTGSEL0 PC Staggering Select 0 656 ** <12> 1 PCSTGSEL1 PC Staggering Select 1 657 ** <13> 1 PCSTGDIS PC Stagger Disable 658 ** <14> 1 PCSLWEN PC Slow Enable 659 ** 660 ** <8><15> Reserved 661 */ 662 #define PMC_SCCR_REG 0x008 663 #define PMC_SCCR_INIT SCCR_M_WMSKINTR 664 #define SCCR_V_STPGLBEN 0 665 #define SCCR_M_STPGLBEN (1 << SCCR_V_STPGLBEN) 666 #define SCCR_V_MORESTOP 1 667 #define SCCR_M_MORESTOP (1 << SCCR_V_MORESTOP) 668 #define SCCR_V_STPRELDLY 2 669 #define SCCR_M_STPRELDLY (0x3 << SCCR_V_STPRELDLY) 670 #define SCCR_V_STPRELDLY0 2 671 #define SCCR_M_STPRELDLY0 (1 << SCCR_V_STPRELDLY0) 672 #define SCCR_V_STPRELDLY1 3 673 #define SCCR_M_STPRELDLY1 (1 << SCCR_V_STPRELDLY1) 674 #define SCCR_V_GRNTDLY 4 675 #define SCCR_M_GRNTDLY (0x3 << SCCR_V_GRNTDLY) 676 #define SCCR_V_GRNTDLY0 4 677 #define SCCR_M_GRNTDLY0 (1 << SCCR_V_GRNTDLY0) 678 #define SCCR_V_GRNTDLY1 5 679 #define SCCR_M_GRNTDLY1 (1 << SCCR_V_GRNTDLY1) 680 #define SCCR_V_WMSKINTR 6 681 #define SCCR_M_WMSKINTR (1 << SCCR_V_WMSKINTR) 682 #define SCCR_V_WAIT4GRNT 7 683 #define SCCR_M_WAIT4GRNT (1 << SCCR_V_WAIT4GRNT) 684 #define SCCR_V_IOTRAPDIS 9 685 #define SCCR_M_IOTRAPDIS (1 << SCCR_V_IOTRAPDIS) 686 #define SCCR_V_SVNCLKPLS 10 687 #define SCCR_M_SVNCLKPLS (1 << SCCR_V_SVNCLKPLS) 688 #define SCCR_V_PCSTGSEL 11 689 #define SCCR_M_PCSTGSEL (0x3 << SCCR_V_PCSTGSEL) 690 #define SCCR_V_PCSTGSEL0 11 691 #define SCCR_M_PCSTGSEL0 (1 << SCCR_V_PCSTGSEL0) 692 #define SCCR_V_PCSTGSEL1 12 693 #define SCCR_M_PCSTGSEL1 (1 << SCCR_V_PCSTGSEL1) 694 #define SCCR_V_PCSTGDIS 13 695 #define SCCR_M_PCSTGDIS (1 << SCCR_V_PCSTGDIS) 696 #define SCCR_V_PCSLWEN 14 697 #define SCCR_M_PCSLWEN (1 << SCCR_V_PCSLWEN) 698 699 /* 700 ** STPCLK Release Delay 701 */ 702 #define STPRELDLY_0S 0x000 703 #define STPRELDLY_1US SCCR_M_STPRELDLY0 704 #define STPRELDLY_45US SCCR_M_STPRELDLY1 705 #define STPRELDLY_1MS (SCCR_M_STPRELDLY0 | SCCR_M_STPRELDLY1) 706 707 /* 708 ** STPCLK Release Delay Select 709 */ 710 #define GRNTDLY_GRANTBUS 0x000 711 #define GRNTDLY_30US SCCR_M_GRNTDLY0 712 #define GRNTDLY_125US SCCR_M_GRNTDLY1 713 #define GRNTDLY_1MS (SCCR_M_GRNTDLY0 | SCCR_M_GRNTDLY1) 714 715 /* 716 ** PC Staggering Select 717 */ 718 #define PCSTGSEL_240US 0x000 719 #define PCSTGSEL_4US SCCR_M_PCSTGSEL0 720 #define PCSTGSEL_16US SCCR_M_PCSTGSEL1 721 #define PCSTGSEL_64MS (SCCR_M_PCSTGSEL0 | SCCR_M_PCSTGSEL1) 722 723 /* 724 ** 725 ** Fully-On Mode Power Control Register (FOMPCR) - Index 0x009 726 ** 727 ** Loc Size Name Function 728 ** ----- ---- ---- --------------------------------- 729 ** <0> 1 PCON0 Power Control Fully-On Mode 0 730 ** <1> 1 PCON1 Power Control Fully-On Mode 1 731 ** <2> 1 PCON2 Power Control Fully-On Mode 2 732 ** <3> 1 PCON3 Power Control Fully-On Mode 3 733 ** <4> 1 PCON4 Power Control Fully-On Mode 4 734 ** <5> 1 PCON5 Power Control Fully-On Mode 5 735 ** <6> 1 PCON6 Power Control Fully-On Mode 6 736 ** <7> 1 PCON7 Power Control Fully-On Mode 7 737 ** <8> 1 PCON8 Power Control Fully-On Mode 8 738 ** <9> 1 PCON9 Power Control Fully-On Mode 9 739 ** <10> 1 GLBLPCEN Global Power Control Enable 740 ** 741 ** <11:15> Reserved 742 */ 743 #define PMC_FOMPCR_REG 0x009 744 #define PMC_FOMPCR_INIT ( FOMPCR_M_PCON0 | FOMPCR_M_PCON1 ) 745 #define FOMPCR_V_PCON 0 746 #define FOMPCR_M_PCON (0x3FF << FOMPCR_V_PCON) 747 #define FOMPCR_V_PCON0 0 748 #define FOMPCR_M_PCON0 (1U << FOMPCR_V_PCON0) 749 #define FOMPCR_V_PCON1 1 750 #define FOMPCR_M_PCON1 (1U << FOMPCR_V_PCON1) 751 #define FOMPCR_V_PCON2 2 752 #define FOMPCR_M_PCON2 (1U << FOMPCR_V_PCON2) 753 #define FOMPCR_V_PCON3 3 754 #define FOMPCR_M_PCON3 (1U << FOMPCR_V_PCON3) 755 #define FOMPCR_V_PCON4 4 756 #define FOMPCR_M_PCON4 (1U << FOMPCR_V_PCON4) 757 #define FOMPCR_V_PCON5 5 758 #define FOMPCR_M_PCON5 (1U << FOMPCR_V_PCON5) 759 #define FOMPCR_V_PCON6 6 760 #define FOMPCR_M_PCON6 (1U << FOMPCR_V_PCON6) 761 #define FOMPCR_V_PCON7 7 762 #define FOMPCR_M_PCON7 (1U << FOMPCR_V_PCON7) 763 #define FOMPCR_V_PCON8 8 764 #define FOMPCR_M_PCON8 (1U << FOMPCR_V_PCON8) 765 #define FOMPCR_V_PCON9 9 766 #define FOMPCR_M_PCON9 (1U << FOMPCR_V_PCON9) 767 #define FOMPCR_V_GLBLPCEN 10 768 #define FOMPCR_M_GLBLPCEN (1U << FOMPCR_V_GLBLPCEN) 769 770 /* 771 ** 772 ** Doze Mode Power Control Register (DZMPCR) - Index 0x00A 773 ** 774 ** Loc Size Name Function 775 ** ----- ---- ---- --------------------------------- 776 ** <0> 1 PCDZ0 Power Control Doze Mode 0 777 ** <1> 1 PCDZ1 Power Control Doze Mode 1 778 ** <2> 1 PCDZ2 Power Control Doze Mode 2 779 ** <3> 1 PCDZ3 Power Control Doze Mode 3 780 ** <4> 1 PCDZ4 Power Control Doze Mode 4 781 ** <5> 1 PCDZ5 Power Control Doze Mode 5 782 ** <6> 1 PCDZ6 Power Control Doze Mode 6 783 ** <7> 1 PCDZ7 Power Control Doze Mode 7 784 ** <8> 1 PCDZ8 Power Control Doze Mode 8 785 ** <9> 1 PCDZ9 Power Control Doze Mode 9 786 ** <10> 1 SPNDDLY Suspend Delay 787 ** <11> 1 STRTDLY Start Delay 788 ** 789 ** <12:15> Reserved 790 */ 791 #define PMC_DZMPCR_REG 0x00A 792 #define PMC_DZMPCR_INIT ( DZMPCR_M_PCDZ0 | DZMPCR_M_PCDZ1 | \ 793 DZMPCR_M_PCDZ2 ) 794 #define DZMPCR_V_PCDZ 0 795 #define DZMPCR_M_PCDZ (0x3FF << DZMPCR_V_PCDZ) 796 #define DZMPCR_V_PCDZ0 0 797 #define DZMPCR_M_PCDZ0 (1 << DZMPCR_V_PCDZ0) 798 #define DZMPCR_V_PCDZ1 1 799 #define DZMPCR_M_PCDZ1 (1 << DZMPCR_V_PCDZ1) 800 #define DZMPCR_V_PCDZ2 2 801 #define DZMPCR_M_PCDZ2 (1 << DZMPCR_V_PCDZ2) 802 #define DZMPCR_V_PCDZ3 3 803 #define DZMPCR_M_PCDZ3 (1 << DZMPCR_V_PCDZ3) 804 #define DZMPCR_V_PCDZ4 4 805 #define DZMPCR_M_PCDZ4 (1 << DZMPCR_V_PCDZ4) 806 #define DZMPCR_V_PCDZ5 5 807 #define DZMPCR_M_PCDZ5 (1 << DZMPCR_V_PCDZ5) 808 #define DZMPCR_V_PCDZ6 6 809 #define DZMPCR_M_PCDZ6 (1 << DZMPCR_V_PCDZ6) 810 #define DZMPCR_V_PCDZ7 7 811 #define DZMPCR_M_PCDZ7 (1 << DZMPCR_V_PCDZ7) 812 #define DZMPCR_V_PCDZ8 8 813 #define DZMPCR_M_PCDZ8 (1 << DZMPCR_V_PCDZ8) 814 #define DZMPCR_V_PCDZ9 9 815 #define DZMPCR_M_PCDZ9 (1 << DZMPCR_V_PCDZ9) 816 #define DZMPCR_V_SPNDDLY 10 817 #define DZMPCR_M_SPNDDLY (1 << DZMPCR_V_SPNDDLY) 818 #define DZMPCR_V_STRTDLY 11 819 #define DZMPCR_M_STRTDLY (1 << DZMPCR_V_STRTDLY) 820 821 /* 822 ** 823 ** Sleep Mode Power Control Register (SLPMPCR) - Index 0x00B 824 ** 825 ** Loc Size Name Function 826 ** ----- ---- ---- --------------------------------- 827 ** <0> 1 PCSLP0 Power Control Sleep Mode 0 828 ** <1> 1 PCSLP1 Power Control Sleep Mode 1 829 ** <2> 1 PCSLP2 Power Control Sleep Mode 2 830 ** <3> 1 PCSLP3 Power Control Sleep Mode 3 831 ** <4> 1 PCSLP4 Power Control Sleep Mode 4 832 ** <5> 1 PCSLP5 Power Control Sleep Mode 5 833 ** <6> 1 PCSLP6 Power Control Sleep Mode 6 834 ** <7> 1 PCSLP7 Power Control Sleep Mode 7 835 ** <8> 1 PCSLP8 Power Control Sleep Mode 8 836 ** <9> 1 PCSLP9 Power Control Sleep Mode 9 837 ** <10> 1 LBLEDFLSH Low Battery LED Flasher Enable 838 ** <11> 1 LBFLSHRAT0 Low Battery LED Flash Rate Selects 0 839 ** <12> 1 LBFLSHRAT1 Low Battery LED Flash Rate Selects 1 840 ** <13> 1 LBFLSHDUR0 Low Battery LED Flash Rate Duration 0 841 ** <14> 1 LBFLSHDUR1 Low Battery LED Flash Rate Duration 1 842 ** <15> 1 VLBFLSHEN Very Low Battery Flash Enable 843 ** 844 */ 845 #define PMC_SLPMPCR_REG 0x00B 846 #define PMC_SLPMPCR_INIT ( SLPMPCR_M_PCSLP0 | SLPMPCR_M_PCSLP1 | \ 847 SLPMPCR_M_PCSLP2 | LBFLSHRAT_2HZ | \ 848 LBFLSHDUR_62PT5MS ) 849 #define SLPMPCR_V_PCSLP 0 850 #define SLPMPCR_M_PCSLP (0x3FF << SLPMPCR_V_PCSLP) 851 #define SLPMPCR_V_PCSLP0 0 852 #define SLPMPCR_M_PCSLP0 (1 << SLPMPCR_V_PCSLP0) 853 #define SLPMPCR_V_PCSLP1 1 854 #define SLPMPCR_M_PCSLP1 (1 << SLPMPCR_V_PCSLP1) 855 #define SLPMPCR_V_PCSLP2 2 856 #define SLPMPCR_M_PCSLP2 (1 << SLPMPCR_V_PCSLP2) 857 #define SLPMPCR_V_PCSLP3 3 858 #define SLPMPCR_M_PCSLP3 (1 << SLPMPCR_V_PCSLP3) 859 #define SLPMPCR_V_PCSLP4 4 860 #define SLPMPCR_M_PCSLP4 (1 << SLPMPCR_V_PCSLP4) 861 #define SLPMPCR_V_PCSLP5 5 862 #define SLPMPCR_M_PCSLP5 (1 << SLPMPCR_V_PCSLP5) 863 #define SLPMPCR_V_PCSLP6 6 864 #define SLPMPCR_M_PCSLP6 (1 << SLPMPCR_V_PCSLP6) 865 #define SLPMPCR_V_PCSLP7 7 866 #define SLPMPCR_M_PCSLP7 (1 << SLPMPCR_V_PCSLP7) 867 #define SLPMPCR_V_PCSLP8 8 868 #define SLPMPCR_M_PCSLP8 (1 << SLPMPCR_V_PCSLP8) 869 #define SLPMPCR_V_PCSLP9 9 870 #define SLPMPCR_M_PCSLP9 (1 << SLPMPCR_V_PCSLP9) 871 #define SLPMPCR_V_LBLEDFLSH 10 872 #define SLPMPCR_M_LBLEDFLSH (1 << SLPMPCR_V_LBLEDFLSH) 873 #define SLPMPCR_V_LBFLSHRAT 11 874 #define SLPMPCR_M_LBFLSHRAT (0x3 << SLPMPCR_V_LBFLSHRAT) 875 #define SLPMPCR_V_LBFLSHRAT0 11 876 #define SLPMPCR_M_LBFLSHRAT0 (1 << SLPMPCR_V_LBFLSHRAT0) 877 #define SLPMPCR_V_LBFLSHRAT1 12 878 #define SLPMPCR_M_LBFLSHRAT1 (1 << SLPMPCR_V_LBFLSHRAT1) 879 #define SLPMPCR_V_LBFLSHDUR 13 880 #define SLPMPCR_M_LBFLSHDUR (0x3 << SLPMPCR_V_LBFLSHDUR) 881 #define SLPMPCR_V_LBFLSHDUR0 13 882 #define SLPMPCR_M_LBFLSHDUR0 (1 << SLPMPCR_V_LBFLSHDUR0) 883 #define SLPMPCR_V_LBFLSHDUR1 14 884 #define SLPMPCR_M_LBFLSHDUR1 (1 << SLPMPCR_V_LBFLSHDUR1) 885 #define SLPMPCR_V_VLBFLSHEN 15 886 #define SLPMPCR_M_VLBFLSHEN (1 << SLPMPCR_V_VLBFLSHEN) 887 888 /* 889 ** Low Battery LED Flash Rate Selects 890 */ 891 #define LBFLSHRAT_HLFHZ 0x000 892 #define LBFLSHRAT_1HZ SLPMPCR_M_LBFLSHRAT0 893 #define LBFLSHRAT_2HZ SLPMPCR_M_LBFLSHRAT1 894 #define LBFLSHRAT_4HZ (SLPMPCR_M_LBFLSHRAT0 | SLPMPCR_M_LBFLSHRAT1) 895 896 /* 897 ** Low Battery LED Flash Rate Duration (milliseconds) 898 */ 899 #define LBFLSHDUR_256MS 0x000 900 #define LBFLSHDUR_128MS SLPMPCR_M_LBFLSHDUR0 901 #define LBFLSHDUR_62PT5MS SLPMPCR_M_LBFLSHDUR1 902 #define LBFLSHDUR_31PT25MS (SLPMPCR_M_LBFLSHDUR0 | SLPMPCR_M_LBFLSHDUR1) 903 904 905 /* 906 ** 907 ** Suspend Mode Power Control Register (SPNDMPCR) - Index 0x00C 908 ** 909 ** Loc Size Name Function 910 ** ----- ---- ---- --------------------------------- 911 ** <0> 1 PCSPND0 Power Control Suspend Mode 0 912 ** <1> 1 PCSPND1 Power Control Suspend Mode 1 913 ** <2> 1 PCSPND2 Power Control Suspend Mode 2 914 ** <3> 1 PCSPND3 Power Control Suspend Mode 3 915 ** <4> 1 PCSPND4 Power Control Suspend Mode 4 916 ** <5> 1 PCSPND5 Power Control Suspend Mode 5 917 ** <6> 1 PCSPND6 Power Control Suspend Mode 6 918 ** <7> 1 PCSPND7 Power Control Suspend Mode 7 919 ** <8> 1 PCSPND8 Power Control Suspend Mode 8 920 ** <9> 1 PCSPND9 Power Control Suspend Mode 9 921 ** <10> 1 SPLEDFLSH Suspend LED Flasher Enable 922 ** <11> 1 SPFLSHRAT0 Suspend LED Flash Rate Selects 0 923 ** <12> 1 SPFLSHRAT1 Suspend LED Flash Rate Selects 1 924 ** <13> 1 SPFLSHDUR0 Suspend LED Flash Rate Duration 0 925 ** <14> 1 SPFLSHDUR1 Suspend LED Flash Rate Duration 1 926 ** 927 ** <15> Reserved 928 ** 929 */ 930 #define PMC_SPNDMPCR_REG 0x00c 931 #define PMC_SPNDMPCR_INIT ( SPNDMPCR_M_PCSPND0 | SPNDMPCR_M_PCSPND1 | \ 932 SPNDMPCR_M_PCSPND2 | SPFLSHRAT_2HZ | \ 933 SPFLSHDUR_62PT5MS ) 934 #define SPNDMPCR_V_PCSPND 0 935 #define SPNDMPCR_M_PCSPND (0x3FF << SPNDMPCR_V_PCSPND) 936 #define SPNDMPCR_V_PCSPND0 0 937 #define SPNDMPCR_M_PCSPND0 (1 << SPNDMPCR_V_PCSPND0) 938 #define SPNDMPCR_V_PCSPND1 1 939 #define SPNDMPCR_M_PCSPND1 (1 << SPNDMPCR_V_PCSPND1) 940 #define SPNDMPCR_V_PCSPND2 2 941 #define SPNDMPCR_M_PCSPND2 (1 << SPNDMPCR_V_PCSPND2) 942 #define SPNDMPCR_V_PCSPND3 3 943 #define SPNDMPCR_M_PCSPND3 (1 << SPNDMPCR_V_PCSPND3) 944 #define SPNDMPCR_V_PCSPND4 4 945 #define SPNDMPCR_M_PCSPND4 (1 << SPNDMPCR_V_PCSPND4) 946 #define SPNDMPCR_V_PCSPND5 5 947 #define SPNDMPCR_M_PCSPND5 (1 << SPNDMPCR_V_PCSPND5) 948 #define SPNDMPCR_V_PCSPND6 6 949 #define SPNDMPCR_M_PCSPND6 (1 << SPNDMPCR_V_PCSPND6) 950 #define SPNDMPCR_V_PCSPND7 7 951 #define SPNDMPCR_M_PCSPND7 (1 << SPNDMPCR_V_PCSPND7) 952 #define SPNDMPCR_V_PCSPND8 8 953 #define SPNDMPCR_M_PCSPND8 (1 << SPNDMPCR_V_PCSPND8) 954 #define SPNDMPCR_V_PCSPND9 9 955 #define SPNDMPCR_M_PCSPND9 (1 << SPNDMPCR_V_PCSPND9) 956 #define SPNDMPCR_V_SPLEDFLSH 10 957 #define SPNDMPCR_M_SPLEDFLSH (1 << SPNDMPCR_V_SPLEDFLSH) 958 #define SPNDMPCR_V_SPFLSHRAT 11 959 #define SPNDMPCR_M_SPFLSHRAT (0x3 << SPNDMPCR_V_SPFLSHRAT) 960 #define SPNDMPCR_V_SPFLSHRAT0 11 961 #define SPNDMPCR_M_SPFLSHRAT0 (1 << SPNDMPCR_V_SPFLSHRAT0) 962 #define SPNDMPCR_V_SPFLSHRAT1 12 963 #define SPNDMPCR_M_SPFLSHRAT1 (1 << SPNDMPCR_V_SPFLSHRAT1) 964 #define SPNDMPCR_V_SPFLSHDUR 13 965 #define SPNDMPCR_M_SPFLSHDUR (0x3 << SPNDMPCR_V_SPFLSHDUR) 966 #define SPNDMPCR_V_SPFLSHDUR0 13 967 #define SPNDMPCR_M_SPFLSHDUR0 (1 << SPNDMPCR_V_SPFLSHDUR0) 968 #define SPNDMPCR_V_SPFLSHDUR1 14 969 #define SPNDMPCR_M_SPFLSHDUR1 (1 << SPNDMPCR_V_SPFLSHDUR1) 970 971 /* 972 ** Suspend LED Flash Rate Selects 973 */ 974 #define SPFLSHRAT_HLFHZ 0x000 975 #define SPFLSHRAT_1HZ SPNDMPCR_M_SPFLSHRAT0 976 #define SPFLSHRAT_2HZ SPNDMPCR_M_SPFLSHRAT1 977 #define SPFLSHRAT_4HZ (SPNDMPCR_M_SPFLSHRAT0 | SPNDMPCR_M_SPFLSHRAT1) 978 979 /* 980 ** Suspend LED Flash Rate Duration (milliseconds) 981 */ 982 #define SPFLSHDUR_256MS 0x000 983 #define SPFLSHDUR_128MS SPNDMPCR_M_SPFLSHDUR0 984 #define SPFLSHDUR_62PT5MS SPNDMPCR_M_SPFLSHDUR1 985 #define SPFLSHDUR_31PT25MS (SPNDMPCR_M_SPFLSHDUR0 | SPNDMPCR_M_SPFLSHDUR1) 986 987 /* 988 ** 989 ** Timer Register (TIMERR) - Index 0x00D 990 ** 991 ** Loc Size Name Function 992 ** ----- ---- ---- --------------------------------- 993 ** <0> 1 GENTMR0 Generic Timer 0 994 ** <1> 1 GENTMR1 Generic Timer 1 995 ** <2> 1 GENTMR2 Generic Timer 2 996 ** <3> 1 GENTMR3 Generic Timer 3 997 ** <4> 1 SPMDTMR0 Suspend Mode Timer 0 998 ** <5> 1 SPMDTMR1 Suspend Mode Timer 1 999 ** <6> 1 SPMDTMR2 Suspend Mode Timer 2 1000 ** <7> 1 SLPTMR0 Sleep Mode Timer 0 1001 ** <8> 1 SLPTMR1 Sleep Mode Timer 1 1002 ** <9> 1 SLPTMR2 Sleep Mode Timer 2 1003 ** <10> 1 DZTMR0 Doze Mode Timer 0 1004 ** <11> 1 DZTMR1 Doze Mode Timer 1 1005 ** <12> 1 DZTMR2 Doze Mode Timer 2 1006 ** <15> 1 GTRSTPADIS Generic Timer Reset by PA Disable 1007 ** 1008 ** <13:14> Reserved 1009 ** 1010 */ 1011 #define PMC_TIMERR_REG 0x00D 1012 #define PMC_TIMERR_INIT 0x0000 1013 #define TIMERR_V_GENTMR 0 1014 #define TIMERR_M_GENTMR (0xF << TIMERR_V_GENTMR) 1015 #define TIMERR_V_GENTMR0 0 1016 #define TIMERR_M_GENTMR0 (1 << TIMERR_V_GENTMR0) 1017 #define TIMERR_V_GENTMR1 1 1018 #define TIMERR_M_GENTMR1 (1 << TIMERR_V_GENTMR1) 1019 #define TIMERR_V_GENTMR2 2 1020 #define TIMERR_M_GENTMR2 (1 << TIMERR_V_GENTMR2) 1021 #define TIMERR_V_GENTMR3 3 1022 #define TIMERR_M_GENTMR3 (1 << TIMERR_V_GENTMR3) 1023 #define TIMERR_V_SPMDTMR 4 1024 #define TIMERR_M_SPMDTMR (0x7 << TIMERR_V_SPMDTMR) 1025 #define TIMERR_V_SPMDTMR0 4 1026 #define TIMERR_M_SPMDTMR0 (1 << TIMERR_V_SPMDTMR0) 1027 #define TIMERR_V_SPMDTMR1 5 1028 #define TIMERR_M_SPMDTMR1 (1 << TIMERR_V_SPMDTMR1) 1029 #define TIMERR_V_SPMDTMR2 6 1030 #define TIMERR_M_SPMDTMR2 (1 << TIMERR_V_SPMDTMR2) 1031 #define TIMERR_V_SLPTMR 7 1032 #define TIMERR_M_SLPTMR (0x7 << TIMERR_V_SLPTMR) 1033 #define TIMERR_V_SLPTMR0 7 1034 #define TIMERR_M_SLPTMR0 (1 << TIMERR_V_SLPTMR0) 1035 #define TIMERR_V_SLPTMR1 8 1036 #define TIMERR_M_SLPTMR1 (1 << TIMERR_V_SLPTMR1) 1037 #define TIMERR_V_SLPTMR2 9 1038 #define TIMERR_M_SLPTMR2 (1 << TIMERR_V_SLPTMR2) 1039 #define TIMERR_V_DZTMR 10 1040 #define TIMERR_M_DZTMR (0x7 << TIMERR_V_DZTMR) 1041 #define TIMERR_V_DZTMR0 10 1042 #define TIMERR_M_DZTMR0 (1 << TIMERR_V_DZTMR0) 1043 #define TIMERR_V_DZTMR1 11 1044 #define TIMERR_M_DZTMR1 (1 << TIMERR_V_DZTMR1) 1045 #define TIMERR_V_DZTMR2 12 1046 #define TIMERR_M_DZTMR2 (1 << TIMERR_V_DZTMR2) 1047 #define TIMERR_V_GTRSTPADIS 15 1048 #define TIMERR_M_GTRSTPADIS (1 << TIMERR_V_GTRSTPADIS) 1049 1050 /* 1051 ** Generic Timer (Seconds) 1052 */ 1053 #define GENTMR_DISABLE 0x000 1054 #define GENTMR_2S TIMERR_M_GENTMR0 1055 #define GENTMR_4S TIMERR_M_GENTMR1 1056 #define GENTMR_6S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1) 1057 #define GENTMR_8S TIMERR_M_GENTMR2 1058 #define GENTMR_10S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR2) 1059 #define GENTMR_15S (TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2) 1060 #define GENTMR_20S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2) 1061 #define GENTMR_25S TIMERR_M_GENTMR3 1062 #define GENTMR_30S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR3) 1063 #define GENTMR_40S (TIMERR_M_GENTMR1 | TIMERR_M_GENTMR3) 1064 #define GENTMR_50S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1 | TIMERR_M_GENTMR3) 1065 #define GENTMR_60S (TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) 1066 #define GENTMR_75S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) 1067 #define GENTMR_90S (TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) 1068 #define GENTMR_120S (TIMERR_M_GENTMR0 | TIMERR_M_GENTMR1 | TIMERR_M_GENTMR2 | TIMERR_M_GENTMR3) 1069 1070 /* 1071 ** Suspend Mode Timer (Minutes) 1072 */ 1073 #define SPMDTMR_DISABLE 0x000 1074 #define SPMDTMR_5MIN TIMERR_M_SPMDTMR0 1075 #define SPMDTMR_10MIN TIMERR_M_SPMDTMR1 1076 #define SPMDTMR_15MIN (TIMERR_M_SPMDTMR0 | TIMERR_M_SPMDTMR1) 1077 #define SPMDTMR_20MIN TIMERR_M_SPMDTMR2 1078 #define SPMDTMR_30MIN (TIMERR_M_SPMDTMR0 | TIMERR_M_SPMDTMR2) 1079 #define SPMDTMR_40MIN (TIMERR_M_SPMDTMR1 | TIMERR_M_SPMDTMR2) 1080 #define SPMDTMR_60MIN (TIMERR_M_SPMDTMR0 | TIMERR_M_SPMDTMR1 | TIMERR_M_SPMDTMR2) 1081 1082 /* 1083 ** Sleep Mode Timer (Minutes) 1084 */ 1085 #define SLPTMR_DISABLE 0x000 1086 #define SLPTMR_1MIN TIMERR_M_SLPTMR0 1087 #define SLPTMR_2MIN TIMERR_M_SLPTMR1 1088 #define SLPTMR_4MIN (TIMERR_M_SLPTMR0 | TIMERR_M_SLPTMR1) 1089 #define SLPTMR_6MIN TIMERR_M_SLPTMR2 1090 #define SLPTMR_8MIN (TIMERR_M_SLPTMR0 | TIMERR_M_SLPTMR2) 1091 #define SLPTMR_12MIN (TIMERR_M_SLPTMR1 | TIMERR_M_SLPTMR2) 1092 #define SLPTMR_16MIN (TIMERR_M_SLPTMR0 | TIMERR_M_SLPTMR1 | TIMERR_M_SLPTMR2) 1093 1094 /* 1095 ** Doze Mode Timer (Seconds) 1096 */ 1097 #define DZTMR_DISABLE 0x000 1098 #define DZTMR_PT125S TIMERR_M_DZTMR0 1099 #define DZTMR_PT250S TIMERR_M_DZTMR1 1100 #define DZTMR_PT500S (TIMERR_M_DZTMR0 | TIMERR_M_DZTMR1) 1101 #define DZTMR_1S TIMERR_M_DZTMR2 1102 #define DZTMR_4S (TIMERR_M_DZTMR0 | TIMERR_M_DZTMR2) 1103 #define DZTMR_8S (TIMERR_M_DZTMR1 | TIMERR_M_DZTMR2) 1104 #define DZTMR_16S (TIMERR_M_DZTMR0 | TIMERR_M_DZTMR1 | TIMERR_M_DZTMR2) 1105 1106 /* 1107 ** 1108 ** PMC Miscellaneous Control 1 Register (PMCMCR1) - Index 0x00E 1109 ** 1110 ** Loc Size Name Function 1111 ** ----- ---- ---- --------------------------------- 1112 ** <2> 1 GPCTSEL0 General Purpose Counter/Timer Select 0 1113 ** <3> 1 GPCTSEL1 General Purpose Counter/Timer Select 1 1114 ** <4> 1 GPCTEN Generic Purpose Counter/Timer Enable 1115 ** <5> 1 WMSKVLBNAC Wake Mask VLB if Not ACPWR 1116 ** <6> 1 WAKE0MSK WAKE0 Mask 1117 ** <7> 1 WAKE1MSK WAKE1 Mask 1118 ** <8> 1 WMSKRING Wake Mask RING 1119 ** <9> 1 WMSKRTC Wake Mask RTC 1120 ** <11> 1 WMSKTMR Wake Mask GP Timer 1121 ** <12> 1 PRDCTID0 Product Identification 0 1122 ** <13> 1 PRDCTID1 Product Identification 1 1123 ** <14> 1 PRDCTID2 Product Identification 2 1124 ** <15> 1 PRDCTID3 Product Identification 3 1125 ** 1126 ** <0:1><10> Reserved 1127 ** 1128 */ 1129 #define PMC_PMCMCR1_REG 0x00E 1130 #define PMC_PMCMCR1_INIT ( PMCMCR1_M_WMSKVLBNAC | PMCMCR1_M_WAKE0MSK | \ 1131 PMCMCR1_M_WAKE1MSK | PMCMCR1_M_WMSKRING | \ 1132 PMCMCR1_M_WMSKRTC | PMCMCR1_M_WMSKTMR ) 1133 #define PMCMCR1_V_GPCTSEL0 2 1134 #define PMCMCR1_M_GPCTSEL0 (1 << PMCMCR1_V_GPCTSEL0) 1135 #define PMCMCR1_V_GPCTSEL1 3 1136 #define PMCMCR1_M_GPCTSEL1 (1 << PMCMCR1_V_GPCTSEL1) 1137 #define PMCMCR1_V_GPCTEN 4 1138 #define PMCMCR1_M_GPCTEN (1 << PMCMCR1_V_GPCTEN) 1139 #define PMCMCR1_V_WMSKVLBNAC 5 1140 #define PMCMCR1_M_WMSKVLBNAC (1 << PMCMCR1_V_WMSKVLBNAC) 1141 #define PMCMCR1_V_WAKE0MSK 6 1142 #define PMCMCR1_M_WAKE0MSK (1 << PMCMCR1_V_WAKE0MSK) 1143 #define PMCMCR1_V_WAKE1MSK 7 1144 #define PMCMCR1_M_WAKE1MSK (1 << PMCMCR1_V_WAKE1MSK) 1145 #define PMCMCR1_V_WMSKRING 8 1146 #define PMCMCR1_M_WMSKRING (1 << PMCMCR1_V_WMSKRING) 1147 #define PMCMCR1_V_WMSKRTC 9 1148 #define PMCMCR1_M_WMSKRTC (1 << PMCMCR1_V_WMSKRTC) 1149 #define PMCMCR1_V_WMSKTMR 11 1150 #define PMCMCR1_M_WMSKTMR (1 << PMCMCR1_V_WMSKTMR) 1151 #define PMCMCR1_V_PRDCTID 12 1152 #define PMCMCR1_M_PRDCTID (0xF << PMCMCR1_V_PRDCTID) 1153 1154 /* 1155 ** 1156 ** GP Counter/Timer Register (GPCTR) - Index 0x010 1157 ** 1158 ** Loc Size Name Function 1159 ** ----- ---- ---- --------------------------------- 1160 ** <0> 1 GPCT0 General Purpose Counter/Timer 0 1161 ** <1> 1 GPCT1 General Purpose Counter/Timer 1 1162 ** <2> 1 GPCT2 General Purpose Counter/Timer 2 1163 ** <3> 1 GPCT3 General Purpose Counter/Timer 3 1164 ** <4> 1 GPCT4 General Purpose Counter/Timer 4 1165 ** <5> 1 GPCT5 General Purpose Counter/Timer 5 1166 ** <6> 1 GPCT6 General Purpose Counter/Timer 6 1167 ** <7> 1 GPCT7 General Purpose Counter/Timer 7 1168 ** <8> 1 GPCT8 General Purpose Counter/Timer 8 1169 ** <9> 1 GPCT9 General Purpose Counter/Timer 9 1170 ** <10> 1 GPCT10 General Purpose Counter/Timer 10 1171 ** <11> 1 GPCT11 General Purpose Counter/Timer 11 1172 ** <12> 1 GPCT12 General Purpose Counter/Timer 12 1173 ** <13> 1 GPCT13 General Purpose Counter/Timer 13 1174 ** <14> 1 GPCT14 General Purpose Counter/Timer 14 1175 ** <15> 1 GPCT15 General Purpose Counter/Timer 15 1176 ** 1177 */ 1178 #define PMC_GPCTR_REG 0x010 1179 #define GPCTR_M_GPCTR 0xFFFFFFFF 1180 1181 /* 1182 ** 1183 ** GP Timer Compare Register (GPTMRCMPR) - Index 0x011 1184 ** 1185 ** Loc Size Name Function 1186 ** ----- ---- ---- --------------------------------- 1187 ** <0> 1 GPTMRCMP0 GP Counter/Timer Compare 0 1188 ** <1> 1 GPTMRCMP1 GP Counter/Timer Compare 1 1189 ** <2> 1 GPTMRCMP2 GP Counter/Timer Compare 2 1190 ** <3> 1 GPTMRCMP3 GP Counter/Timer Compare 3 1191 ** <4> 1 GPTMRCMP4 GP Counter/Timer Compare 4 1192 ** <5> 1 GPTMRCMP5 GP Counter/Timer Compare 5 1193 ** <6> 1 GPTMRCMP6 GP Counter/Timer Compare 6 1194 ** <7> 1 GPTMRCMP7 GP Counter/Timer Compare 7 1195 ** <8> 1 GPTMRCMP8 GP Counter/Timer Compare 8 1196 ** <9> 1 GPTMRCMP9 GP Counter/Timer Compare 9 1197 ** <10> 1 GPTMRCMP10 GP Counter/Timer Compare 10 1198 ** <11> 1 GPTMRCMP11 GP Counter/Timer Compare 11 1199 ** <12> 1 GPTMRCMP12 GP Counter/Timer Compare 12 1200 ** <13> 1 GPTMRCMP13 GP Counter/Timer Compare 13 1201 ** <14> 1 GPTMRCMP14 GP Counter/Timer Compare 14 1202 ** <15> 1 GPTMRCMP15 GP Counter/Timer Compare 15 1203 ** 1204 */ 1205 #define PMC_GPTMRCMPR_REG 0x010 1206 #define GPTMRCMPR_M_GPTMRCMPR 0xFFFFFFFF 1207 1208 /* 1209 ** 1210 ** Debounce Control Register (DBCR) - Index 0x012 1211 ** 1212 ** Loc Size Name Function 1213 ** ----- ---- ---- --------------------------------- 1214 ** <0> 1 DBDIS0 Debounce Disable 0 1215 ** <2> 1 DBDIS1 Debounce Disable 1 1216 ** <3> 1 DBTMDR1 Debounce Time Duration 1 1217 ** <4> 1 DBDIS2 Debounce Disable 2 1218 ** <5> 1 DBTMDR2 Debounce Time Duration 2 1219 ** <6> 1 DBDIS3 Debounce Disable 3 1220 ** <7> 1 DBTMDR3 Debounce Time Duration 3 1221 ** <12> 1 WAKE0DBDIS WAKE0 Debounce Disable 1222 ** <13> 1 WAKE0DBTMDR WAKE0 Debounce Time Duration 1223 ** <14> 1 WAKE1DBDIS WAKE1 Debounce Disable 1224 ** <15> 1 WAKE1DBTMDR WAKE1 Debounce Time Duration 1225 ** 1226 ** <1><8:11> Reserved 1227 ** 1228 */ 1229 #define PMC_DBCR_REG 0x012 1230 #define PMC_DBCR_INIT 0x0000 1231 #define DBCR_V_DBDIS0 0 1232 #define DBCR_M_DBDIS0 (1 << DBCR_V_DBDIS0) 1233 #define DBCR_V_DBDIS1 2 1234 #define DBCR_M_DBDIS1 (1 << DBCR_V_DBDIS1) 1235 #define DBCR_V_DBTMDR1 3 1236 #define DBCR_M_DBTMDR1 (1 << DBCR_V_DBTMDR1) 1237 #define DBCR_V_DBDIS2 4 1238 #define DBCR_M_DBDIS2 (1 << DBCR_V_DBDIS2) 1239 #define DBCR_V_DBTMDR2 5 1240 #define DBCR_M_DBTMDR2 (1 << DBCR_V_DBTMDR2) 1241 #define DBCR_V_DBDIS3 6 1242 #define DBCR_M_DBDIS3 (1 << DBCR_V_DBDIS3) 1243 #define DBCR_V_DBTMDR3 7 1244 #define DBCR_M_DBTMDR3 (1 << DBCR_V_DBTMDR3) 1245 #define DBCR_V_WAKE0DBDIS 12 1246 #define DBCR_M_WAKE0DBDIS (1 << DBCR_V_WAKE0DBDIS) 1247 #define DBCR_V_WAKE0DBTMDR 13 1248 #define DBCR_M_WAKE0DBTMDR (1 << DBCR_V_WAKE0DBTMDR) 1249 #define DBCR_V_WAKE1DBDIS 14 1250 #define DBCR_M_WAKE1DBDIS (1 << DBCR_V_WAKE1DBDIS) 1251 #define DBCR_V_WAKE1DBTMDR 15 1252 #define DBCR_M_WAKE1DBTMDR (1 << DBCR_V_WAKE1DBTMDR) 1253 1254 /* 1255 ** 1256 ** PMC Miscellaneous Control 2 Register (PMCMCR2) - Index 0x013 1257 ** 1258 ** Loc Size Name Function 1259 ** ----- ---- ---- --------------------------------- 1260 ** <1> 1 SMIRDYEN SMIRDY# Enable 1261 ** <2> 1 PWRGDSTBYDIS PWRGOOD Standby Disable 1262 ** <3> 1 GLBLRSTEN Global Reset Enable 1263 ** <4> 1 PMCRSTEN PMC Reset Enable 1264 ** <7> 1 SPSRESETDIS Disable SRESET Upon Resume 1265 ** <8> 1 SPRSTDRVDIS Disable RSTDRV Upon Resume 1266 ** <9> 1 WAKE0TOGL WAKE0 Toggle Select 1267 ** <10> 1 WAKE1TOGL WAKE1 Toggle Select 1268 ** <14> 1 SWTCHEN SWTCH Enable 1269 ** <15> 1 RSTCPUFLG RSTCPU Flag 1270 ** 1271 ** <0><5:6><11:13> Reserved 1272 ** 1273 */ 1274 #define PMC_PMCMCR2_REG 0x013 1275 #define PMC_PMCMCR2_INIT ( PMCMCR2_M_PWRGDSTBYDIS | PMCMCR2_M_GLBLRSTEN | \ 1276 PMCMCR2_M_PMCRSTEN | \ 1277 PMCMCR2_M_SPSRESETDIS ) 1278 #define PMCMCR2_V_GPCTSEL0 1 1279 #define PMCMCR2_M_GPCTSEL0 (1 << PMCMCR2_V_SMIRDYEN) 1280 #define PMCMCR2_V_PWRGDSTBYDIS 2 1281 #define PMCMCR2_M_PWRGDSTBYDIS (1 << PMCMCR2_V_PWRGDSTBYDIS) 1282 #define PMCMCR2_V_GLBLRSTEN 3 1283 #define PMCMCR2_M_GLBLRSTEN (1 << PMCMCR2_V_GLBLRSTEN) 1284 #define PMCMCR2_V_PMCRSTEN 4 1285 #define PMCMCR2_M_PMCRSTEN (1 << PMCMCR2_V_PMCRSTEN) 1286 #define PMCMCR2_V_SPSRESETDIS 7 1287 #define PMCMCR2_M_SPSRESETDIS (1 << PMCMCR2_V_SPSRESETDIS) 1288 #define PMCMCR2_V_SPRSTDRVDIS 8 1289 #define PMCMCR2_M_SPRSTDRVDIS (1 << PMCMCR2_V_SPRSTDRVDIS) 1290 #define PMCMCR2_V_WAKE0TOGL 9 1291 #define PMCMCR2_M_WAKE0TOGL (1 << PMCMCR2_V_WAKE0TOGL) 1292 #define PMCMCR2_V_WAKE1TOGL 10 1293 #define PMCMCR2_M_WAKE1TOGL (1 << PMCMCR2_V_WAKE1TOGL) 1294 #define PMCMCR2_V_SWTCHEN 14 1295 #define PMCMCR2_M_SWTCHEN (1 << PMCMCR2_V_SWTCHEN) 1296 #define PMCMCR2_V_RSTCPUFLG 15 1297 #define PMCMCR2_M_RSTCPUFLG (1 << PMCMCR2_V_RSTCPUFLG) 1298 1299 /* 1300 ** 1301 ** Optional GPIO Control Register 2 (GPIOCR2) - Index 0x014 1302 ** 1303 ** Loc Size Name Function 1304 ** ----- ---- ---- --------------------------------- 1305 ** <0> 1 GPIOADATA0 General Purpose I/O A Data 0 1306 ** <1> 1 GPIOADATA1 General Purpose I/O A Data 1 1307 ** <2> 1 GPIOADIR0 General Purpose I/O A Direction 0 1308 ** <3> 1 GPIOADIR1 General Purpose I/O A Direction 1 1309 ** <4> 1 GPIOBDATA0 General Purpose I/O B Data 0 1310 ** <5> 1 GPIOBDATA1 General Purpose I/O B Data 1 1311 ** <6> 1 GPIOBDIR0 General Purpose I/O B Direction 0 1312 ** <7> 1 GPIOBDIR1 General Purpose I/O B Direction 1 1313 ** <8> 1 GPIOCDATA0 General Purpose I/O C Data 0 1314 ** <9> 1 GPIOCDATA1 General Purpose I/O C Data 1 1315 ** <10> 1 GPIOCDIR0 General Purpose I/O C Direction 0 1316 ** <11> 1 GPIOCDIR1 General Purpose I/O C Direction 1 1317 ** 1318 ** <12:15> Reserved 1319 ** 1320 */ 1321 #define PMC_GPIOCR2_REG 0x014 1322 #define PMC_GPIOCR2_INIT ( GPIOCR2_M_GPIOADIR0 | GPIOCR2_M_GPIOADIR1 | \ 1323 GPIOCR2_M_GPIOBDIR1 | GPIOCR2_M_GPIOCDATA0 | \ 1324 GPIOCR2_M_GPIOCDIR0 | GPIOCR2_M_GPIOCDIR1 ) 1325 #define GPIOCR2_V_GPIOADATA 0 1326 #define GPIOCR2_M_GPIOADATA (0x3 << GPIOCR2_V_GPIOADATA) 1327 #define GPIOCR2_V_GPIOADATA0 0 1328 #define GPIOCR2_M_GPIOADATA0 (1 << GPIOCR2_V_GPIOADATA0) 1329 #define GPIOCR2_V_GPIOADATA1 1 1330 #define GPIOCR2_M_GPIOADATA1 (1 << GPIOCR2_V_GPIOADATA1) 1331 #define GPIOCR2_V_GPIOADIR 2 1332 #define GPIOCR2_M_GPIOADIR (0x3 << GPIOCR2_V_GPIOADIR) 1333 #define GPIOCR2_V_GPIOADIR0 2 1334 #define GPIOCR2_M_GPIOADIR0 (1 << GPIOCR2_V_GPIOADIR0) 1335 #define GPIOCR2_V_GPIOADIR1 3 1336 #define GPIOCR2_M_GPIOADIR1 (1 << GPIOCR2_V_GPIOADIR1) 1337 #define GPIOCR2_V_GPIOBDATA 4 1338 #define GPIOCR2_M_GPIOBDATA (0x3 << GPIOCR2_V_GPIOBDATA) 1339 #define GPIOCR2_V_GPIOBDATA0 4 1340 #define GPIOCR2_M_GPIOBDATA0 (1 << GPIOCR2_V_GPIOBDATA0) 1341 #define GPIOCR2_V_GPIOBDATA1 5 1342 #define GPIOCR2_M_GPIOBDATA1 (1 << GPIOCR2_V_GPIOBDATA1) 1343 #define GPIOCR2_V_GPIOBDIR 6 1344 #define GPIOCR2_M_GPIOBDIR (0x3 << GPIOCR2_V_GPIOBDIR) 1345 #define GPIOCR2_V_GPIOBDIR0 6 1346 #define GPIOCR2_M_GPIOBDIR0 (1 << GPIOCR2_V_GPIOBDIR0) 1347 #define GPIOCR2_V_GPIOBDIR1 7 1348 #define GPIOCR2_M_GPIOBDIR1 (1 << GPIOCR2_V_GPIOBDIR1) 1349 #define GPIOCR2_V_GPIOCDATA 8 1350 #define GPIOCR2_M_GPIOCDATA (0x3 << GPIOCR2_V_GPIOCDATA) 1351 #define GPIOCR2_V_GPIOCDATA0 8 1352 #define GPIOCR2_M_GPIOCDATA0 (1 << GPIOCR2_V_GPIOCDATA0) 1353 #define GPIOCR2_V_GPIOCDATA1 9 1354 #define GPIOCR2_M_GPIOCDATA1 (1 << GPIOCR2_V_GPIOCDATA1) 1355 #define GPIOCR2_V_GPIOCDIR 10 1356 #define GPIOCR2_M_GPIOCDIR (0x3 << GPIOCR2_V_GPIOCDIR) 1357 #define GPIOCR2_V_GPIOCDIR0 10 1358 #define GPIOCR2_M_GPIOCDIR0 (1 << GPIOCR2_V_GPIOCDIR0) 1359 #define GPIOCR2_V_GPIOCDIR1 11 1360 #define GPIOCR2_M_GPIOCDIR1 (1 << GPIOCR2_V_GPIOCDIR1) 1361 1362 /* 1363 ** 1364 ** Leakage Control Register (LKCR) - Index 0x015 1365 ** 1366 ** Loc Size Name Function 1367 ** ----- ---- ---- --------------------------------- 1368 ** <0> 1 CPULCDIS CPU Interface Leakage Control Disable 1369 ** <1> 1 DRAMLCDIS DRAM Interface Leakage Control Disable 1370 ** <2> 1 L2CACHELCDIS L2 Cache Leakage Control Disable 1371 ** <3> 1 ATLCDIS AT Bus Interface Leakage Control Disable 1372 ** <4> 1 BBUSLCDIS Burst Bus Interface Leakage Control Disable 1373 ** <5> 1 GPIOLCDIS GPIO Interface Leakage Control Disable 1374 ** <6> 1 PC49LCDIS PC4 to PC9 Leakage Control Disable 1375 ** <7> 1 LEDLCDIS LED Interface Leakage Control Disable 1376 ** <8> 1 BMLCDIS Battery Management Leakage Control Disable 1377 ** <9> 1 PC03LCDIS PC0 to PC3 Leakage Control Disable 1378 ** <14> 1 PWRGDLCDIS Enable Leakage Control 1379 ** <15> 1 LCDIS Global Leakage Control 1380 ** 1381 ** <10:13> Reserved 1382 ** 1383 */ 1384 #define PMC_LKCR_REG 0x015 1385 #define PMC_LKCR_INIT ( LKCR_M_CPULCDIS | LKCR_M_DRAMLCDIS | \ 1386 LKCR_M_L2CACHELCDIS | LKCR_M_ATLCDIS | \ 1387 LKCR_M_BBUSLCDIS | LKCR_M_GPIOLCDIS | \ 1388 LKCR_M_PC49LCDIS | LKCR_M_LEDLCDIS | \ 1389 LKCR_M_BMLCDIS | LKCR_M_PC03LCDIS | \ 1390 LKCR_M_PWRGDLCDIS | LKCR_M_LCDIS ) 1391 #define LKCR_V_CPULCDIS 0 1392 #define LKCR_M_CPULCDIS (1 << LKCR_V_CPULCDIS) 1393 #define LKCR_V_DRAMLCDIS 1 1394 #define LKCR_M_DRAMLCDIS (1 << LKCR_V_DRAMLCDIS) 1395 #define LKCR_V_L2CACHELCDIS 2 1396 #define LKCR_M_L2CACHELCDIS (1 << LKCR_V_L2CACHELCDIS) 1397 #define LKCR_V_ATLCDIS 3 1398 #define LKCR_M_ATLCDIS (1 << LKCR_V_ATLCDIS) 1399 #define LKCR_V_BBUSLCDIS 4 1400 #define LKCR_M_BBUSLCDIS (1 << LKCR_V_BBUSLCDIS) 1401 #define LKCR_V_GPIOLCDIS 5 1402 #define LKCR_M_GPIOLCDIS (1 << LKCR_V_GPIOLCDIS) 1403 #define LKCR_V_PC49LCDIS 6 1404 #define LKCR_M_PC49LCDIS (1 << LKCR_V_PC49LCDIS) 1405 #define LKCR_V_LEDLCDIS 7 1406 #define LKCR_M_LEDLCDIS (1 << LKCR_V_LEDLCDIS) 1407 #define LKCR_V_BMLCDIS 8 1408 #define LKCR_M_BMLCDIS (1 << LKCR_V_BMLCDIS) 1409 #define LKCR_V_PC03LCDIS 9 1410 #define LKCR_M_PC03LCDIS (1 << LKCR_V_PC03LCDIS) 1411 #define LKCR_V_PWRGDLCDIS 14 1412 #define LKCR_M_PWRGDLCDIS (1 << LKCR_V_PWRGDLCDIS) 1413 #define LKCR_V_LCDIS 15 1414 #define LKCR_M_LCDIS (1 << LKCR_V_LCDIS) 1415 1416 /* 1417 ** 1418 ** SEQUOIA-1 Miscellaneous Register 1 (SEQMR1) - Index 0x016 1419 ** 1420 ** Loc Size Name Function 1421 ** ----- ---- ---- --------------------------------- 1422 ** <11> 1 DISCREADS Driving EADS# on Non-Cacheable Region 1423 ** <12> 1 FRCBLASTDIS Forcing BLAST low During Reset 1424 ** <14> 1 P92B3EN Enable Control Bit for Port 92 Bit 3 Function 1425 ** <15> 1 SWTSTBYDIS Disable Standby on SWTCH 1426 ** 1427 ** <0:10><13> Reserved 1428 ** 1429 */ 1430 #define PMC_SEQMR1_REG 0x016 1431 #define PMC_SEQMR1_INIT 0x0000 1432 #define SEQMR1_V_DISCREADS 11 1433 #define SEQMR1_M_DISCREADS (1 << SEQMR1_V_DISCREADS) 1434 #define SEQMR1_V_FRCBLASTDIS 12 1435 #define SEQMR1_M_FRCBLASTDIS (1 << SEQMR1_V_FRCBLASTDIS) 1436 #define SEQMR1_V_P92B3EN 14 1437 #define SEQMR1_M_P92B3EN (1 << SEQMR1_V_P92B3EN) 1438 #define SEQMR1_V_SWTSTBYDIS 15 1439 #define SEQMR1_M_SWTSTBYDIS (1 << SEQMR1_V_SWTSTBYDIS) 1440 1441 /* 1442 ** 1443 ** SEQUOIA-1 Miscellaneous Register 2 (SEQMR2) - Index 0x017 1444 ** 1445 ** Loc Size Name Function 1446 ** ----- ---- ---- --------------------------------- 1447 ** <0> 1 DLYWCASEN Delay Write CAS Enable 1448 ** <1> 1 SMMWTEN SMM Write-Through Enable 1449 ** <2> 1 STATICSPNDEN Static Suspend Enable 1450 ** 1451 ** <3:15> Reserved 1452 ** 1453 */ 1454 #define PMC_SEQMR2_REG 0x017 1455 #define PMC_SEQMR2_INIT 0x0000 1456 #define SEQMR2_V_DLYWCASEN 0 1457 #define SEQMR2_M_DLYWCASEN (1 << SEQMR2_V_DLYWCASEN) 1458 #define SEQMR2_V_SMMWTEN 1 1459 #define SEQMR2_M_SMMWTEN (1 << SEQMR2_V_SMMWTEN) 1460 #define SEQMR2_V_STATICSPNDEN 2 1461 #define SEQMR2_M_STATICSPNDEN (1 << SEQMR2_V_STATICSPNDEN) 1462 1463 /* 1464 ** 1465 ** Secondary Activity Mask Register (SAMR) - Index 0x019 1466 ** 1467 ** Loc Size Name Function 1468 ** ----- ---- ---- --------------------------------- 1469 ** <0> 1 SAMSKVID Secondary Activity Mask Video Accesses 1470 ** <3> 1 SAMSKKBD Secondary Activity Mask Keyboard Accesses 1471 ** <6> 1 SAMSKPROG0 Secondary Activity Mask PR 0 1472 ** <7> 1 SAMSKPROG1 Secondary Activity Mask PR 1 1473 ** <8> 1 SAMSKPROG2 Secondary Activity Mask PR 2 1474 ** <9> 1 SAMSKPROG3 Secondary Activity Mask PR 3 1475 ** <12> 1 SAMSKEACT0 Secondary Activity Mask EXTACT0 1476 ** <13> 1 SAMSKEACT1 Secondary Activity Mask EXTACT1 1477 ** <14> 1 SAMSKEACT2 Secondary Activity Mask EXTACT2 1478 ** <15> 1 SAMSKEACT3 Secondary Activity Mask EXTACT3 1479 ** 1480 ** <1:2><4:5><10:11> Reserved 1481 ** 1482 */ 1483 #define PMC_SAMR_REG 0x019 1484 #define PMC_SAMR_INIT ( SAMR_M_SAMSKVID | SAMR_M_SAMSKKBD | \ 1485 SAMR_M_SAMSKPROG0 | SAMR_M_SAMSKPROG1 | \ 1486 SAMR_M_SAMSKPROG2 | SAMR_M_SAMSKPROG3 | \ 1487 SAMR_M_SAMSKEACT0 | SAMR_M_SAMSKEACT1 | \ 1488 SAMR_M_SAMSKEACT2 | SAMR_M_SAMSKEACT3 ) 1489 #define SAMR_V_SAMSKVID 0 1490 #define SAMR_M_SAMSKVID (1 << SAMR_V_SAMSKVID) 1491 #define SAMR_V_SAMSKKBD 3 1492 #define SAMR_M_SAMSKKBD (1 << SAMR_V_SAMSKKBD) 1493 #define SAMR_V_SAMSKPROG0 6 1494 #define SAMR_M_SAMSKPROG0 (1 << SAMR_V_SAMSKPROG0) 1495 #define SAMR_V_SAMSKPROG1 7 1496 #define SAMR_M_SAMSKPROG1 (1 << SAMR_V_SAMSKPROG1) 1497 #define SAMR_V_SAMSKPROG2 8 1498 #define SAMR_M_SAMSKPROG2 (1 << SAMR_V_SAMSKPROG2) 1499 #define SAMR_V_SAMSKPROG3 9 1500 #define SAMR_M_SAMSKPROG3 (1 << SAMR_V_SAMSKPROG3) 1501 #define SAMR_V_SAMSKEACT0 12 1502 #define SAMR_M_SAMSKEACT0 (1 << SAMR_V_SAMSKEACT0) 1503 #define SAMR_V_SAMSKEACT1 13 1504 #define SAMR_M_SAMSKEACT1 (1 << SAMR_V_SAMSKEACT1) 1505 #define SAMR_V_SAMSKEACT2 14 1506 #define SAMR_M_SAMSKEACT2 (1 << SAMR_V_SAMSKEACT2) 1507 #define SAMR_V_SAMSKEACT3 15 1508 #define SAMR_M_SAMSKEACT3 (1 << SAMR_V_SAMSKEACT3) 1509 1510 /* 1511 ** 1512 ** Additional Activity Source Register (AASR) - Index 0x01A 1513 ** 1514 ** Loc Size Name Function 1515 ** ----- ---- ---- --------------------------------- 1516 ** <0> 1 WAKE0ACTV WAKE0 Active 1517 ** <1> 1 WAKE1ACTV WAKE1 Active 1518 ** <2> 1 INTRACTV Interrupt Active 1519 ** <4> 1 DZTO Doze Time-out Status 1520 ** <5> 1 SLPTO Sleep Time-out Status 1521 ** <6> 1 SPNDTO Suspend Time-out Status 1522 ** <7> 1 GENTO Generic Timer Time-out Status 1523 ** <8> 1 PRTMR0TO Programmable Timer 0 Time-out Status 1524 ** <9> 1 PRTMR1TO Programmable Timer 1 Time-out Status 1525 ** <10> 1 PRTMR2TO Programmable Timer 2 Time-out Status 1526 ** <11> 1 PRTMR3TO Programmable Timer 3 Time-out Status 1527 ** <12> 1 PRTOPMI0 Programmable Timer 0 PMI Flag 1528 ** <13> 1 PRTOPMI1 Programmable Timer 1 PMI Flag 1529 ** <14> 1 PRTOPMI2 Programmable Timer 2 PMI Flag 1530 ** <15> 1 PRTOPMI3 Programmable Timer 3 PMI Flag 1531 ** 1532 ** <3> Reserved 1533 ** 1534 */ 1535 #define PMC_AASR_REG 0x01A 1536 #define PMC_AASR_INIT 0x0000 1537 #define AASR_V_WAKE0ACTV 0 1538 #define AASR_M_WAKE0ACTV (1 << AASR_V_WAKE0ACTV) 1539 #define AASR_V_WAKE1ACTV 1 1540 #define AASR_M_WAKE1ACTV (1 << AASR_V_WAKE1ACTV) 1541 #define AASR_V_INTRACTV 2 1542 #define AASR_M_INTRACTV (1 << AASR_V_INTRACTV) 1543 #define AASR_V_DZTO 4 1544 #define AASR_M_DZTO (1 << AASR_V_DZTO) 1545 #define AASR_V_SLPTO 5 1546 #define AASR_M_SLPTO (1 << AASR_V_SLPTO) 1547 #define AASR_V_SPNDTO 6 1548 #define AASR_M_SPNDTO (1 << AASR_V_SPNDTO) 1549 #define AASR_V_GENTO 7 1550 #define AASR_M_GENTO (1 << AASR_V_GENTO) 1551 #define AASR_V_PRTMR0TO 8 1552 #define AASR_M_PRTMR0TO (1 << AASR_V_PRTMR0TO) 1553 #define AASR_V_PRTMR1TO 9 1554 #define AASR_M_PRTMR1TO (1 << AASR_V_PRTMR0T1) 1555 #define AASR_V_PRTMR2TO 10 1556 #define AASR_M_PRTMR2TO (1 << AASR_V_PRTMR0T2) 1557 #define AASR_V_PRTMR3TO 11 1558 #define AASR_M_PRTMR3TO (1 << AASR_V_PRTMR0T3) 1559 #define AASR_V_PRTOPMI0 12 1560 #define AASR_M_PRTOPMI0 (1 << AASR_V_PRTOPMI0) 1561 #define AASR_V_PRTOPMI1 13 1562 #define AASR_M_PRTOPMI1 (1 << AASR_V_PRTOPMI1) 1563 #define AASR_V_PRTOPMI2 14 1564 #define AASR_M_PRTOPMI2 (1 << AASR_V_PRTOPMI2) 1565 #define AASR_V_PRTOPMI3 15 1566 #define AASR_M_PRTOPMI3 (1 << AASR_V_PRTOPMI3) 1567 1568 /* 1569 ** 1570 ** Additional Primary Activity Mask Register (APAMR) - Index 0x01B 1571 ** 1572 ** Loc Size Name Function 1573 ** ----- ---- ---- --------------------------------- 1574 ** <0> 1 PAMSKWAKE0 Primary Activity Mask WAKE0 1575 ** <1> 1 PAMSKWAKE1 Primary Activity Mask WAKE1 1576 ** <2> 1 PAMSKINTR Primary Activity Mask INTR 1577 ** <3> 1 PAMSKPMI Primary Activity Mask PMI 1578 ** <4> 1 PAMSKHOLD Primary Activity Mask HOLD Request 1579 ** <5> 1 PAMSKNMI Primary Activity Mask NMI 1580 ** <6> 1 PAMSKDMA Primary Activity Mask DMA 1581 ** <7> 1 PAMSKMSTR Primary Activity Mask MASTER 1582 ** <11> 1 DISPACTVON Disable Primary Activity On 1583 ** <14> 1 HD2EN Hard Disk Secondar Enable 1584 ** <15> 1 LMTPACTV Limited Primary Activity PMI 1585 ** 1586 ** <8:10><12:13> Reserved 1587 ** 1588 */ 1589 #define PMC_APAMR_REG 0x01B 1590 #define PMC_APAMR_INIT ( APAMR_M_PAMSKWAKE0 | APAMR_M_PAMSKWAKE1 | \ 1591 APAMR_M_PAMSKINTR | APAMR_M_PAMSKPMI | \ 1592 APAMR_M_PAMSKHOLD | APAMR_M_PAMSKNMI | \ 1593 APAMR_M_PAMSKDMA | APAMR_M_PAMSKMSTR | \ 1594 APAMR_M_LMTPACTV ) 1595 #define APAMR_V_PAMSKWAKE0 0 1596 #define APAMR_M_PAMSKWAKE0 (1 << APAMR_V_PAMSKWAKE0) 1597 #define APAMR_V_PAMSKWAKE1 1 1598 #define APAMR_M_PAMSKWAKE1 (1 << APAMR_V_PAMSKWAKE1) 1599 #define APAMR_V_PAMSKINTR 2 1600 #define APAMR_M_PAMSKINTR (1 << APAMR_V_PAMSKINTR) 1601 #define APAMR_V_PAMSKPMI 3 1602 #define APAMR_M_PAMSKPMI (1 << APAMR_V_PAMSKPMI) 1603 #define APAMR_V_PAMSKHOLD 4 1604 #define APAMR_M_PAMSKHOLD (1 << APAMR_V_PAMSKHOLD) 1605 #define APAMR_V_PAMSKNMI 5 1606 #define APAMR_M_PAMSKNMI (1 << APAMR_V_PAMSKNMI) 1607 #define APAMR_V_PAMSKDMA 6 1608 #define APAMR_M_PAMSKDMA (1 << APAMR_V_PAMSKDMA) 1609 #define APAMR_V_PAMSKMSTR 7 1610 #define APAMR_M_PAMSKMSTR (1 << APAMR_V_PAMSKMSTR) 1611 #define APAMR_V_DISPACTVON 11 1612 #define APAMR_M_DISPACTVON (1 << APAMR_V_DISPACTVON) 1613 #define APAMR_V_HD2EN 14 1614 #define APAMR_M_HD2EN (1 << APAMR_V_HD2EN) 1615 #define APAMR_V_LMTPACTV 15 1616 #define APAMR_M_LMTPACTV (1 << APAMR_V_LMTPACTV) 1617 1618 /* 1619 ** 1620 ** Additional Secondary Control Register (ASCR) - Index 0x01C 1621 ** 1622 ** Loc Size Name Function 1623 ** ----- ---- ---- --------------------------------- 1624 ** <0> 1 SAMSKWAKE0 Secondary Activity Mask WAKE0 1625 ** <1> 1 SAMSKWAKE1 Secondary Activity Mask WAKE1 1626 ** <2> 1 SAMSKINTR Secondary Activity Mask INTR 1627 ** <3> 1 SAMSKPMI Secondary Activity Mask PMI 1628 ** <4> 1 SAMSKIRQ0 Secondary Activity Mask IRQ0 1629 ** <6> 1 SAMSKDMA Secondary Activity Mask DMA 1630 ** <7> 1 SAMSKMSTR Secondary Activity Mask MASTER 1631 ** <9> 1 SACTVTMR0 Secondary Activity Timer 0 1632 ** <10> 1 SACTVTMR1 Secondary Activity Timer 1 1633 ** <11> 1 SACTVTMR2 Secondary Activity Timer 2 1634 ** <15> 1 LMTSACTV Limited Secondary Activity PMI 1635 ** 1636 ** <5><8><12:14> Reserved 1637 ** 1638 */ 1639 #define PMC_ASCR_REG 0x01C 1640 #define PMC_ASCR_INIT ( ASCR_M_SAMSKWAKE0 | ASCR_M_SAMSKWAKE1 | \ 1641 ASCR_M_SAMSKINTR | ASCR_M_SAMSKPMI | \ 1642 ASCR_M_SAMSKIRQ0 | ASCR_M_SAMSKDMA | \ 1643 ASCR_M_SAMSKMSTR | ASCR_M_SACTVTMR2 | \ 1644 ASCR_M_LMTSACTV ) 1645 #define ASCR_V_SAMSKWAKE0 0 1646 #define ASCR_M_SAMSKWAKE0 (1 << ASCR_V_SAMSKWAKE0) 1647 #define ASCR_V_SAMSKWAKE1 1 1648 #define ASCR_M_SAMSKWAKE1 (1 << ASCR_V_SAMSKWAKE1) 1649 #define ASCR_V_SAMSKINTR 2 1650 #define ASCR_M_SAMSKINTR (1 << ASCR_V_SAMSKINTR) 1651 #define ASCR_V_SAMSKPMI 3 1652 #define ASCR_M_SAMSKPMI (1 << ASCR_V_SAMSKPMI) 1653 #define ASCR_V_SAMSKIRQ0 4 1654 #define ASCR_M_SAMSKIRQ0 (1 << ASCR_V_SAMSKIRQ0) 1655 #define ASCR_V_SAMSKDMA 6 1656 #define ASCR_M_SAMSKDMA (1 << ASCR_V_SAMSKDMA) 1657 #define ASCR_V_SAMSKMSTR 7 1658 #define ASCR_M_SAMSKMSTR (1 << ASCR_V_SAMSKMSTR) 1659 #define ASCR_V_SACTVTMR 9 1660 #define ASCR_M_SACTVTMR (0x7 << ASCR_V_SACTVTMR) 1661 #define ASCR_V_SACTVTMR0 9 1662 #define ASCR_M_SACTVTMR0 (1 << ASCR_V_SACTVTMR0) 1663 #define ASCR_V_SACTVTMR1 10 1664 #define ASCR_M_SACTVTMR1 (1 << ASCR_V_SACTVTMR1) 1665 #define ASCR_V_SACTVTMR2 11 1666 #define ASCR_M_SACTVTMR2 (1 << ASCR_V_SACTVTMR2) 1667 #define ASCR_V_LMTSACTV 15 1668 #define ASCR_M_LMTSACTV (1 << ASCR_V_LMTSACTV) 1669 1670 /* 1671 ** Secondary Activity Timer 1672 */ 1673 #define SACTVTMR_125US 0x000 1674 #define SACTVTMR_1MS ASCR_M_SACTVTMR0 1675 #define SACTVTMR_2MS ASCR_M_SACTVTMR1 1676 #define SACTVTMR_4MS (ASCR_M_SACTVTMR0 | ASCR_M_SACTVTMR1) 1677 #define SACTVTMR_8MS ASCR_M_SACTVTMR2 1678 #define SACTVTMR_16MS (ASCR_M_SACTVTMR0 | ASCR_M_SACTVTMR2) 1679 #define SACTVTMR_32MS (ASCR_M_SACTVTMR1 | ASCR_M_SACTVTMR2) 1680 #define SACTVTMR_64MS (ASCR_M_SACTVTMR0 | ASCR_M_SACTVTMR1 | ASCR_M_SACTVTMR2) 1681 1682 /* 1683 ** 1684 ** Additional PMI Mask Register (APMIMR) - Index 0x01D 1685 ** 1686 ** Loc Size Name Function 1687 ** ----- ---- ---- --------------------------------- 1688 ** <0> 1 IMSKWAKE0 Mask WAKE0 from PMI 1689 ** <1> 1 IMSKWAKE1 Mask WAKE1 from PMI 1690 ** <3> 1 IMSKRTC Mask RTC from PMI 1691 ** <4> 1 RESCHED0 Reschedule PMI 0 1692 ** <5> 1 RESCHED1 Reschedule PMI 1 1693 ** <6> 1 SFTSMI Soft SMI 1694 ** <8> 1 IMSKPRTMR0TO Mask Programmable Time 0 Time-out from PMI 1695 ** <9> 1 IMSKPRTMR1TO Mask Programmable Time 1 Time-out from PMI 1696 ** <10> 1 IMSKPRTMR2TO Mask Programmable Time 2 Time-out from PMI 1697 ** <11> 1 IMSKPRTMR3TO Mask Programmable Time 3 Time-out from PMI 1698 ** 1699 ** <2><7><12:15> Reserved 1700 ** 1701 */ 1702 #define PMC_APMIMR_REG 0x01D 1703 #define PMC_APMIMR_INIT ( APMIMR_M_IMSKWAKE0 | APMIMR_M_IMSKWAKE1 | \ 1704 APMIMR_M_IMSKRTC | APMIMR_M_IMSKPRTMR0TO| \ 1705 APMIMR_M_IMSKPRTMR1TO | \ 1706 APMIMR_M_IMSKPRTMR2TO | \ 1707 APMIMR_M_IMSKPRTMR3TO ) 1708 #define APMIMR_V_IMSKWAKE0 0 1709 #define APMIMR_M_IMSKWAKE0 (1 << APMIMR_V_IMSKWAKE0) 1710 #define APMIMR_V_IMSKWAKE1 1 1711 #define APMIMR_M_IMSKWAKE1 (1 << APMIMR_V_IMSKWAKE1) 1712 #define APMIMR_V_IMSKRTC 3 1713 #define APMIMR_M_IMSKRTC (1 << APMIMR_V_IMSKRTC) 1714 #define APMIMR_V_RESCHED 4 1715 #define APMIMR_M_RESCHED (0x3 << APMIMR_V_RESCHED) 1716 #define APMIMR_V_RESCHED0 4 1717 #define APMIMR_M_RESCHED0 (1 << APMIMR_V_RESCHED0) 1718 #define APMIMR_V_RESCHED1 5 1719 #define APMIMR_M_RESCHED1 (1 << APMIMR_V_RESCHED1) 1720 #define APMIMR_V_SFTSMI 6 1721 #define APMIMR_M_SFTSMI (1 << APMIMR_V_SFTSMI) 1722 #define APMIMR_V_IMSKPRTMR0TO 8 1723 #define APMIMR_M_IMSKPRTMR0TO (1 << APMIMR_V_IMSKPRTMR0TO) 1724 #define APMIMR_V_IMSKPRTMR1TO 9 1725 #define APMIMR_M_IMSKPRTMR1TO (1 << APMIMR_V_IMSKPRTMR1TO) 1726 #define APMIMR_V_IMSKPRTMR2TO 10 1727 #define APMIMR_M_IMSKPRTMR2TO (1 << APMIMR_V_IMSKPRTMR2TO) 1728 #define APMIMR_V_IMSKPRTMR3TO 11 1729 #define APMIMR_M_IMSKPRTMR3TO (1 << APMIMR_V_IMSKPRTMR3TO) 1730 1731 /* 1732 ** Reschedule PMI 1733 */ 1734 #define RESCHED_DISABLE 0x000 1735 #define RESCHED_64MS APMIMR_M_RESCHED0 1736 #define RESCHED_1MS APMIMR_M_RESCHED1 1737 #define RESCHED_1S (APMIMR_M_RESCHED0 | APMIMR_M_RESCHED1) 1738 1739 /* 1740 ** 1741 ** Miscellaneous Control Register (MCR) - Index 0x01E 1742 ** 1743 ** Loc Size Name Function 1744 ** ----- ---- ---- --------------------------------- 1745 ** <0> 1 PMIFLGEN PMI Flag Enable 1746 ** <1> 1 PAFLGEN Primary Activity Flag Enable 1747 ** <2> 1 SAFLGEN Secondary Activity Flag Enable 1748 ** 1749 ** <3:15> Reserved 1750 ** 1751 */ 1752 #define PMC_MCR_REG 0x01E 1753 #define PMC_MCR_INIT 0x0000 1754 #define MCR_V_PMIFLGEN 0 1755 #define MCR_M_PMIFLGEN (1 << MCR_V_PMIFLGEN) 1756 #define MCR_V_PAFLGEN 1 1757 #define MCR_M_PAFLGEN (1 << MCR_V_PAFLGEN) 1758 #define MCR_V_SAFLGEN 2 1759 #define MCR_M_SAFLGEN (1 << MCR_V_SAFLGEN) 1760 1761 /* 1762 ** 1763 ** SEQUOIA-1 Identification Register (SEQIDR) - Index 0x01F 1764 ** 1765 ** Loc Size Name Function 1766 ** ----- ---- ---- --------------------------------- 1767 ** <0> 1 SQ1ID0 SEQUOIA-1 Revision Number ID 0 1768 ** <1> 1 SQ1ID1 SEQUOIA-1 Revision Number ID 1 1769 ** <2> 1 SQ1ID2 SEQUOIA-1 Revision Number ID 2 1770 ** <3> 1 SQ1ID3 SEQUOIA-1 Revision Number ID 3 1771 ** 1772 ** <4:15> Reserved 1773 ** 1774 */ 1775 #define PMC_SEQIDR_REG 0x01F 1776 #define SEQIDR_V_SQ1ID 0 1777 #define SEQIDR_M_SQ1ID (0xF << SEQIDR_V_SQ1ID) 1778 1779 /* 1780 ** 1781 ** Programmable Range Address Register 0 (PRAR0) - Index 0x020 1782 ** 1783 ** Loc Size Name Function 1784 ** ----- ---- ---- --------------------------------- 1785 ** <0> 9 PRMA PRM 0 Address 1786 ** <14> 1 PROSHDW0EN Programmable Shadow Register 0 Enable 1787 ** <15> 1 PROCS0EN Programmable Chip Select 0 Enable 1788 ** 1789 ** <10:13> Reserved 1790 ** 1791 */ 1792 #define PMC_PRAR0_REG 0x020 1793 #define PMC_PRAR0_INIT 0x0000 1794 #define PRAR0_V_PRMA 0 1795 #define PRAR0_M_PRMA (0x3FF << PRAR0_V_PRMA) 1796 #define PRAR0_V_PROSHDW0EN 14 1797 #define PRAR0_M_PROSHDW0EN (1 << PRAR0_V_PROSHDW0EN) 1798 #define PRAR0_V_PROCS0EN 15 1799 #define PRAR0_M_PROCS0EN (1 << PRAR0_V_PROCS0EN) 1800 1801 /* 1802 ** 1803 ** Programmable Range Compare Register 0 (PRCR0) - Index 0x021 1804 ** 1805 ** Loc Size Name Function 1806 ** ----- ---- ---- --------------------------------- 1807 ** <0> 1 PRMCMPEN00 PRM 0 Compare Enable 0 1808 ** <1> 1 PRMCMPEN01 PRM 0 Compare Enable 1 1809 ** <2> 1 PRMCMPEN02 PRM 0 Compare Enable 2 1810 ** <3> 1 PRMCMPEN03 PRM 0 Compare Enable 3 1811 ** <4> 1 PRMCMPEN04 PRM 0 Compare Enable 4 1812 ** <5> 1 PRMCMPEN05 PRM 0 Compare Enable 5 1813 ** <6> 1 PRMCMPEN06 PRM 0 Compare Enable 6 1814 ** <7> 1 PRMCMPEN07 PRM 0 Compare Enable 7 1815 ** <8> 1 PRMCMPEN08 PRM 0 Compare Enable 8 1816 ** <9> 1 PRMCMPEN09 PRM 0 Compare Enable 9 1817 ** <10> 1 PRMWR0EN PRM 0 Compare Write Enable 1818 ** <11> 1 PRMRD0EN PRM 0 Compare Read Enable 1819 ** <12> 1 PRM0MIO PRM 0 Memory or I/O Compare Enable 1820 ** <13> 1 PRM0EN PRM 0 Enable 1821 ** 1822 ** <14:15> Reserved 1823 ** 1824 */ 1825 #define PMC_PRCR0_REG 0x021 1826 #define PMC_PRCR0_INIT 0x0000 1827 #define PRCR0_V_PRMCMPEN 0 1828 #define PRCR0_M_PRMCMPEN (0x3FF << PRCR0_V_PRMCMPEN) 1829 #define PRCR0_V_PRMCMPEN00 0 1830 #define PRCR0_M_PRMCMPEN00 (1 << PRCR0_V_PRMCMPEN00) 1831 #define PRCR0_V_PRMCMPEN01 1 1832 #define PRCR0_M_PRMCMPEN01 (1 << PRCR0_V_PRMCMPEN01) 1833 #define PRCR0_V_PRMCMPEN02 2 1834 #define PRCR0_M_PRMCMPEN02 (1 << PRCR0_V_PRMCMPEN02) 1835 #define PRCR0_V_PRMCMPEN03 3 1836 #define PRCR0_M_PRMCMPEN03 (1 << PRCR0_V_PRMCMPEN03) 1837 #define PRCR0_V_PRMCMPEN04 4 1838 #define PRCR0_M_PRMCMPEN04 (1 << PRCR0_V_PRMCMPEN04) 1839 #define PRCR0_V_PRMCMPEN05 5 1840 #define PRCR0_M_PRMCMPEN05 (1 << PRCR0_V_PRMCMPEN05) 1841 #define PRCR0_V_PRMCMPEN06 6 1842 #define PRCR0_M_PRMCMPEN06 (1 << PRCR0_V_PRMCMPEN06) 1843 #define PRCR0_V_PRMCMPEN07 7 1844 #define PRCR0_M_PRMCMPEN07 (1 << PRCR0_V_PRMCMPEN07) 1845 #define PRCR0_V_PRMCMPEN08 8 1846 #define PRCR0_M_PRMCMPEN08 (1 << PRCR0_V_PRMCMPEN08) 1847 #define PRCR0_V_PRMCMPEN09 9 1848 #define PRCR0_M_PRMCMPEN09 (1 << PRCR0_V_PRMCMPEN09) 1849 #define PRCR0_V_PRMWR0EN 10 1850 #define PRCR0_M_PRMWR0EN (1 << PRCR0_V_PRMWR0EN) 1851 #define PRCR0_V_PRMRD0EN 11 1852 #define PRCR0_M_PRMRD0EN (1 << PRCR0_V_PRMRD0EN) 1853 #define PRCR0_V_PRM0MIO 12 1854 #define PRCR0_M_PRM0MIO (1 << PRCR0_V_PRM0MIO) 1855 #define PRCR0_V_PRM0EN 13 1856 #define PRCR0_M_PRM0EN (1 << PRCR0_V_PRM0EN) 1857 1858 /* 1859 ** 1860 ** Programmable Range Address Register 1 (PRAR1) - Index 0x022 1861 ** 1862 ** Loc Size Name Function 1863 ** ----- ---- ---- --------------------------------- 1864 ** <0> 9 PRMA PRM 1 Address 1865 ** <14> 1 PROSHDW1EN Programmable Shadow Register 1 Enable 1866 ** <15> 1 PROCS1EN Programmable Chip Select 1 Enable 1867 ** 1868 ** <10:13> Reserved 1869 ** 1870 */ 1871 #define PMC_PRAR1_REG 0x022 1872 #define PRAR1_V_PRMA 0 1873 #define PRAR1_M_PRMA (0x3FF << PRAR1_V_PRMA) 1874 #define PRAR1_V_PROSHDW1EN 14 1875 #define PRAR1_M_PROSHDW1EN (1 << PRAR1_V_PROSHDW1EN) 1876 #define PRAR1_V_PROCS1EN 15 1877 #define PRAR1_M_PROCS1EN (1 << PRAR1_V_PROCS1EN) 1878 1879 /* 1880 ** 1881 ** Programmable Range Compare Register 1 (PRCR1) - Index 0x023 1882 ** 1883 ** Loc Size Name Function 1884 ** ----- ---- ---- --------------------------------- 1885 ** <0> 1 PRMCMPEN10 PRM 1 Compare Enable 0 1886 ** <1> 1 PRMCMPEN11 PRM 1 Compare Enable 1 1887 ** <2> 1 PRMCMPEN12 PRM 1 Compare Enable 2 1888 ** <3> 1 PRMCMPEN13 PRM 1 Compare Enable 3 1889 ** <4> 1 PRMCMPEN14 PRM 1 Compare Enable 4 1890 ** <5> 1 PRMCMPEN15 PRM 1 Compare Enable 5 1891 ** <6> 1 PRMCMPEN16 PRM 1 Compare Enable 6 1892 ** <7> 1 PRMCMPEN17 PRM 1 Compare Enable 7 1893 ** <8> 1 PRMCMPEN18 PRM 1 Compare Enable 8 1894 ** <9> 1 PRMCMPEN19 PRM 1 Compare Enable 9 1895 ** <10> 1 PRMWR1EN PRM 1 Compare Write Enable 1896 ** <11> 1 PRMRD1EN PRM 1 Compare Read Enable 1897 ** <12> 1 PRM1MIO PRM 1 Memory or I/O Compare Enable 1898 ** <13> 1 PRM1EN PRM 1 Enable 1899 ** 1900 ** <14:15> Reserved 1901 ** 1902 */ 1903 #define PMC_PRCR1_REG 0x023 1904 #define PMC_PRCR1_INIT 0x0000 1905 #define PRCR1_V_PRMCMPEN 0 1906 #define PRCR1_M_PRMCMPEN (0x3FF << PRCR1_V_PRMCMPEN) 1907 #define PRCR1_V_PRMCMPEN10 0 1908 #define PRCR1_M_PRMCMPEN10 (1 << PRCR1_V_PRMCMPEN10) 1909 #define PRCR1_V_PRMCMPEN11 1 1910 #define PRCR1_M_PRMCMPEN11 (1 << PRCR1_V_PRMCMPEN11) 1911 #define PRCR1_V_PRMCMPEN12 2 1912 #define PRCR1_M_PRMCMPEN12 (1 << PRCR1_V_PRMCMPEN12) 1913 #define PRCR1_V_PRMCMPEN13 3 1914 #define PRCR1_M_PRMCMPEN13 (1 << PRCR1_V_PRMCMPEN13) 1915 #define PRCR1_V_PRMCMPEN14 4 1916 #define PRCR1_M_PRMCMPEN14 (1 << PRCR1_V_PRMCMPEN14) 1917 #define PRCR1_V_PRMCMPEN15 5 1918 #define PRCR1_M_PRMCMPEN15 (1 << PRCR1_V_PRMCMPEN15) 1919 #define PRCR1_V_PRMCMPEN16 6 1920 #define PRCR1_M_PRMCMPEN16 (1 << PRCR1_V_PRMCMPEN16) 1921 #define PRCR1_V_PRMCMPEN17 7 1922 #define PRCR1_M_PRMCMPEN17 (1 << PRCR1_V_PRMCMPEN17) 1923 #define PRCR1_V_PRMCMPEN18 8 1924 #define PRCR1_M_PRMCMPEN18 (1 << PRCR1_V_PRMCMPEN18) 1925 #define PRCR1_V_PRMCMPEN19 9 1926 #define PRCR1_M_PRMCMPEN19 (1 << PRCR1_V_PRMCMPEN19) 1927 #define PRCR1_V_PRMWR1EN 10 1928 #define PRCR1_M_PRMWR1EN (1 << PRCR1_V_PRMWR1EN) 1929 #define PRCR1_V_PRMRD1EN 11 1930 #define PRCR1_M_PRMRD1EN (1 << PRCR1_V_PRMRD1EN) 1931 #define PRCR1_V_PRM1MIO 12 1932 #define PRCR1_M_PRM1MIO (1 << PRCR1_V_PRM1MIO) 1933 #define PRCR1_V_PRM1EN 13 1934 #define PRCR1_M_PRM1EN (1 << PRCR1_V_PRM1EN) 1935 1936 /* 1937 ** 1938 ** Programmable Range Address Register 2 (PRAR2) - Index 0x024 1939 ** 1940 ** Loc Size Name Function 1941 ** ----- ---- ---- --------------------------------- 1942 ** <0> 9 PRMA PRM 2 Address 1943 ** <14> 1 PROSHDW2EN Programmable Shadow Register 2 Enable 1944 ** <15> 1 PROCS2EN Programmable Chip Select 2 Enable 1945 ** 1946 ** <10:13> Reserved 1947 ** 1948 */ 1949 #define PMC_PRAR2_REG 0x024 1950 #define PRAR2_V_PRMA 0 1951 #define PRAR2_M_PRMA (0x3FF << PRAR2_V_PRMA) 1952 #define PRAR2_V_PROSHDW2EN 14 1953 #define PRAR2_M_PROSHDW2EN (1 << PRAR2_V_PROSHDW2EN) 1954 #define PRAR2_V_PROCS2EN 15 1955 #define PRAR2_M_PROCS2EN (1 << PRAR2_V_PROCS2EN) 1956 1957 /* 1958 ** 1959 ** Programmable Range Compare Register 2 (PRCR2) - Index 0x025 1960 ** 1961 ** Loc Size Name Function 1962 ** ----- ---- ---- --------------------------------- 1963 ** <0> 1 PRMCMPEN10 PRM 2 Compare Enable 0 1964 ** <1> 1 PRMCMPEN11 PRM 2 Compare Enable 1 1965 ** <2> 1 PRMCMPEN12 PRM 2 Compare Enable 2 1966 ** <3> 1 PRMCMPEN13 PRM 2 Compare Enable 3 1967 ** <4> 1 PRMCMPEN14 PRM 2 Compare Enable 4 1968 ** <5> 1 PRMCMPEN15 PRM 2 Compare Enable 5 1969 ** <6> 1 PRMCMPEN16 PRM 2 Compare Enable 6 1970 ** <7> 1 PRMCMPEN17 PRM 2 Compare Enable 7 1971 ** <8> 1 PRMCMPEN18 PRM 2 Compare Enable 8 1972 ** <9> 1 PRMCMPEN19 PRM 2 Compare Enable 9 1973 ** <10> 1 PRMWR2EN PRM 2 Compare Write Enable 1974 ** <11> 1 PRMRD2EN PRM 2 Compare Read Enable 1975 ** <12> 1 PRM2MIO PRM 2 Memory or I/O Compare Enable 1976 ** <13> 1 PRM2EN PRM 2 Enable 1977 ** 1978 ** <14:15> Reserved 1979 ** 1980 */ 1981 #define PMC_PRCR2_REG 0x025 1982 #define PMC_PRCR2_INIT 0x0000 1983 #define PRCR2_V_PRMCMPEN 0 1984 #define PRCR2_M_PRMCMPEN (0x3FF << PRCR2_V_PRMCMPEN) 1985 #define PRCR2_V_PRMCMPEN10 0 1986 #define PRCR2_M_PRMCMPEN10 (1 << PRCR2_V_PRMCMPEN10) 1987 #define PRCR2_V_PRMCMPEN11 1 1988 #define PRCR2_M_PRMCMPEN11 (1 << PRCR2_V_PRMCMPEN11) 1989 #define PRCR2_V_PRMCMPEN12 2 1990 #define PRCR2_M_PRMCMPEN12 (1 << PRCR2_V_PRMCMPEN12) 1991 #define PRCR2_V_PRMCMPEN13 3 1992 #define PRCR2_M_PRMCMPEN13 (1 << PRCR2_V_PRMCMPEN13) 1993 #define PRCR2_V_PRMCMPEN14 4 1994 #define PRCR2_M_PRMCMPEN14 (1 << PRCR2_V_PRMCMPEN14) 1995 #define PRCR2_V_PRMCMPEN15 5 1996 #define PRCR2_M_PRMCMPEN15 (1 << PRCR2_V_PRMCMPEN15) 1997 #define PRCR2_V_PRMCMPEN16 6 1998 #define PRCR2_M_PRMCMPEN16 (1 << PRCR2_V_PRMCMPEN16) 1999 #define PRCR2_V_PRMCMPEN17 7 2000 #define PRCR2_M_PRMCMPEN17 (1 << PRCR2_V_PRMCMPEN17) 2001 #define PRCR2_V_PRMCMPEN18 8 2002 #define PRCR2_M_PRMCMPEN18 (1 << PRCR2_V_PRMCMPEN18) 2003 #define PRCR2_V_PRMCMPEN19 9 2004 #define PRCR2_M_PRMCMPEN19 (1 << PRCR2_V_PRMCMPEN19) 2005 #define PRCR2_V_PRMWR2EN 10 2006 #define PRCR2_M_PRMWR2EN (1 << PRCR2_V_PRMWR2EN) 2007 #define PRCR2_V_PRMRD2EN 11 2008 #define PRCR2_M_PRMRD2EN (1 << PRCR2_V_PRMRD2EN) 2009 #define PRCR2_V_PRM2MIO 12 2010 #define PRCR2_M_PRM2MIO (1 << PRCR2_V_PRM2MIO) 2011 #define PRCR2_V_PRM2EN 13 2012 #define PRCR2_M_PRM2EN (1 << PRCR2_V_PRM2EN) 2013 2014 /* 2015 ** 2016 ** Programmable Range Address Register 3 (PRAR3) - Index 0x026 2017 ** 2018 ** Loc Size Name Function 2019 ** ----- ---- ---- --------------------------------- 2020 ** <0> 9 PRMA PRM 3 Address 2021 ** <14> 1 PROSHDW3EN Programmable Shadow Register 3 Enable 2022 ** <15> 1 PROCS3EN Programmable Chip Select 3 Enable 2023 ** 2024 ** <10:13> Reserved 2025 ** 2026 */ 2027 #define PMC_PRAR3_REG 0x026 2028 #define PMC_PRAR3_INIT 0x0000 2029 #define PRAR3_V_PRMA 0 2030 #define PRAR3_M_PRMA (0x3FF << PRAR3_V_PRMA) 2031 #define PRAR3_V_PROSHDW3EN 14 2032 #define PRAR3_M_PROSHDW3EN (1 << PRAR3_V_PROSHDW3EN) 2033 #define PRAR3_V_PROCS3EN 15 2034 #define PRAR3_M_PROCS3EN (1 << PRAR3_V_PROCS3EN) 2035 2036 /* 2037 ** 2038 ** Programmable Range Compare Register 3 (PRCR3) - Index 0x027 2039 ** 2040 ** Loc Size Name Function 2041 ** ----- ---- ---- --------------------------------- 2042 ** <0> 1 PRMCMPEN10 PRM 3 Compare Enable 0 2043 ** <1> 1 PRMCMPEN11 PRM 3 Compare Enable 1 2044 ** <2> 1 PRMCMPEN12 PRM 3 Compare Enable 2 2045 ** <3> 1 PRMCMPEN13 PRM 3 Compare Enable 3 2046 ** <4> 1 PRMCMPEN14 PRM 3 Compare Enable 4 2047 ** <5> 1 PRMCMPEN15 PRM 3 Compare Enable 5 2048 ** <6> 1 PRMCMPEN16 PRM 3 Compare Enable 6 2049 ** <7> 1 PRMCMPEN17 PRM 3 Compare Enable 7 2050 ** <8> 1 PRMCMPEN18 PRM 3 Compare Enable 8 2051 ** <9> 1 PRMCMPEN19 PRM 3 Compare Enable 9 2052 ** <10> 1 PRMWR3EN PRM 3 Compare Write Enable 2053 ** <11> 1 PRMRD3EN PRM 3 Compare Read Enable 2054 ** <12> 1 PRM3MIO PRM 3 Memory or I/O Compare Enable 2055 ** <13> 1 PRM3EN PRM 3 Enable 2056 ** 2057 ** <14:15> Reserved 2058 ** 2059 */ 2060 #define PMC_PRCR3_REG 0x027 2061 #define PMC_PRCR3_INIT 0x0000 2062 #define PRCR3_V_PRMCMPEN 0 2063 #define PRCR3_M_PRMCMPEN (0x3FF << PRCR3_V_PRMCMPEN) 2064 #define PRCR3_V_PRMCMPEN10 0 2065 #define PRCR3_M_PRMCMPEN10 (1 << PRCR3_V_PRMCMPEN10) 2066 #define PRCR3_V_PRMCMPEN11 1 2067 #define PRCR3_M_PRMCMPEN11 (1 << PRCR3_V_PRMCMPEN11) 2068 #define PRCR3_V_PRMCMPEN12 2 2069 #define PRCR3_M_PRMCMPEN12 (1 << PRCR3_V_PRMCMPEN12) 2070 #define PRCR3_V_PRMCMPEN13 3 2071 #define PRCR3_M_PRMCMPEN13 (1 << PRCR3_V_PRMCMPEN13) 2072 #define PRCR3_V_PRMCMPEN14 4 2073 #define PRCR3_M_PRMCMPEN14 (1 << PRCR3_V_PRMCMPEN14) 2074 #define PRCR3_V_PRMCMPEN15 5 2075 #define PRCR3_M_PRMCMPEN15 (1 << PRCR3_V_PRMCMPEN15) 2076 #define PRCR3_V_PRMCMPEN16 6 2077 #define PRCR3_M_PRMCMPEN16 (1 << PRCR3_V_PRMCMPEN16) 2078 #define PRCR3_V_PRMCMPEN17 7 2079 #define PRCR3_M_PRMCMPEN17 (1 << PRCR3_V_PRMCMPEN17) 2080 #define PRCR3_V_PRMCMPEN18 8 2081 #define PRCR3_M_PRMCMPEN18 (1 << PRCR3_V_PRMCMPEN18) 2082 #define PRCR3_V_PRMCMPEN19 9 2083 #define PRCR3_M_PRMCMPEN19 (1 << PRCR3_V_PRMCMPEN19) 2084 #define PRCR3_V_PRMWR3EN 10 2085 #define PRCR3_M_PRMWR3EN (1 << PRCR3_V_PRMWR3EN) 2086 #define PRCR3_V_PRMRD3EN 11 2087 #define PRCR3_M_PRMRD3EN (1 << PRCR3_V_PRMRD3EN) 2088 #define PRCR3_V_PRM3MIO 12 2089 #define PRCR3_M_PRM3MIO (1 << PRCR3_V_PRM3MIO) 2090 #define PRCR3_V_PRM3EN 13 2091 #define PRCR3_M_PRM3EN (1 << PRCR3_V_PRM3EN) 2092 2093 /* 2094 ** 2095 ** Programmable Time-out Timer Register 0 (PTOTR0) - Index 0x028 2096 ** 2097 ** Loc Size Name Function 2098 ** ----- ---- ---- --------------------------------- 2099 ** <0> 1 PROGTMR00 Programmable Time-out Timer 0 0 2100 ** <1> 1 PROGTMR01 Programmable Time-out Timer 0 1 2101 ** <2> 1 PROGTMR02 Programmable Time-out Timer 0 2 2102 ** <3> 1 PROGTMR03 Programmable Time-out Timer 0 3 2103 ** <7> 1 TMR0SOURCE Clock Source for Timer 0 2104 ** <14> 1 TMR0PC2EN Time-out Timer 0 to PC2 Enable 2105 ** <15> 1 TMR0EN Programmable Timer 0 Enable 2106 ** 2107 ** <4:6><8:13> Reserved 2108 ** 2109 */ 2110 #define PMC_PTOTR0_REG 0x028 2111 #define PMC_PTOTR0_INIT 0x0000 2112 #define PTOTR0_V_PROGTMR0 0 2113 #define PTOTR0_M_PROGTMR0 (0xF << PTOTR0_V_PROGTMR0) 2114 #define PTOTR0_V_PROGTMR00 0 2115 #define PTOTR0_M_PROGTMR00 (1 << PTOTR0_V_PROGTMR00) 2116 #define PTOTR0_V_PROGTMR01 1 2117 #define PTOTR0_M_PROGTMR01 (1 << PTOTR0_V_PROGTMR01) 2118 #define PTOTR0_V_PROGTMR02 2 2119 #define PTOTR0_M_PROGTMR02 (1 << PTOTR0_V_PROGTMR02) 2120 #define PTOTR0_V_PROGTMR03 3 2121 #define PTOTR0_M_PROGTMR03 (1 << PTOTR0_V_PROGTMR03) 2122 #define PTOTR0_V_TMR0SOURCE 7 2123 #define PTOTR0_M_TMR0SOURCE (1 << PTOTR0_V_TMR0SOURCE) 2124 #define PTOTR0_V_TMR0PC2EN 14 2125 #define PTOTR0_M_TMR0PC2EN (1 << PTOTR0_V_TMR0PC2EN) 2126 #define PTOTR0_V_TMR0EN 15 2127 #define PTOTR0_M_TMR0EN (1 << PTOTR0_V_TMR0EN) 2128 2129 /* 2130 ** Programmable Time-out Timer 0 2131 */ 2132 #define PROGTMR0_2S 0x000 2133 #define PROGTMR0_5S PTOTR0_M_PROGTMR00 2134 #define PROGTMR0_10S PTOTR0_M_PROGTMR01 2135 #define PROGTMR0_15S (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01) 2136 #define PROGTMR0_30S PTOTR0_M_PROGTMR02 2137 #define PROGTMR0_45S (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR02) 2138 #define PROGTMR0_60S (PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02) 2139 #define PROGTMR0_90S (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02) 2140 #define PROGTMR0_2MIN PTOTR0_M_PROGTMR03 2141 #define PROGTMR0_3MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR03) 2142 #define PROGTMR0_4MIN (PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR03) 2143 #define PROGTMR0_6MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR03 2144 #define PROGTMR0_8MIN (PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) 2145 #define PROGTMR0_10MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) 2146 #define PROGTMR0_15MIN (PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) 2147 #define PROGTMR0_20MIN (PTOTR0_M_PROGTMR00 | PTOTR0_M_PROGTMR01 | PTOTR0_M_PROGTMR02 | PTOTR0_M_PROGTMR03) 2148 2149 /* 2150 ** 2151 ** Programmable Time-out Timer Register 1 (PTOTR1) - Index 0x029 2152 ** 2153 ** Loc Size Name Function 2154 ** ----- ---- ---- --------------------------------- 2155 ** <0> 1 PROGTMR10 Programmable Time-out Timer 1 0 2156 ** <1> 1 PROGTMR11 Programmable Time-out Timer 1 1 2157 ** <2> 1 PROGTMR12 Programmable Time-out Timer 1 2 2158 ** <3> 1 PROGTMR13 Programmable Time-out Timer 1 3 2159 ** <7> 1 TMR1SOURCE Clock Source for Timer 1 2160 ** <14> 1 TMR1PC3EN Time-out Timer 1 to PC3 Enable 2161 ** <15> 1 TMR1EN Programmable Timer 1 Enable 2162 ** 2163 ** <4:6><8:13> Reserved 2164 ** 2165 */ 2166 #define PMC_PTOTR1_REG 0x029 2167 #define PMC_PTOTR1_INIT 0x0000 2168 #define PTOTR1_V_PROGTMR1 0 2169 #define PTOTR1_M_PROGTMR1 (0xF << PTOTR1_V_PROGTMR1) 2170 #define PTOTR1_V_PROGTMR10 0 2171 #define PTOTR1_M_PROGTMR10 (1 << PTOTR1_V_PROGTMR10) 2172 #define PTOTR1_V_PROGTMR11 1 2173 #define PTOTR1_M_PROGTMR11 (1 << PTOTR1_V_PROGTMR11) 2174 #define PTOTR1_V_PROGTMR12 2 2175 #define PTOTR1_M_PROGTMR12 (1 << PTOTR1_V_PROGTMR12) 2176 #define PTOTR1_V_PROGTMR13 3 2177 #define PTOTR1_M_PROGTMR13 (1 << PTOTR1_V_PROGTMR13) 2178 #define PTOTR1_V_TMR1SOURCE 7 2179 #define PTOTR1_M_TMR1SOURCE (1 << PTOTR1_V_TMR1SOURCE) 2180 #define PTOTR1_V_TMR1PC3EN 14 2181 #define PTOTR1_M_TMR1PC3EN (1 << PTOTR1_V_TMR1PC3EN) 2182 #define PTOTR1_V_TMR1EN 15 2183 #define PTOTR1_M_TMR1EN (1 << PTOTR1_V_TMR1EN) 2184 2185 /* 2186 ** Programmable Time-out Timer 1 2187 */ 2188 #define PROGTMR1_2S 0x000 2189 #define PROGTMR1_5S PTOTR1_M_PROGTMR10 2190 #define PROGTMR1_10S PTOTR1_M_PROGTMR11 2191 #define PROGTMR1_15S (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11) 2192 #define PROGTMR1_30S PTOTR1_M_PROGTMR12 2193 #define PROGTMR1_45S (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR12) 2194 #define PROGTMR1_60S (PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12) 2195 #define PROGTMR1_90S (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12) 2196 #define PROGTMR1_2MIN PTOTR1_M_PROGTMR13 2197 #define PROGTMR1_3MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR13) 2198 #define PROGTMR1_4MIN (PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR13) 2199 #define PROGTMR1_6MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR13 2200 #define PROGTMR1_8MIN (PTOTR1_M_PROGTMR12 | PTOTR1_M_PROGTMR13) 2201 #define PROGTMR1_10MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR12 | PTOTR1_M_PROGTMR13) 2202 #define PROGTMR1_15MIN (PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12 | PTOTR1_M_PROGTMR13) 2203 #define PROGTMR1_20MIN (PTOTR1_M_PROGTMR10 | PTOTR1_M_PROGTMR11 | PTOTR1_M_PROGTMR12 | PTOTR0_M_PROGTMR13) 2204 2205 /* 2206 ** 2207 ** Programmable Time-out Timer Register 2 (PTOTR2) - Index 0x02A 2208 ** 2209 ** Loc Size Name Function 2210 ** ----- ---- ---- --------------------------------- 2211 ** <0> 1 PROGTMR20 Programmable Time-out Timer 2 0 2212 ** <1> 1 PROGTMR21 Programmable Time-out Timer 2 1 2213 ** <2> 1 PROGTMR22 Programmable Time-out Timer 2 2 2214 ** <3> 1 PROGTMR23 Programmable Time-out Timer 2 3 2215 ** <7> 1 TMR2SOURCE Clock Source for Timer 2 2216 ** <14> 1 TMR2PC8EN Time-out Timer 2 to PC8 Enable 2217 ** <15> 1 TMR2EN Programmable Timer 2 Enable 2218 ** 2219 ** <4:6><8:13> Reserved 2220 ** 2221 */ 2222 #define PMC_PTOTR2_REG 0x02A 2223 #define PMC_PTOTR2_INIT 0x0000 2224 #define PTOTR2_V_PROGTMR2 0 2225 #define PTOTR2_M_PROGTMR2 (0xF << PTOTR2_V_PROGTMR2) 2226 #define PTOTR2_V_PROGTMR20 0 2227 #define PTOTR2_M_PROGTMR20 (1 << PTOTR2_V_PROGTMR20) 2228 #define PTOTR2_V_PROGTMR21 1 2229 #define PTOTR2_M_PROGTMR21 (1 << PTOTR2_V_PROGTMR21) 2230 #define PTOTR2_V_PROGTMR22 2 2231 #define PTOTR2_M_PROGTMR22 (1 << PTOTR2_V_PROGTMR22) 2232 #define PTOTR2_V_PROGTMR23 3 2233 #define PTOTR2_M_PROGTMR23 (1 << PTOTR2_V_PROGTMR23) 2234 #define PTOTR2_V_TMR2SOURCE 7 2235 #define PTOTR2_M_TMR2SOURCE (1 << PTOTR2_V_TMR2SOURCE) 2236 #define PTOTR2_V_TMR2PC8EN 14 2237 #define PTOTR2_M_TMR2PC8EN (1 << PTOTR2_V_TMR2PC8EN) 2238 #define PTOTR2_V_TMR2EN 15 2239 #define PTOTR2_M_TMR2EN (1 << PTOTR2_V_TMR2EN) 2240 2241 /* 2242 ** Programmable Time-out Timer 2 2243 */ 2244 #define PROGTMR2_2S 0x000 2245 #define PROGTMR2_5S PTOTR2_M_PROGTMR20 2246 #define PROGTMR2_10S PTOTR2_M_PROGTMR21 2247 #define PROGTMR2_15S (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21) 2248 #define PROGTMR2_30S PTOTR2_M_PROGTMR22 2249 #define PROGTMR2_45S (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR22) 2250 #define PROGTMR2_60S (PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22) 2251 #define PROGTMR2_90S (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22) 2252 #define PROGTMR2_2MIN PTOTR2_M_PROGTMR23 2253 #define PROGTMR2_3MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR23) 2254 #define PROGTMR2_4MIN (PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR23) 2255 #define PROGTMR2_6MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR23 2256 #define PROGTMR2_8MIN (PTOTR2_M_PROGTMR22 | PTOTR2_M_PROGTMR23) 2257 #define PROGTMR2_10MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR22 | PTOTR2_M_PROGTMR23) 2258 #define PROGTMR2_15MIN (PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22 | PTOTR2_M_PROGTMR23) 2259 #define PROGTMR2_20MIN (PTOTR2_M_PROGTMR20 | PTOTR2_M_PROGTMR21 | PTOTR2_M_PROGTMR22 | PTOTR0_M_PROGTMR23) 2260 2261 /* 2262 ** 2263 ** Programmable Time-out Timer Register 3 (PTOTR3) - Index 0x02B 2264 ** 2265 ** Loc Size Name Function 2266 ** ----- ---- ---- --------------------------------- 2267 ** <0> 1 PROGTMR30 Programmable Time-out Timer 3 0 2268 ** <1> 1 PROGTMR31 Programmable Time-out Timer 3 1 2269 ** <2> 1 PROGTMR32 Programmable Time-out Timer 3 2 2270 ** <3> 1 PROGTMR33 Programmable Time-out Timer 3 3 2271 ** <7> 1 TMR3SOURCE Clock Source for Timer 3 2272 ** <14> 1 TMR3PC9EN Time-out Timer 3 to PC9 Enable 2273 ** <15> 1 TMR3EN Programmable Timer 3 Enable 2274 ** 2275 ** <4:6><8:13> Reserved 2276 ** 2277 */ 2278 #define PMC_PTOTR3_REG 0x02B 2279 #define PMC_PTOTR3_INIT 0x0000 2280 #define PTOTR3_V_PROGTMR3 0 2281 #define PTOTR3_M_PROGTMR3 (0xF << PTOTR3_V_PROGTMR3) 2282 #define PTOTR3_V_PROGTMR30 0 2283 #define PTOTR3_M_PROGTMR30 (1 << PTOTR3_V_PROGTMR30) 2284 #define PTOTR3_V_PROGTMR31 1 2285 #define PTOTR3_M_PROGTMR31 (1 << PTOTR3_V_PROGTMR31) 2286 #define PTOTR3_V_PROGTMR32 2 2287 #define PTOTR3_M_PROGTMR32 (1 << PTOTR3_V_PROGTMR32) 2288 #define PTOTR3_V_PROGTMR33 3 2289 #define PTOTR3_M_PROGTMR33 (1 << PTOTR3_V_PROGTMR33) 2290 #define PTOTR3_V_TMR3SOURCE 7 2291 #define PTOTR3_M_TMR3SOURCE (1 << PTOTR3_V_TMR3SOURCE) 2292 #define PTOTR3_V_TMR3PC9EN 14 2293 #define PTOTR3_M_TMR3PC9EN (1 << PTOTR3_V_TMR3PC9EN) 2294 #define PTOTR3_V_TMR3EN 15 2295 #define PTOTR3_M_TMR3EN (1 << PTOTR3_V_TMR3EN) 2296 2297 /* 2298 ** Programmable Time-out Timer 3 2299 */ 2300 #define PROGTMR3_2S 0x000 2301 #define PROGTMR3_5S PTOTR3_M_PROGTMR30 2302 #define PROGTMR3_10S PTOTR3_M_PROGTMR31 2303 #define PROGTMR3_15S (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31) 2304 #define PROGTMR3_30S PTOTR3_M_PROGTMR32 2305 #define PROGTMR3_45S (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR32) 2306 #define PROGTMR3_60S (PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32) 2307 #define PROGTMR3_90S (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32) 2308 #define PROGTMR3_2MIN PTOTR3_M_PROGTMR33 2309 #define PROGTMR3_3MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR33) 2310 #define PROGTMR3_4MIN (PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR33) 2311 #define PROGTMR3_6MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR33 2312 #define PROGTMR3_8MIN (PTOTR3_M_PROGTMR32 | PTOTR3_M_PROGTMR33) 2313 #define PROGTMR3_10MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR32 | PTOTR3_M_PROGTMR33) 2314 #define PROGTMR3_15MIN (PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32 | PTOTR3_M_PROGTMR33) 2315 #define PROGTMR3_20MIN (PTOTR3_M_PROGTMR30 | PTOTR3_M_PROGTMR31 | PTOTR3_M_PROGTMR32 | PTOTR0_M_PROGTMR33) 2316 2317 /* 2318 ** 2319 ** Programmable Time-out Timer Source Register 1 (PTOTSR1) - Index 0x02C 2320 ** 2321 ** Loc Size Name Function 2322 ** ----- ---- ---- --------------------------------- 2323 ** <0> 1 VDTMRSEL0 Video Activity Time-out Timer Select 0 2324 ** <1> 1 VDTMRSEL1 Video Activity Time-out Timer Select 1 2325 ** <3> 1 VDTMRSELEN Video Activity Time-out Timer Select Enable 2326 ** <4> 1 HDTMRSEL0 Hard Drive Activity Time-out Timer Select 0 2327 ** <5> 1 HDTMRSEL1 Hard Drive Activity Time-out Timer Select 1 2328 ** <7> 1 HDTMRSELEN Hard Drive Activity Time-out Timer Select Enable 2329 ** <8> 1 FDTMRSEL0 Floppy Drive Activity Time-out Timer Select 0 2330 ** <9> 1 FDTMRSEL1 Floppy Drive Activity Time-out Timer Select 1 2331 ** <11> 1 FDTMRSELEN Floppy Drive Activity Time-out Timer Select Enable 2332 ** <12> 1 KBTMRSEL0 Keyboard Activity Time-out Timer Select 0 2333 ** <13> 1 KBTMRSEL1 Keyboard Activity Time-out Timer Select 1 2334 ** <15> 1 KBTMRSELEN Keyboard Activity Time-out Timer Select Enable 2335 ** 2336 ** <2><6><10><14> Reserved 2337 ** 2338 */ 2339 #define PMC_PTOTSR1_REG 0x02C 2340 #define PMC_PTOTSR1_INIT 0x0000 2341 #define PTOTSR1_V_VDTMRSEL 0 2342 #define PTOTSR1_M_VDTMRSEL (0x3 << PTOTSR1_V_VDTMRSEL) 2343 #define PTOTSR1_V_VDTMRSEL0 0 2344 #define PTOTSR1_M_VDTMRSEL0 (1 << PTOTSR1_V_VDTMRSEL0) 2345 #define PTOTSR1_V_VDTMRSEL1 1 2346 #define PTOTSR1_M_VDTMRSEL1 (1 << PTOTSR1_V_VDTMRSEL1) 2347 #define PTOTSR1_V_VDTMRSELEN 3 2348 #define PTOTSR1_M_VDTMRSELEN (1 << PTOTSR1_V_VDTMRSELEN) 2349 #define PTOTSR1_V_HDTMRSEL 4 2350 #define PTOTSR1_M_HDTMRSEL (0x3 << PTOTSR1_V_HDTMRSEL) 2351 #define PTOTSR1_V_HDTMRSEL0 4 2352 #define PTOTSR1_M_HDTMRSEL0 (1 << PTOTSR1_V_HDTMRSEL0) 2353 #define PTOTSR1_V_HDTMRSEL1 5 2354 #define PTOTSR1_M_HDTMRSEL1 (1 << PTOTSR1_V_HDTMRSEL1) 2355 #define PTOTSR1_V_HDTMRSELEN 7 2356 #define PTOTSR1_M_HDTMRSELEN (1 << PTOTSR1_V_HDTMRSELEN) 2357 #define PTOTSR1_V_FDTMRSEL 8 2358 #define PTOTSR1_M_FDTMRSEL (0x3 << PTOTSR1_V_FDTMRSEL) 2359 #define PTOTSR1_V_FDTMRSEL0 8 2360 #define PTOTSR1_M_FDTMRSEL0 (1 << PTOTSR1_V_FDTMRSEL0) 2361 #define PTOTSR1_V_FDTMRSEL1 9 2362 #define PTOTSR1_M_FDTMRSEL1 (1 << PTOTSR1_V_FDTMRSEL1) 2363 #define PTOTSR1_V_FDTMRSELEN 11 2364 #define PTOTSR1_M_FDTMRSELEN (1 << PTOTSR1_V_FDTMRSELEN) 2365 #define PTOTSR1_V_KBTMRSEL 12 2366 #define PTOTSR1_M_KBTMRSEL (0x3 << PTOTSR1_V_KBTMRSEL) 2367 #define PTOTSR1_V_KBTMRSEL0 12 2368 #define PTOTSR1_M_KBTMRSEL0 (1 << PTOTSR1_V_KBTMRSEL0) 2369 #define PTOTSR1_V_KBTMRSEL1 13 2370 #define PTOTSR1_M_KBTMRSEL1 (1 << PTOTSR1_V_KBTMRSEL1) 2371 #define PTOTSR1_V_KBTMRSELEN 15 2372 #define PTOTSR1_M_KBTMRSELEN (1 << PTOTSR1_V_KBTMRSELEN) 2373 2374 /* 2375 ** Video Activity Programmable Time-out Timer 2376 */ 2377 #define VDTMRSEL_0 0x000 2378 #define VDTMRSEL_1 PTOTSR1_M_VDTMRSEL0 2379 #define VDTMRSEL_2 PTOTSR1_M_VDTMRSEL1 2380 #define VDTMRSEL_3 (PTOTSR1_M_VDTMRSEL0 | PTOTSR1_M_VDTMRSEL1) 2381 2382 /* 2383 ** Hard Drive Activity Programmable Time-out Timer 2384 */ 2385 #define HDTMRSEL_0 0x000 2386 #define HDTMRSEL_1 PTOTSR1_M_HDTMRSEL0 2387 #define HDTMRSEL_2 PTOTSR1_M_HDTMRSEL1 2388 #define HDTMRSEL_3 (PTOTSR1_M_HDTMRSEL0 | PTOTSR1_M_HDTMRSEL1) 2389 2390 /* 2391 ** Floppy Drive Activity Programmable Time-out Timer 2392 */ 2393 #define FDTMRSEL_0 0x000 2394 #define FDTMRSEL_1 PTOTSR1_M_FDTMRSEL0 2395 #define FDTMRSEL_2 PTOTSR1_M_FDTMRSEL1 2396 #define FDTMRSEL_3 (PTOTSR1_M_FDTMRSEL0 | PTOTSR1_M_FDTMRSEL1) 2397 2398 /* 2399 ** Keyboard Activity Programmable Time-out Timer 2400 */ 2401 #define KBTMRSEL_0 0x000 2402 #define KBTMRSEL_1 PTOTSR1_M_KBTMRSEL0 2403 #define KBTMRSEL_2 PTOTSR1_M_KBTMRSEL1 2404 #define KBTMRSEL_3 (PTOTSR1_M_KBTMRSEL0 | PTOTSR1_M_KBTMRSEL1) 2405 2406 /* 2407 ** 2408 ** Programmable Time-out Timer Source Register 2 (PTOTSR2) - Index 0x02D 2409 ** 2410 ** Loc Size Name Function 2411 ** ----- ---- ---- --------------------------------- 2412 ** <0> 1 SIOTMRSEL0 Serial Port Activity Time-out Timer Select 0 2413 ** <1> 1 SIOTMRSEL1 Serial Port Activity Time-out Timer Select 1 2414 ** <3> 1 SIOTMRSELEN Serial Port Activity Time-out Timer Select Enable 2415 ** <4> 1 PIOTMRSEL0 Parallel Port Activity Time-out Timer Select 0 2416 ** <5> 1 PIOTMRSEL1 Parallel Port Activity Time-out Timer Select 1 2417 ** <7> 1 PIOTMRSELEN Parallel Port Activity Time-out Timer Select Enable 2418 ** <8> 1 PR0TMRSEL0 PRM 0 Activity Time-out Timer Select 0 2419 ** <9> 1 PR0TMRSEL1 PRM 0 Activity Time-out Timer Select 1 2420 ** <11> 1 PR0TMRSELEN PRM 0 Activity Time-out Timer Select Enable 2421 ** <12> 1 PR1TMRSEL0 PRM 1 Activity Time-out Timer Select 0 2422 ** <13> 1 PR1TMRSEL1 PRM 1 Activity Time-out Timer Select 1 2423 ** <15> 1 PR1TMRSELEN PRM 1 Activity Time-out Timer Select Enable 2424 ** 2425 ** <2><6><10><14> Reserved 2426 ** 2427 */ 2428 #define PMC_PTOTSR2_REG 0x02D 2429 #define PMC_PTOTSR2_INIT 0x0000 2430 #define PTOTSR2_V_SIOTMRSEL 0 2431 #define PTOTSR2_M_SIOTMRSEL (0x3 << PTOTSR2_V_SIOTMRSEL) 2432 #define PTOTSR2_V_SIOTMRSEL0 0 2433 #define PTOTSR2_M_SIOTMRSEL0 (1 << PTOTSR2_V_SIOTMRSEL0) 2434 #define PTOTSR2_V_SIOTMRSEL1 1 2435 #define PTOTSR2_M_SIOTMRSEL1 (1 << PTOTSR2_V_SIOTMRSEL1) 2436 #define PTOTSR2_V_SIOTMRSELEN 3 2437 #define PTOTSR2_M_SIOTMRSELEN (1 << PTOTSR2_V_SIOTMRSELEN) 2438 #define PTOTSR2_V_PIOTMRSEL 4 2439 #define PTOTSR2_M_PIOTMRSEL (0x3 << PTOTSR2_V_PIOTMRSEL) 2440 #define PTOTSR2_V_PIOTMRSEL0 4 2441 #define PTOTSR2_M_PIOTMRSEL0 (1 << PTOTSR2_V_PIOTMRSEL0) 2442 #define PTOTSR2_V_PIOTMRSEL1 5 2443 #define PTOTSR2_M_PIOTMRSEL1 (1 << PTOTSR2_V_PIOTMRSEL1) 2444 #define PTOTSR2_V_PIOTMRSELEN 7 2445 #define PTOTSR2_M_PIOTMRSELEN (1 << PTOTSR2_V_PIOTMRSELEN) 2446 #define PTOTSR2_V_PR0TMRSEL 8 2447 #define PTOTSR2_M_PR0TMRSEL (0x3 << PTOTSR2_V_PR0TMRSEL) 2448 #define PTOTSR2_V_PR0TMRSEL0 8 2449 #define PTOTSR2_M_PR0TMRSEL0 (1 << PTOTSR2_V_PR0TMRSEL0) 2450 #define PTOTSR2_V_PR0TMRSEL1 9 2451 #define PTOTSR2_M_PR0TMRSEL1 (1 << PTOTSR2_V_PR0TMRSEL1) 2452 #define PTOTSR2_V_PR0TMRSELEN 11 2453 #define PTOTSR2_M_PR0TMRSELEN (1 << PTOTSR2_V_PR0TMRSELEN) 2454 #define PTOTSR2_V_PR1TMRSEL 12 2455 #define PTOTSR2_M_PR1TMRSEL (0x3 << PTOTSR2_V_PR1TMRSEL) 2456 #define PTOTSR2_V_PR1TMRSEL0 12 2457 #define PTOTSR2_M_PR1TMRSEL0 (1 << PTOTSR2_V_PR1TMRSEL0) 2458 #define PTOTSR2_V_PR1TMRSEL1 13 2459 #define PTOTSR2_M_PR1TMRSEL1 (1 << PTOTSR2_V_PR1TMRSEL1) 2460 #define PTOTSR2_V_PR1TMRSELEN 15 2461 #define PTOTSR2_M_PR1TMRSELEN (1 << PTOTSR2_V_PR1TMRSELEN) 2462 2463 /* 2464 ** Serial Port Activity Programmable Time-out Timer 2465 */ 2466 #define SIOTMRSEL_0 0x000 2467 #define SIOTMRSEL_1 PTOTSR2_M_SIOTMRSEL0 2468 #define SIOTMRSEL_2 PTOTSR2_M_SIOTMRSEL1 2469 #define SIOTMRSEL_3 (PTOTSR2_M_SIOTMRSEL0 | PTOTSR2_M_SIOTMRSEL1) 2470 2471 /* 2472 ** Parallel Port Activity Programmable Time-out Timer 2473 */ 2474 #define PIOTMRSEL_0 0x000 2475 #define PIOTMRSEL_1 PTOTSR2_M_PIOTMRSEL0 2476 #define PIOTMRSEL_2 PTOTSR2_M_PIOTMRSEL1 2477 #define PIOTMRSEL_3 (PTOTSR2_M_PIOTMRSEL0 | PTOTSR2_M_PIOTMRSEL1) 2478 2479 /* 2480 ** PRM 0 Activity Programmable Time-out Timer 2481 */ 2482 #define PR0TMRSEL_0 0x000 2483 #define PR0TMRSEL_1 PTOTSR2_M_PR0TMRSEL0 2484 #define PR0TMRSEL_2 PTOTSR2_M_PR0TMRSEL1 2485 #define PR0TMRSEL_3 (PTOTSR2_M_PR0TMRSEL0 | PTOTSR2_M_PR0TMRSEL1) 2486 2487 /* 2488 ** PRM 1 Activity Programmable Time-out Timer 2489 */ 2490 #define PR1TMRSEL_0 0x000 2491 #define PR1TMRSEL_1 PTOTSR2_M_PR1TMRSEL0 2492 #define PR1TMRSEL_2 PTOTSR2_M_PR1TMRSEL1 2493 #define PR1TMRSEL_3 (PTOTSR2_M_PR1TMRSEL0 | PTOTSR2_M_PR1TMRSEL1) 2494 2495 /* 2496 ** 2497 ** Programmable Time-out Timer Source Register 3 (PTOTSR3) - Index 0x02E 2498 ** 2499 ** Loc Size Name Function 2500 ** ----- ---- ---- --------------------------------- 2501 ** <0> 1 PR2TMRSEL0 PRM 2 Activity Time-out Timer Select 0 2502 ** <1> 1 PR2TMRSEL1 PRM 2 Activity Time-out Timer Select 1 2503 ** <3> 1 PR2TMRSELEN PRM 2 Activity Time-out Timer Select Enable 2504 ** <4> 1 PR3TMRSEL0 PRM 3 Activity Time-out Timer Select 0 2505 ** <5> 1 PR3TMRSEL1 PRM 3 Activity Time-out Timer Select 1 2506 ** <7> 1 PR3TMRSELEN PRM 3 Activity Time-out Timer Select Enable 2507 ** 2508 ** <2><6><8:15> Reserved 2509 ** 2510 */ 2511 #define PMC_PTOTSR3_REG 0x02E 2512 #define PMC_PTOTSR3_INIT 0x0000 2513 #define PTOTSR3_V_PR2TMRSEL 0 2514 #define PTOTSR3_M_PR2TMRSEL (0x3 << PTOTSR3_V_PR2TMRSEL) 2515 #define PTOTSR3_V_PR2TMRSEL0 0 2516 #define PTOTSR3_M_PR2TMRSEL0 (1 << PTOTSR3_V_PR2TMRSEL0) 2517 #define PTOTSR3_V_PR2TMRSEL1 1 2518 #define PTOTSR3_M_PR2TMRSEL1 (1 << PTOTSR3_V_PR2TMRSEL1) 2519 #define PTOTSR3_V_PR2TMRSELEN 3 2520 #define PTOTSR3_M_PR2TMRSELEN (1 << PTOTSR3_V_PR2TMRSELEN) 2521 #define PTOTSR3_V_PR3TMRSEL 4 2522 #define PTOTSR3_M_PR3TMRSEL (0x3 << PTOTSR3_V_PR3TMRSEL) 2523 #define PTOTSR3_V_PR3TMRSEL0 4 2524 #define PTOTSR3_M_PR3TMRSEL0 (1 << PTOTSR3_V_PR3TMRSEL0) 2525 #define PTOTSR3_V_PR3TMRSEL1 5 2526 #define PTOTSR3_M_PR3TMRSEL1 (1 << PTOTSR3_V_PR3TMRSEL1) 2527 #define PTOTSR3_V_PR3TMRSELEN 7 2528 #define PTOTSR3_M_PR3TMRSELEN (1 << PTOTSR3_V_PR3TMRSELEN) 2529 2530 /* 2531 ** PRM 2 Activity Programmable Time-out Timer 2532 */ 2533 #define PR2TMRSEL_0 0x000 2534 #define PR2TMRSEL_1 PTOTSR3_M_PR2TMRSEL0 2535 #define PR2TMRSEL_2 PTOTSR3_M_PR2TMRSEL1 2536 #define PR2TMRSEL_3 (PTOTSR3_M_PR2TMRSEL0 | PTOTSR3_M_PR2TMRSEL1) 2537 2538 /* 2539 ** PRM 3 Activity Programmable Time-out Timer 2540 */ 2541 #define PR3TMRSEL_0 0x000 2542 #define PR3TMRSEL_1 PTOTSR3_M_PR3TMRSEL0 2543 #define PR3TMRSEL_2 PTOTSR3_M_PR3TMRSEL1 2544 #define PR3TMRSEL_3 (PTOTSR3_M_PR3TMRSEL0 | PTOTSR3_M_PR3TMRSEL1) 2545 2546 /* 2547 ** 2548 ** Programmable Time-out Timer Source Register 4 (PTOTSR4) - Index 0x02F 2549 ** 2550 ** Loc Size Name Function 2551 ** ----- ---- ---- --------------------------------- 2552 ** <0> 1 EXT0TMRSEL0 EXTACT0 Activity Time-out Timer Select 0 2553 ** <1> 1 EXT0TMRSEL1 EXTACT0 Activity Time-out Timer Select 1 2554 ** <3> 1 EXT0TMRSELEN EXTACT0 Activity Time-out Timer Select Enable 2555 ** <4> 1 EXT1TMRSEL0 EXTACT1 Activity Time-out Timer Select 0 2556 ** <5> 1 EXT1TMRSEL1 EXTACT1 Activity Time-out Timer Select 1 2557 ** <7> 1 EXT1TMRSELEN EXTACT1 Activity Time-out Timer Select Enable 2558 ** <8> 1 EXT2TMRSEL0 EXTACT2 Activity Time-out Timer Select 0 2559 ** <9> 1 EXT2TMRSEL1 EXTACT2 Activity Time-out Timer Select 1 2560 ** <11> 1 EXT2TMRSELEN EXTACT2 Activity Time-out Timer Select Enable 2561 ** <12> 1 EXT3TMRSEL0 EXTACT3 Activity Time-out Timer Select 0 2562 ** <13> 1 EXT3TMRSEL1 EXTACT3 Activity Time-out Timer Select 1 2563 ** <15> 1 EXT3TMRSELEN EXTACT3 Activity Time-out Timer Select Enable 2564 ** 2565 ** <2><6><10><14> Reserved 2566 ** 2567 */ 2568 #define PMC_PTOTSR4_REG 0x02F 2569 #define PMC_PTOTSR4_INIT 0x0000 2570 #define PTOTSR4_V_EXT0TMRSEL 0 2571 #define PTOTSR4_M_EXT0TMRSEL (0x3 << PTOTSR4_V_EXT0TMRSEL) 2572 #define PTOTSR4_V_EXT0TMRSEL0 0 2573 #define PTOTSR4_M_EXT0TMRSEL0 (1 << PTOTSR4_V_EXT0TMRSEL0) 2574 #define PTOTSR4_V_EXT0TMRSEL1 1 2575 #define PTOTSR4_M_EXT0TMRSEL1 (1 << PTOTSR4_V_EXT0TMRSEL1) 2576 #define PTOTSR4_V_EXT0TMRSELEN 3 2577 #define PTOTSR4_M_EXT0TMRSELEN (1 << PTOTSR4_V_EXT0TMRSELEN) 2578 #define PTOTSR4_V_EXT1TMRSEL 4 2579 #define PTOTSR4_M_EXT1TMRSEL (0x3 << PTOTSR4_V_EXT1TMRSEL) 2580 #define PTOTSR4_V_EXT1TMRSEL0 4 2581 #define PTOTSR4_M_EXT1TMRSEL0 (1 << PTOTSR4_V_EXT1TMRSEL0) 2582 #define PTOTSR4_V_EXT1TMRSEL1 5 2583 #define PTOTSR4_M_EXT1TMRSEL1 (1 << PTOTSR4_V_EXT1TMRSEL1) 2584 #define PTOTSR4_V_EXT1TMRSELEN 7 2585 #define PTOTSR4_M_EXT1TMRSELEN (1 << PTOTSR4_V_EXT1TMRSELEN) 2586 #define PTOTSR4_V_EXT2TMRSEL 8 2587 #define PTOTSR4_M_EXT2TMRSEL (0x3 << PTOTSR4_V_EXT2TMRSEL) 2588 #define PTOTSR4_V_EXT2TMRSEL0 8 2589 #define PTOTSR4_M_EXT2TMRSEL0 (1 << PTOTSR4_V_EXT2TMRSEL0) 2590 #define PTOTSR4_V_EXT2TMRSEL1 9 2591 #define PTOTSR4_M_EXT2TMRSEL1 (1 << PTOTSR4_V_EXT2TMRSEL1) 2592 #define PTOTSR4_V_EXT2TMRSELEN 11 2593 #define PTOTSR4_M_EXT2TMRSELEN (1 << PTOTSR4_V_EXT2TMRSELEN) 2594 #define PTOTSR4_V_EXT3TMRSEL 12 2595 #define PTOTSR4_M_EXT3TMRSEL (0x3 << PTOTSR4_V_EXT3TMRSEL) 2596 #define PTOTSR4_V_EXT3TMRSEL0 12 2597 #define PTOTSR4_M_EXT3TMRSEL0 (1 << PTOTSR4_V_EXT3TMRSEL0) 2598 #define PTOTSR4_V_EXT3TMRSEL1 13 2599 #define PTOTSR4_M_EXT3TMRSEL1 (1 << PTOTSR4_V_EXT3TMRSEL1) 2600 #define PTOTSR4_V_EXT3TMRSELEN 15 2601 #define PTOTSR4_M_EXT3TMRSELEN (1 << PTOTSR4_V_EXT3TMRSELEN) 2602 2603 /* 2604 ** EXTACT0 Activity Programmable Time-out Timer 2605 */ 2606 #define EXT0TMRSEL_0 0x000 2607 #define EXT0TMRSEL_1 PTOTSR4_M_EXT0TMRSEL0 2608 #define EXT0TMRSEL_2 PTOTSR4_M_EXT0TMRSEL1 2609 #define EXT0TMRSEL_3 (PTOTSR4_M_EXT0TMRSEL0 | PTOTSR4_M_EXT0TMRSEL1) 2610 2611 /* 2612 ** EXTACT1 Activity Programmable Time-out Timer 2613 */ 2614 #define EXT1TMRSEL_0 0x000 2615 #define EXT1TMRSEL_1 PTOTSR4_M_EXT1TMRSEL0 2616 #define EXT1TMRSEL_2 PTOTSR4_M_EXT1TMRSEL1 2617 #define EXT1TMRSEL_3 (PTOTSR4_M_EXT1TMRSEL0 | PTOTSR4_M_EXT1TMRSEL1) 2618 2619 /* 2620 ** EXTACT2 Activity Programmable Time-out Timer 2621 */ 2622 #define EXT2TMRSEL_0 0x000 2623 #define EXT2TMRSEL_1 PTOTSR4_M_EXT2TMRSEL0 2624 #define EXT2TMRSEL_2 PTOTSR4_M_EXT2TMRSEL1 2625 #define EXT2TMRSEL_3 (PTOTSR4_M_EXT2TMRSEL0 | PTOTSR4_M_EXT2TMRSEL1) 2626 2627 /* 2628 ** EXTACT3 Activity Programmable Time-out Timer 2629 */ 2630 #define EXT3TMRSEL_0 0x000 2631 #define EXT3TMRSEL_1 PTOTSR4_M_EXT3TMRSEL0 2632 #define EXT3TMRSEL_2 PTOTSR4_M_EXT3TMRSEL1 2633 #define EXT3TMRSEL_3 (PTOTSR4_M_EXT3TMRSEL0 | PTOTSR4_M_EXT3TMRSEL1) 2634 2635 /* 2636 ** System Registers 2637 ** 2638 */ 2639 2640 /* 2641 ** 2642 ** Power-On Register (POR) - Index 0x100 2643 ** 2644 ** Loc Size Name Function 2645 ** ----- ---- ---- --------------------------------- 2646 ** <0> 1 SEQUOIASEL SEQUOIA Select 2647 ** <3> 1 DLYBDEN Delay BD Bus Enable 2648 ** <4> 1 CPUMODESEL CPU Mode Select 2649 ** <6> 1 DLYBDBUSEN Delay BADS# & BDEV# Enable 2650 ** <7> 1 MISCCF0 Miscellaneous Configuration 0 2651 ** <8> 1 MISCCF1 Miscellaneous Configuration 1 2652 ** <9> 1 MISCCF2 Miscellaneous Configuration 2 2653 ** <11> 1 EXTRTC Optional External RTC 2654 ** <12> 1 1X2XCLKSEL 1X/2X Clock Select 2655 ** 2656 ** <1:2><5><10><13:15> Reserved 2657 */ 2658 #define SR_POR_REG 0x100 2659 #define POR_V_SEQUOIASEL 0 2660 #define POR_M_SEQUOIASEL (1 << POR_V_SEQUOIASEL) 2661 #define POR_V_DLYBDEN 3 2662 #define POR_M_DLYBDEN (1 << POR_V_DLYBDEN) 2663 #define POR_V_CPUMODESEL 4 2664 #define POR_M_CPUMODESEL (1 << POR_V_CPUMODESEL) 2665 #define POR_V_DLYBDBUSEN 6 2666 #define POR_M_DLYBDBUSEN (1 << POR_V_DLYBDBUSEN) 2667 #define POR_V_MISCCF 7 2668 #define POR_M_MISCCF (0x7 << POR_V_MISCCF) 2669 #define POR_V_MISCCF0 7 2670 #define POR_M_MISCCF0 (1 << POR_V_MISCCF0) 2671 #define POR_V_MISCCF1 8 2672 #define POR_M_MISCCF1 (1 << POR_V_MISCCF1) 2673 #define POR_V_MISCCF2 9 2674 #define POR_M_MISCCF2 (1 << POR_V_MISCCF2) 2675 #define POR_V_EXTRTC 11 2676 #define POR_M_EXTRTC (1 << POR_V_EXTRTC) 2677 #define POR_V_1X2XCLKSEL 12 2678 #define POR_M_1X2XCLKSEL (1 << POR_V_1X2XCLKSEL) 2679 2680 /* 2681 ** 2682 ** Non-Cacheable Region 1 Register (NCR1R) - Index 0x101 2683 ** 2684 ** Loc Size Name Function 2685 ** ----- ---- ---- --------------------------------- 2686 ** <0> 1 NCR1EN Enable Non-Cacheable Region 1 2687 ** <1> 1 NCR1BS0 Non-Cacheable Region 1 Block Size 0 2688 ** <2> 1 NCR1BS1 Non-Cacheable Region 1 Block Size 1 2689 ** <3> 13 NCR1A Non-Cacheable Region 1 Starting Addr 2690 ** 2691 */ 2692 #define SR_NCR1R_REG 0x101 2693 #define SR_NCR1R_INIT 0x0000 2694 #define NCR1R_V_NCR1EN 0 2695 #define NCR1R_M_NCR1EN (1 << NCR1R_V_NCR1EN) 2696 #define NCR1R_V_NCR1BS 1 2697 #define NCR1R_M_NCR1BS (0x3 << NCR1R_V_NCR1BS) 2698 #define NCR1R_V_NCR1BS0 1 2699 #define NCR1R_M_NCR1BS0 (1 << NCR1R_V_NCR1BS0) 2700 #define NCR1R_V_NCR1BS1 1 2701 #define NCR1R_M_NCR1BS1 (1 << NCR1R_V_NCR1BS1) 2702 #define NCR1R_V_NCR1A 3 2703 #define NCR1R_M_NCR1A (0xFFF8 << NCR1R_V_NCR1A) 2704 2705 /* 2706 ** Non-Cacheable Region 1 Block Size (Kbytes) 2707 */ 2708 #define NCR1BS_32K 0x000 2709 #define NCR1BS_64K NCR1R_M_NCR1BS0 2710 #define NCR1BS_128K NCR1R_M_NCR1BS1 2711 #define NCR1BS_256K (NCR1R_M_NCR1BS0 | NCR1R_M_NCR1BS1) 2712 2713 /* 2714 ** 2715 ** Non-Cacheable Region 2 Register (NCR2R) - Index 0x102 2716 ** 2717 ** Loc Size Name Function 2718 ** ----- ---- ---- --------------------------------- 2719 ** <0> 1 NCR2EN Enable Non-Cacheable Region 2 2720 ** <1> 1 NCR2BS0 Non-Cacheable Region 2 Block Size 0 2721 ** <2> 1 NCR2BS1 Non-Cacheable Region 2 Block Size 1 2722 ** <3> 13 NCR2A Non-Cacheable Region 2 Starting Addr 2723 ** 2724 */ 2725 #define SR_NCR2R_REG 0x102 2726 #define SR_NCR2R_INIT 0x0000 2727 #define NCR2R_V_NCR2EN 0 2728 #define NCR2R_M_NCR2EN (1 << NCR2R_V_NCR2EN) 2729 #define NCR2R_V_NCR2BS 1 2730 #define NCR2R_M_NCR2BS (0x3 << NCR2R_V_NCR2BS) 2731 #define NCR2R_V_NCR2BS0 1 2732 #define NCR2R_M_NCR2BS0 (1 << NCR2R_V_NCR2BS0) 2733 #define NCR2R_V_NCR2BS1 1 2734 #define NCR2R_M_NCR2BS1 (1 << NCR2R_V_NCR2BS1) 2735 #define NCR2R_V_NCR2A 3 2736 #define NCR2R_M_NCR2A (0xFFF8 << NCR2R_V_NCR2A) 2737 2738 /* 2739 ** Non-Cacheable Region 2 Block Size (Kbytes) 2740 */ 2741 #define NCR2BS_32K 0x000 2742 #define NCR2BS_64K NCR2R_M_NCR2BS0 2743 #define NCR2BS_128K NCR2R_M_NCR2BS1 2744 #define NCR2BS_256K (NCR2R_M_NCR2BS0 | NCR2R_M_NCR2BS1) 2745 2746 /* 2747 ** 2748 ** SYS Miscellaneous Control Register 1 (SYSMCR1) - Index 0x103 2749 ** 2750 ** Loc Size Name Function 2751 ** ----- ---- ---- --------------------------------- 2752 ** <0> 1 LDSMIHLDER Load SMI Handler into SMM Space 2753 ** <1> 1 MOVRLYEN Memory Overlay Enable 2754 ** <2> 1 SMMMAPSEL SMM Memory Map Select 2755 ** <3> 1 SMMDETECT SMM Detect 2756 ** <4> 1 FLUSHWSMI Generate FLUSH# with SMI# Active 2757 ** <5> 1 SMIFLUSHIN SMI Flush In 2758 ** <6> 1 SMIFLUSHOUT SMI Flush Out 2759 ** <7> 1 SMMKENDIS SMM KEN Disable 2760 ** <8> 1 KDISSMMREG SMM Region KEN Disable 2761 ** <9> 1 SMISEL SMI Select 2762 ** <10> 1 SMMBLASTL Force BLAST# Low During SMM Cycles Enable 2763 ** <11> 1 SMMMSKA20 SMM Mask A20 2764 ** <13> 1 SMMMAPD SMM Memory Map Using D Segment 2765 ** <14> 1 SMMMAPE SMM Memory Map Using E Segment 2766 ** <15> 1 SMISTRTSEL SMI Start Select 2767 ** 2768 ** <12> Reserved 2769 */ 2770 #define SR_SYSMCR1_REG 0x103 2771 #define SR_SYSMCR1_INIT SYSMCR1_M_SMISEL 2772 #define SYSMCR1_V_LDSMIHLDER 0 2773 #define SYSMCR1_M_LDSMIHLDER (1 << SYSMCR1_V_LDSMIHLDER) 2774 #define SYSMCR1_V_MOVRLYEN 1 2775 #define SYSMCR1_M_MOVRLYEN (1 << SYSMCR1_V_MOVRLYEN) 2776 #define SYSMCR1_V_SMMMAPSEL 2 2777 #define SYSMCR1_M_SMMMAPSEL (1 << SYSMCR1_V_SMMMAPSEL) 2778 #define SYSMCR1_V_SMMDETECT 3 2779 #define SYSMCR1_M_SMMDETECT (1 << SYSMCR1_V_SMMDETECT) 2780 #define SYSMCR1_V_FLUSHWSMI 4 2781 #define SYSMCR1_M_FLUSHWSMI (1 << SYSMCR1_V_FLUSHWSMI) 2782 #define SYSMCR1_V_SMIFLUSHIN 5 2783 #define SYSMCR1_M_SMIFLUSHIN (1 << SYSMCR1_V_SMIFLUSHIN) 2784 #define SYSMCR1_V_SMIFLUSHOUT 6 2785 #define SYSMCR1_M_SMIFLUSHOUT (1 << SYSMCR1_V_SMIFLUSHOUT) 2786 #define SYSMCR1_V_SMMKENDIS 7 2787 #define SYSMCR1_M_SMMKENDIS (1 << SYSMCR1_V_SMMKENDIS) 2788 #define SYSMCR1_V_KDISSMMREG 8 2789 #define SYSMCR1_M_KDISSMMREG (1 << SYSMCR1_V_KDISSMMREG) 2790 #define SYSMCR1_V_SMISEL 9 2791 #define SYSMCR1_M_SMISEL (1 << SYSMCR1_V_SMISEL) 2792 #define SYSMCR1_V_SMMBLASTL 10 2793 #define SYSMCR1_M_SMMBLASTL (1 << SYSMCR1_V_SMMBLASTL) 2794 #define SYSMCR1_V_SMMMSKA20 11 2795 #define SYSMCR1_M_SMMMSKA20 (1 << SYSMCR1_V_SMMMSKA20) 2796 #define SYSMCR1_V_SMMMAPD 13 2797 #define SYSMCR1_M_SMMMAPD (1 << SYSMCR1_V_SMMMAPD) 2798 #define SYSMCR1_V_SMMMAPE 14 2799 #define SYSMCR1_M_SMMMAPE (1 << SYSMCR1_V_SMMMAPE) 2800 #define SYSMCR1_V_SMISTRTSEL 15 2801 #define SYSMCR1_M_SMISTRTSEL (1 << SYSMCR1_V_SMISTRTSEL) 2802 2803 /* 2804 ** 2805 ** SYS Miscellaneous Control Register 2 (SYSMCR2) - Index 0x104 2806 ** 2807 ** Loc Size Name Function 2808 ** ----- ---- ---- --------------------------------- 2809 ** <0> 1 SMIHLDOFRST Enable Hold-Off of SRESET During SMI Cycles 2810 ** <1> 1 LCLKDIS KEN Disable Always 2811 ** <2> 1 KFLUSH Cache Flush 2812 ** <4> 1 LSTIOLTCHEN Last I/O Latch Enable 2813 ** <6> 1 VLMSTLDOFF Lead-off Wait-State for VL-Master Cycle 2814 ** <13> 1 ENRDYN Generate RDY# at the End of a Burst Cycle 2815 ** <14> 1 LMABLOCK Local Memory Access at A0000-BFFFFH Lock 2816 ** <15> 1 SHDWRLOCK Shadow RAM Write Lock 2817 ** 2818 ** <3><5><7:12> Reserved 2819 */ 2820 #define SR_SYSMCR2_REG 0x104 2821 #define SR_SYSMCR2_INIT ( SYSMCR2_M_SMIHLDOFRST | SYSMCR2_M_VLMSTLDOFF \ 2822 SYSMCR2_M_ENRDYN ) 2823 #define SYSMCR2_V_SMIHLDOFRST 0 2824 #define SYSMCR2_M_SMIHLDOFRST (1 << SYSMCR2_V_SMIHLDOFRST) 2825 #define SYSMCR2_V_LCLKDIS 1 2826 #define SYSMCR2_M_LCLKDIS (1 << SYSMCR2_V_LCLKDIS) 2827 #define SYSMCR2_V_KFLUSH 2 2828 #define SYSMCR2_M_KFLUSH (1 << SYSMCR2_V_KFLUSH) 2829 #define SYSMCR2_V_LSTIOLTCHEN 4 2830 #define SYSMCR2_M_LSTIOLTCHEN (1 << SYSMCR2_V_LSTIOLTCHEN) 2831 #define SYSMCR2_V_VLMSTLDOFF 6 2832 #define SYSMCR2_M_VLMSTLDOFF (1 << SYSMCR2_V_VLMSTLDOFF) 2833 #define SYSMCR2_V_ENRDYN 13 2834 #define SYSMCR2_M_ENRDYN (1 << SYSMCR2_V_ENRDYN) 2835 #define SYSMCR2_V_LMABLOCK 14 2836 #define SYSMCR2_M_LMABLOCK (1 << SYSMCR2_V_LMABLOCK) 2837 #define SYSMCR2_V_SHDWRLOCK 15 2838 #define SYSMCR2_M_SHDWRLOCK (1 << SYSMCR2_V_SHDWRLOCK) 2839 2840 /* 2841 ** 2842 ** Parity Address Register 1 (PARADR1) - Index 0x105 2843 ** 2844 ** Loc Size Name Function 2845 ** ----- ---- ---- --------------------------------- 2846 ** <2> 14 PARADR Parity Error Address 2847 ** 2848 ** <0:1> Reserved 2849 */ 2850 #define SR_PARADR1_REG 0x105 2851 #define PARADR1_V_PARADR 2 2852 #define PARADR1_M_PARADR (0xFFFC << PARADR1_V_PARADR) 2853 2854 /* 2855 ** 2856 ** Parity Address Register 2 (PARADR2) - Index 0x106 2857 ** 2858 ** Loc Size Name Function 2859 ** ----- ---- ---- --------------------------------- 2860 ** <0> 12 PARADR Parity Error Address 2861 ** <12> 1 PARBE0 Byte Enables for Parity Error Address 0 2862 ** <13> 1 PARBE1 Byte Enables for Parity Error Address 1 2863 ** <14> 1 PARBE2 Byte Enables for Parity Error Address 2 2864 ** <15> 1 PARBE3 Byte Enables for Parity Error Address 3 2865 ** 2866 */ 2867 #define SR_PARADR2_REG 0x106 2868 #define PARADR2_V_PARADR 0 2869 #define PARADR2_M_PARADR (0xFFF << PARADR2_V_PARADR) 2870 #define PARADR2_V_PARBE 12 2871 #define PARADR2_M_PARBE (0xF << PARADR2_V_PARBE) 2872 #define PARADR2_V_PARBE0 12 2873 #define PARADR2_M_PARBE0 (1 << PARADR2_V_PARBE0) 2874 #define PARADR2_V_PARBE1 13 2875 #define PARADR2_M_PARBE1 (1 << PARADR2_V_PARBE1) 2876 #define PARADR2_V_PARBE2 14 2877 #define PARADR2_M_PARBE2 (1 << PARADR2_V_PARBE2) 2878 #define PARADR2_V_PARBE3 15 2879 #define PARADR2_M_PARBE3 (1 << PARADR2_V_PARBE3) 2880 2881 /* 2882 ** SEQUOIA-1 Pin Function Select Registers 2883 ** 2884 */ 2885 2886 /* 2887 ** 2888 ** SEQUOIA-1 Pin Select Register 1 (SEQPSR1) - Index 0x110 2889 ** 2890 ** Loc Size Name Function 2891 ** ----- ---- ---- --------------------------------- 2892 ** <0> 1 NPWRGDDBDIS Negative PWRGD Edge Debounce Disable 2893 ** <1> 1 PORT92DIS Port 92 Disable 2894 ** <2> 1 TAGCSSEL TAGCS# Select 2895 ** <3> 1 LOCKPINSEL LOCK# Pin Select 2896 ** <4> 1 CCSPINEN CCS Pin Enable # 2897 ** <5> 1 TAGDEN TAG RAM Data Enable # 2898 ** <8> 1 GPIOC0PINEN GPIOC0 Pin Enable 2899 ** <10> 1 HTRGOUTEN Heat Regulator Output Enable 2900 ** <11> 1 GPIOA0PINEN GPIOA0 Pin Enable 2901 ** 2902 ** <6:7><9><12:15> Reserved 2903 */ 2904 #define SEQR_SEQPSR1_REG 0x110 2905 #define SEQR_SEQPSR1_INIT ( SEQPSR1_M_PORT92DIS | SEQPSR1_M_CCSPINEN | \ 2906 SEQPSR1_M_TAGDEN) 2907 #define SEQPSR1_V_NPWRGDDBDIS 0 2908 #define SEQPSR1_M_NPWRGDDBDIS (1 << SEQPSR1_V_NPWRGDDBDIS) 2909 #define SEQPSR1_V_PORT92DIS 1 2910 #define SEQPSR1_M_PORT92DIS (1 << SEQPSR1_V_PORT92DIS) 2911 #define SEQPSR1_V_TAGCSSEL 2 2912 #define SEQPSR1_M_TAGCSSEL (1 << SEQPSR1_V_TAGCSSEL) 2913 #define SEQPSR1_V_LOCKPINSEL 3 2914 #define SEQPSR1_M_LOCKPINSEL (1 << SEQPSR1_V_LOCKPINSEL) 2915 #define SEQPSR1_V_CCSPINEN 4 2916 #define SEQPSR1_M_CCSPINEN (1 << SEQPSR1_V_CCSPINEN) 2917 #define SEQPSR1_V_TAGDEN 5 2918 #define SEQPSR1_M_TAGDEN (1 << SEQPSR1_V_TAGDEN) 2919 #define SEQPSR1_V_GPIOC0PINEN 8 2920 #define SEQPSR1_M_GPIOC0PINEN (1 << SEQPSR1_V_GPIOC0PINEN) 2921 #define SEQPSR1_V_HTRGOUTEN 10 2922 #define SEQPSR1_M_HTRGOUTEN (1 << SEQPSR1_V_HTRGOUTEN) 2923 #define SEQPSR1_V_GPIOA0PINEN 11 2924 #define SEQPSR1_M_GPIOA0PINEN (1 << SEQPSR1_V_GPIOA0PINEN) 2925 2926 /* 2927 ** 2928 ** SEQUOIA-1 Pin Select Register 2 (SEQPSR2) - Index 0x111 2929 ** 2930 ** Loc Size Name Function 2931 ** ----- ---- ---- --------------------------------- 2932 ** <0> 1 OPGPEXTEN Optional GPEXT Enable 2933 ** <2> 1 EXTACT3PINEN EXTACT3 Pin Enable 2934 ** <3> 1 NMIPINEN NMI Pin Enable 2935 ** <4> 1 DIRTYPINEN DIRTY Pin Enable # 2936 ** <5> 1 GPIOB0PINEN GPIOB0 Pin Enable 2937 ** <6> 1 DRTWEPINEN DRTWE# Pin Enable # 2938 ** <7> 1 GPIOB1PINEN GPIOB1 Pin Enable 2939 ** <8> 1 KBRSTPINEN KB reset Pin Enable 2940 ** <11> 1 GPIOC1PINEN GPIOC1 Pin Enable 2941 ** <12> 1 GPIO0PINEN GPIO0 Pin Enable # 2942 ** <13> 1 GPIO1PINEN GPIO1 Pin Enable # 2943 ** <14> 1 GPIO2PINEN GPIO2 Pin Enable # 2944 ** <15> 1 GPIO3PINEN GPIO3 Pin Enable # 2945 ** 2946 ** <1><9:10> Reserved 2947 */ 2948 #define SEQR_SEQPSR2_REG 0x111 2949 #define SEQR_SEQPSR2_INIT ( SEQPSR2_M_NMIPINEN | SEQPSR2_M_DIRTYPINEN |\ 2950 SEQPSR2_M_GPIOB0PINEN | SEQPSR2_M_DRTWEPINEN |\ 2951 SEQPSR2_M_GPIOB1PINEN | SEQPSR2_M_KBRSTPINEN |\ 2952 SEQPSR2_M_BIT9 | SEQPSR2_M_BIT10 |\ 2953 SEQPSR2_M_GPIOC1PINEN ) 2954 #define SEQPSR2_V_OPGPEXTEN 0 2955 #define SEQPSR2_M_OPGPEXTEN (1 << SEQPSR2_V_OPGPEXTEN) 2956 #define SEQPSR2_V_EXTACT3PINEN 2 2957 #define SEQPSR2_M_EXTACT3PINEN (1 << SEQPSR2_V_EXTACT3PINEN) 2958 #define SEQPSR2_V_NMIPINEN 3 2959 #define SEQPSR2_M_NMIPINEN (1 << SEQPSR2_V_NMIPINEN) 2960 #define SEQPSR2_V_DIRTYPINEN 4 2961 #define SEQPSR2_M_DIRTYPINEN (1 << SEQPSR2_V_DIRTYPINEN) 2962 #define SEQPSR2_V_GPIOB0PINEN 5 2963 #define SEQPSR2_M_GPIOB0PINEN (1 << SEQPSR2_V_GPIOB0PINEN) 2964 #define SEQPSR2_V_DRTWEPINEN 6 2965 #define SEQPSR2_M_DRTWEPINEN (1 << SEQPSR2_V_DRTWEPINEN) 2966 #define SEQPSR2_V_GPIOB1PINEN 7 2967 #define SEQPSR2_M_GPIOB1PINEN (1 << SEQPSR2_V_GPIOB1PINEN) 2968 #define SEQPSR2_V_KBRSTPINEN 8 2969 #define SEQPSR2_M_KBRSTPINEN (1 << SEQPSR2_V_KBRSTPINEN) 2970 #define SEQPSR2_V_BIT9 9 2971 #define SEQPSR2_M_BIT9 (1 << SEQPSR2_V_BIT9) 2972 #define SEQPSR2_V_BIT10 10 2973 #define SEQPSR2_M_BIT10 (1 << SEQPSR2_V_BIT10) 2974 #define SEQPSR2_V_GPIOC1PINEN 11 2975 #define SEQPSR2_M_GPIOC1PINEN (1 << SEQPSR2_V_GPIOC1PINEN) 2976 #define SEQPSR2_V_GPIO0PINEN 12 2977 #define SEQPSR2_M_GPIO0PINEN (1 << SEQPSR2_V_GPIO0PINEN) 2978 #define SEQPSR2_V_GPIO1PINEN 13 2979 #define SEQPSR2_M_GPIO1PINEN (1 << SEQPSR2_V_GPIO1PINEN) 2980 #define SEQPSR2_V_GPIO2PINEN 14 2981 #define SEQPSR2_M_GPIO2PINEN (1 << SEQPSR2_V_GPIO2PINEN) 2982 #define SEQPSR2_V_GPIO3PINEN 15 2983 #define SEQPSR2_M_GPIO3PINEN (1 << SEQPSR2_V_GPIO3PINEN) 2984 2985 /* 2986 ** 2987 ** SEQUOIA-1 Pin Select Register 3 (SEQPSR3) - Index 0x112 2988 ** 2989 ** Loc Size Name Function 2990 ** ----- ---- ---- --------------------------------- 2991 ** <0> 1 PC0PINEN PC0 Pin Enable # 2992 ** <2> 1 PC2PINEN PC2 Pin Enable # 2993 ** <3> 1 PC3PINEN PC3 Pin Enable # 2994 ** <4> 1 PC4PINEN PC4 Pin Enable # 2995 ** <5> 1 PC5PINEN PC5 Pin Enable # 2996 ** <6> 1 PC6PINEN PC6 Pin Enable # 2997 ** <7> 1 PC7PINEN PC7 Pin Enable # 2998 ** <8> 1 PC8PINEN PC8 Pin Enable # 2999 ** <9> 1 PC9PINEN PC9 Pin Enable # 3000 ** <12> 1 EXTACT0PINEN EXTACT0 Pin Enable 3001 ** <15> 1 EXTACT1PINEN EXTACT1 Pin Enable 3002 ** 3003 ** <1><10:11><13:14> Reserved 3004 */ 3005 #define SEQR_SEQPSR3_REG 0x112 3006 #define SEQR_SEQPSR3_INIT ( SEQPSR3_M_PC2PINEN | SEQPSR3_M_PC3PINEN | \ 3007 SEQPSR3_M_PC4PINEN | SEQPSR3_M_PC5PINEN | \ 3008 SEQPSR3_M_PC6PINEN | SEQPSR3_M_PC7PINEN | \ 3009 SEQPSR3_M_PC8PINEN | SEQPSR3_M_PC9PINEN ) 3010 #define SEQPSR3_V_PC0PINEN 0 3011 #define SEQPSR3_M_PC0PINEN (1U << SEQPSR3_V_PC0PINEN) 3012 #define SEQPSR3_V_PC2PINEN 2 3013 #define SEQPSR3_M_PC2PINEN (1U << SEQPSR3_V_PC2PINEN) 3014 #define SEQPSR3_V_PC3PINEN 3 3015 #define SEQPSR3_M_PC3PINEN (1U << SEQPSR3_V_PC3PINEN) 3016 #define SEQPSR3_V_PC4PINEN 4 3017 #define SEQPSR3_M_PC4PINEN (1U << SEQPSR3_V_PC4PINEN) 3018 #define SEQPSR3_V_PC5PINEN 5 3019 #define SEQPSR3_M_PC5PINEN (1U << SEQPSR3_V_PC5PINEN) 3020 #define SEQPSR3_V_PC6PINEN 6 3021 #define SEQPSR3_M_PC6PINEN (1U << SEQPSR3_V_PC6PINEN) 3022 #define SEQPSR3_V_PC7PINEN 7 3023 #define SEQPSR3_M_PC7PINEN (1U << SEQPSR3_V_PC7PINEN) 3024 #define SEQPSR3_V_PC8PINEN 8 3025 #define SEQPSR3_M_PC8PINEN (1U << SEQPSR3_V_PC8PINEN) 3026 #define SEQPSR3_V_PC9PINEN 9 3027 #define SEQPSR3_M_PC9PINEN (1U << SEQPSR3_V_PC9PINEN) 3028 #define SEQPSR3_V_EXTACT0PINEN 12 3029 #define SEQPSR3_M_EXTACT0PINEN (1U << SEQPSR3_V_EXTACT0PINEN) 3030 #define SEQPSR3_V_EXTACT1PINEN 15 3031 #define SEQPSR3_M_EXTACT1PINEN (1U << SEQPSR3_V_EXTACT1PINEN) 3032 3033 /* 3034 ** 3035 ** Modular Clock Control Register (MODCLKCR) - Index 0x118 3036 ** 3037 ** Loc Size Name Function 3038 ** ----- ---- ---- --------------------------------- 3039 ** <1> 1 VLCLKSTPEN VL Clock Stop Enable 3040 ** <5> 1 ADSMDIS ADS Mask Disable 3041 ** <8> 1 MDCHGIMD Mode Change Immediate 3042 ** <11> 1 SLWATCKEN SLOW AT Clock Enable 3043 ** 3044 ** <0><2:4><6:7><9:10><12:15> Reserved 3045 */ 3046 #define SEQR_MODCLKCR_REG 0x118 3047 #define SEQR_MODCLKCR_INIT MODCLKCR_M_VLCLKSTPEN 3048 #define MODCLKCR_V_VLCLKSTPEN 1 3049 #define MODCLKCR_M_VLCLKSTPEN (1 << MODCLKCR_V_VLCLKSTPEN) 3050 #define MODCLKCR_V_ADSMDIS 5 3051 #define MODCLKCR_M_ADSMDIS (1 << MODCLKCR_V_ADSMDIS) 3052 #define MODCLKCR_V_MDCHGIMD 8 3053 #define MODCLKCR_M_MDCHGIMD (1 << MODCLKCR_V_MDCHGIMD) 3054 #define MODCLKCR_V_SLWATCKEN 11 3055 #define MODCLKCR_M_SLWWATCKEN (1 << MODCLKCR_V_SLWATCKEN) 3056 3057 /* 3058 ** 3059 ** Burst Bus Control Register (BBUSCR) - Index 0x180 3060 ** 3061 ** Loc Size Name Function 3062 ** ----- ---- ---- --------------------------------- 3063 ** <3> 1 SQ1GIDEEN SEQUOIA-1 Global Turbo IDE Enable 3064 ** <5> 1 RSTREADSEN Restart EADS Enable 3065 ** <15> 1 SECIDEN Secondary IDE Drive Enable 3066 ** 3067 ** <0:2><4><6:14> Reserved 3068 */ 3069 #define SEQR_BBUSCR_REG 0x180 3070 #define BBUSCR_V_SQ1GIDEEN 3 3071 #define BBUSCR_M_SQ1GIDEEN (1 << BBUSCR_V_SQ1GIDEEN) 3072 #define BBUSCR_V_RSTREADSEN 5 3073 #define BBUSCR_M_RSTREADSEN (1 << BBUSCR_V_RSTREADSEN) 3074 #define BBUSCR_V_SECIDEN 15 3075 #define BBUSCR_M_SECIDEN (1 << BBUSCR_V_SECIDEN) 3076 3077 /* 3078 ** DRAM Control Registers 3079 ** 3080 */ 3081 3082 /* 3083 ** 3084 ** Shadow RAM Read Enable Control Register (SRAMRDENCR) - Index 0x200 3085 ** 3086 ** Loc Size Name Function 3087 ** ----- ---- ---- --------------------------------- 3088 ** <0> 1 LMEMRDEN0 Local Memory C0000H-C3FFFH Read Enable 3089 ** <1> 1 LMEMRDEN1 Local Memory C4000H-C7FFFH Read Enable 3090 ** <2> 1 LMEMRDEN2 Local Memory C8000H-CBFFFH Read Enable 3091 ** <3> 1 LMEMRDEN3 Local Memory CC000H-CFFFFH Read Enable 3092 ** <4> 1 LMEMRDEN4 Local Memory D0000H-D3FFFH Read Enable 3093 ** <5> 1 LMEMRDEN5 Local Memory D4000H-D7FFFH Read Enable 3094 ** <6> 1 LMEMRDEN6 Local Memory D8000H-DBFFFH Read Enable 3095 ** <7> 1 LMEMRDEN7 Local Memory DC000H-DFFFFH Read Enable 3096 ** <8> 1 LMEMRDEN8 Local Memory E0000H-E3FFFH Read Enable 3097 ** <9> 1 LMEMRDEN9 Local Memory E4000H-E7FFFH Read Enable 3098 ** <10> 1 LMEMRDEN10 Local Memory E8000H-EBFFFH Read Enable 3099 ** <11> 1 LMEMRDEN11 Local Memory EC000H-EFFFFH Read Enable 3100 ** <12> 1 LMEMRDEN12 Local Memory F0000H-FFFFFH Read Enable 3101 ** 3102 ** <13:15> Reserved 3103 */ 3104 #define DRAMCR_SRAMRDENCR_REG 0x200 3105 #define DRAMCR_SRAMRDENCR_INIT 0x0000 3106 #define SRAMRDENCR_V_LMEMRDEN0 0 3107 #define SRAMRDENCR_M_LMEMRDEN0 (1 << SRAMRDENCR_V_LMEMRDEN0) 3108 #define SRAMRDENCR_V_LMEMRDEN1 1 3109 #define SRAMRDENCR_M_LMEMRDEN1 (1 << SRAMRDENCR_V_LMEMRDEN1) 3110 #define SRAMRDENCR_V_LMEMRDEN2 2 3111 #define SRAMRDENCR_M_LMEMRDEN2 (1 << SRAMRDENCR_V_LMEMRDEN2) 3112 #define SRAMRDENCR_V_LMEMRDEN3 3 3113 #define SRAMRDENCR_M_LMEMRDEN3 (1 << SRAMRDENCR_V_LMEMRDEN3) 3114 #define SRAMRDENCR_V_LMEMRDEN4 4 3115 #define SRAMRDENCR_M_LMEMRDEN4 (1 << SRAMRDENCR_V_LMEMRDEN4) 3116 #define SRAMRDENCR_V_LMEMRDEN5 5 3117 #define SRAMRDENCR_M_LMEMRDEN5 (1 << SRAMRDENCR_V_LMEMRDEN5) 3118 #define SRAMRDENCR_V_LMEMRDEN6 6 3119 #define SRAMRDENCR_M_LMEMRDEN6 (1 << SRAMRDENCR_V_LMEMRDEN6) 3120 #define SRAMRDENCR_V_LMEMRDEN7 7 3121 #define SRAMRDENCR_M_LMEMRDEN7 (1 << SRAMRDENCR_V_LMEMRDEN7) 3122 #define SRAMRDENCR_V_LMEMRDEN8 8 3123 #define SRAMRDENCR_M_LMEMRDEN8 (1 << SRAMRDENCR_V_LMEMRDEN8) 3124 #define SRAMRDENCR_V_LMEMRDEN9 9 3125 #define SRAMRDENCR_M_LMEMRDEN9 (1 << SRAMRDENCR_V_LMEMRDEN9) 3126 #define SRAMRDENCR_V_LMEMRDEN10 10 3127 #define SRAMRDENCR_M_LMEMRDEN10 (1 << SRAMRDENCR_V_LMEMRDEN10) 3128 #define SRAMRDENCR_V_LMEMRDEN11 11 3129 #define SRAMRDENCR_M_LMEMRDEN11 (1 << SRAMRDENCR_V_LMEMRDEN11) 3130 #define SRAMRDENCR_V_LMEMRDEN12 12 3131 #define SRAMRDENCR_M_LMEMRDEN12 (1 << SRAMRDENCR_V_LMEMRDEN12) 3132 3133 /* 3134 ** 3135 ** Shadow RAM Write Enable Control Register (SRAMWRENCR) - Index 0x201 3136 ** 3137 ** Loc Size Name Function 3138 ** ----- ---- ---- --------------------------------- 3139 ** <0> 1 LMEMWREN0 Local Memory C0000H-C3FFFH Write Enable 3140 ** <1> 1 LMEMWREN1 Local Memory C4000H-C7FFFH Write Enable 3141 ** <2> 1 LMEMWREN2 Local Memory C8000H-CBFFFH Write Enable 3142 ** <3> 1 LMEMWREN3 Local Memory CC000H-CFFFFH Write Enable 3143 ** <4> 1 LMEMWREN4 Local Memory D0000H-D3FFFH Write Enable 3144 ** <5> 1 LMEMWREN5 Local Memory D4000H-D7FFFH Write Enable 3145 ** <6> 1 LMEMWREN6 Local Memory D8000H-DBFFFH Write Enable 3146 ** <7> 1 LMEMWREN7 Local Memory DC000H-DFFFFH Write Enable 3147 ** <8> 1 LMEMWREN8 Local Memory E0000H-E3FFFH Write Enable 3148 ** <9> 1 LMEMWREN9 Local Memory E4000H-E7FFFH Write Enable 3149 ** <10> 1 LMEMWREN10 Local Memory E8000H-EBFFFH Write Enable 3150 ** <11> 1 LMEMWREN11 Local Memory EC000H-EFFFFH Write Enable 3151 ** <12> 1 LMEMWREN12 Local Memory F0000H-FFFFFH Write Enable 3152 ** 3153 ** <13:15> Reserved 3154 */ 3155 #define DRAMCR_SRAMWRENCR_REG 0x201 3156 #define DRAMCR_SRAMWRENCR_INIT 0x0000 3157 #define SRAMWRENCR_V_LMEMWREN0 0 3158 #define SRAMWRENCR_M_LMEMWREN0 (1 << SRAMWRENCR_V_LMEMWREN0) 3159 #define SRAMWRENCR_V_LMEMWREN1 1 3160 #define SRAMWRENCR_M_LMEMWREN1 (1 << SRAMWRENCR_V_LMEMWREN1) 3161 #define SRAMWRENCR_V_LMEMWREN2 2 3162 #define SRAMWRENCR_M_LMEMWREN2 (1 << SRAMWRENCR_V_LMEMWREN2) 3163 #define SRAMWRENCR_V_LMEMWREN3 3 3164 #define SRAMWRENCR_M_LMEMWREN3 (1 << SRAMWRENCR_V_LMEMWREN3) 3165 #define SRAMWRENCR_V_LMEMWREN4 4 3166 #define SRAMWRENCR_M_LMEMWREN4 (1 << SRAMWRENCR_V_LMEMWREN4) 3167 #define SRAMWRENCR_V_LMEMWREN5 5 3168 #define SRAMWRENCR_M_LMEMWREN5 (1 << SRAMWRENCR_V_LMEMWREN5) 3169 #define SRAMWRENCR_V_LMEMWREN6 6 3170 #define SRAMWRENCR_M_LMEMWREN6 (1 << SRAMWRENCR_V_LMEMWREN6) 3171 #define SRAMWRENCR_V_LMEMWREN7 7 3172 #define SRAMWRENCR_M_LMEMWREN7 (1 << SRAMWRENCR_V_LMEMWREN7) 3173 #define SRAMWRENCR_V_LMEMWREN8 8 3174 #define SRAMWRENCR_M_LMEMWREN8 (1 << SRAMWRENCR_V_LMEMWREN8) 3175 #define SRAMWRENCR_V_LMEMWREN9 9 3176 #define SRAMWRENCR_M_LMEMWREN9 (1 << SRAMWRENCR_V_LMEMWREN9) 3177 #define SRAMWRENCR_V_LMEMWREN10 10 3178 #define SRAMWRENCR_M_LMEMWREN10 (1 << SRAMWRENCR_V_LMEMWREN10) 3179 #define SRAMWRENCR_V_LMEMWREN11 11 3180 #define SRAMWRENCR_M_LMEMWREN11 (1 << SRAMWRENCR_V_LMEMWREN11) 3181 #define SRAMWRENCR_V_LMEMWREN12 12 3182 #define SRAMWRENCR_M_LMEMWREN12 (1 << SRAMWRENCR_V_LMEMWREN12) 3183 3184 /* 3185 ** 3186 ** Bank 0 Control Register (BK0CR) - Index 0x202 3187 ** 3188 ** Loc Size Name Function 3189 ** ----- ---- ---- --------------------------------- 3190 ** <0> 8 B0A Bank 0 Starting Address 3191 ** <8> 1 B0S0 Bank 0 DRAM Size 0 3192 ** <9> 1 B0S1 Bank 0 DRAM Size 1 3193 ** <10> 1 B0S2 Bank 0 DRAM Size 2 3194 ** <11> 1 BANKEN0 Bank 0 Enable 3195 ** <12> 1 ENMDEN0N Enable MDEN# for Bank 0 3196 ** <13> 1 COLADR00 Number of Column Address Bits for Bank 0 0 3197 ** <14> 1 COLADR01 Number of Column Address Bits for Bank 0 1 3198 ** <15> 1 COLADR02 Number of Column Address Bits for Bank 0 2 3199 ** 3200 */ 3201 #define DRAMCR_BK0CR_REG 0x202 3202 #define DRAMCR_BK0CR_INIT 0x0000 3203 #define BK0CR_V_B0A 0 3204 #define BK0CR_M_B0A (0xFF << BK0CR_V_B0A) 3205 #define BK0CR_V_B0S 8 3206 #define BK0CR_M_B0S (0x7 << BK0CR_V_B0S) 3207 #define BK0CR_V_B0S0 8 3208 #define BK0CR_M_B0S0 (1 << BK0CR_V_B0S0) 3209 #define BK0CR_V_B0S1 9 3210 #define BK0CR_M_B0S1 (1 << BK0CR_V_B0S1) 3211 #define BK0CR_V_B0S2 10 3212 #define BK0CR_M_B0S2 (1 << BK0CR_V_B0S2) 3213 #define BK0CR_V_BANKEN0 11 3214 #define BK0CR_M_BANKEN0 (1 << BK0CR_V_BANKEN0) 3215 #define BK0CR_V_ENMDEN0N 12 3216 #define BK0CR_M_ENMDEN0N (1 << BK0CR_V_ENMDEN0N) 3217 #define BK0CR_V_COLADR0 13 3218 #define BK0CR_M_COLADR0 (0xE << BK0CR_V_COLADR0) 3219 #define BK0CR_V_COLADR00 13 3220 #define BK0CR_M_COLADR00 (1 << BK0CR_V_COLADR00) 3221 #define BK0CR_V_COLADR01 14 3222 #define BK0CR_M_COLADR01 (1 << BK0CR_V_COLADR01) 3223 #define BK0CR_V_COLADR02 15 3224 #define BK0CR_M_COLADR02 (1 << BK0CR_V_COLADR02) 3225 3226 /* 3227 ** Bank 0 DRAM Size 3228 */ 3229 #define B0S_256KB 0x000 3230 #define B0S_512KB BK0CR_M_B0S0 3231 #define B0S_1MB BK0CR_M_B0S1 3232 #define B0S_2MB (BK0CR_M_B0S0 | BK0CR_M_B0S1) 3233 #define B0S_4MB BK0CR_M_B0S2 3234 #define B0S_16MB (BK0CR_M_B0S1 | BK0CR_M_B0S2) 3235 3236 /* 3237 ** Bank 0 Column Address Bits 3238 */ 3239 #define COLADR0_8 0x000 3240 #define COLADR0_9 BK0CR_M_COLADR00 3241 #define COLADR0_10 BK0CR_M_COLADR01 3242 #define COLADR0_11 (BK0CR_M_COLADR00 | BK0CR_M_COLADR01) 3243 #define COLADR0_12 BK0CR_M_COLADR02 3244 3245 /* 3246 ** 3247 ** Bank 1 Control Register (BK1CR) - Index 0x203 3248 ** 3249 ** Loc Size Name Function 3250 ** ----- ---- ---- --------------------------------- 3251 ** <0> 8 B1A Bank 1 Starting Address 3252 ** <8> 1 B1S0 Bank 1 DRAM Size 0 3253 ** <9> 1 B1S1 Bank 1 DRAM Size 1 3254 ** <10> 1 B1S2 Bank 1 DRAM Size 2 3255 ** <11> 1 BANKEN1 Bank 1 Enable 3256 ** <12> 1 ENMDEN1N Enable MDEN# for Bank 1 3257 ** <13> 1 COLADR10 Number of Column Address Bits for Bank 1 0 3258 ** <14> 1 COLADR11 Number of Column Address Bits for Bank 1 1 3259 ** <15> 1 COLADR12 Number of Column Address Bits for Bank 1 2 3260 ** 3261 */ 3262 #define DRAMCR_BK1CR_REG 0x203 3263 #define DRAMCR_BK1CR_INIT 0x0000 3264 #define BK1CR_V_B1A 0 3265 #define BK1CR_M_B1A (0xFF << BK1CR_V_B1A) 3266 #define BK1CR_V_B1S 8 3267 #define BK1CR_M_B1S (0x7 << BK1CR_V_B1S) 3268 #define BK1CR_V_B1S0 8 3269 #define BK1CR_M_B1S0 (1 << BK1CR_V_B1S0) 3270 #define BK1CR_V_B1S1 9 3271 #define BK1CR_M_B1S1 (1 << BK1CR_V_B1S1) 3272 #define BK1CR_V_B1S2 10 3273 #define BK1CR_M_B1S2 (1 << BK1CR_V_B1S2) 3274 #define BK1CR_V_BANKEN1 11 3275 #define BK1CR_M_BANKEN1 (1 << BK1CR_V_BANKEN1) 3276 #define BK1CR_V_ENMDEN1N 12 3277 #define BK1CR_M_ENMDEN1N (1 << BK1CR_V_ENMDEN1N) 3278 #define BK1CR_V_COLADR1 13 3279 #define BK1CR_M_COLADR1 (0xE << BK1CR_V_COLADR1) 3280 #define BK1CR_V_COLADR10 13 3281 #define BK1CR_M_COLADR10 (1 << BK1CR_V_COLADR10) 3282 #define BK1CR_V_COLADR11 14 3283 #define BK1CR_M_COLADR11 (1 << BK1CR_V_COLADR11) 3284 #define BK1CR_V_COLADR12 15 3285 #define BK1CR_M_COLADR12 (1 << BK1CR_V_COLADR12) 3286 3287 /* 3288 ** Bank 1 DRAM Size 3289 */ 3290 #define B1S_256KB 0x000 3291 #define B1S_512KB BK1CR_M_B1S0 3292 #define B1S_1MB BK1CR_M_B1S1 3293 #define B1S_2MB (BK1CR_M_B1S0 | BK1CR_M_B1S1) 3294 #define B1S_4MB BK1CR_M_B1S2 3295 #define B1S_16MB (BK1CR_M_B1S1 | BK1CR_M_B1S2) 3296 3297 /* 3298 ** Bank 1 Column Address Bits 3299 */ 3300 #define COLADR1_8 0x000 3301 #define COLADR1_9 BK1CR_M_COLADR10 3302 #define COLADR1_10 BK1CR_M_COLADR11 3303 #define COLADR1_11 (BK1CR_M_COLADR10 | BK1CR_M_COLADR11) 3304 #define COLADR1_12 BK1CR_M_COLADR12 3305 3306 /* 3307 ** 3308 ** Bank 0/1 Timing Control Register (BK01TCR) - Index 0x204 3309 ** 3310 ** Loc Size Name Function 3311 ** ----- ---- ---- --------------------------------- 3312 ** <0> 1 B01WRCPW0 Bank 0/1 Write CAS Cycle Time 0 3313 ** <1> 1 B01WRCPW1 Bank 0/1 Write CAS Cycle Time 1 3314 ** <2> 1 MA01WRDLY Bank 0/1 Write MA Delay 3315 ** <3> 1 B01RDCPW0 Bank 0/1 Read CAS Cycle Time 0 3316 ** <4> 1 B01RDCPW1 Bank 0/1 Read CAS Cycle Time 1 3317 ** <5> 1 MA01RDDLY Bank 0/1 Read MA Delay 3318 ** <6> 1 B01CPRE Bank 0/1 CAS Precharge 3319 ** <7> 1 B01RTMA Bank 0/1 RAS to CAS Delay 3320 ** <8> 1 B01MATC Bank 0/1 MA to CAS Delay 3321 ** <9> 1 B01RPRE0 Bank 0/1 RAS Precharge Time 0 3322 ** <10> 1 B01RPRE1 Bank 0/1 RAS Precharge Time 1 3323 ** <11> 1 B01RPRE2 Bank 0/1 RAS Precharge Time 2 3324 ** <12> 1 B01ILAVDT Bank 0/1 Interleave Avoid Time 3325 ** <13> 1 BNK01_ITL Bank 0/1 Interleave Enable 3326 ** 3327 ** <14:15> Reserved 3328 */ 3329 #define DRAMCR_BK01TCR_REG 0x204 3330 #define DRAMCR_BK01TCR_INIT ( BK01TCR_M_B01WRCPW | BK01TCR_M_MA01WRDLY | \ 3331 BK01TCR_M_B01RDCPW | BK01TCR_M_MA01RDDLY | \ 3332 BK01TCR_M_B01CPRE | BK01TCR_M_B01RTMA | \ 3333 BK01TCR_M_B01MATC | BK01TCR_M_B01RPRE | \ 3334 BK01TCR_M_B01ILAVDT ) 3335 #define BK01TCR_V_B01WRCPW 0 3336 #define BK01TCR_M_B01WRCPW (0x3 << BK01TCR_V_B01WRCPW) 3337 #define BK01TCR_V_B01WRCPW0 0 3338 #define BK01TCR_M_B01WRCPW0 (1 << BK01TCR_V_B01WRCPW0) 3339 #define BK01TCR_V_B01WRCPW1 1 3340 #define BK01TCR_M_B01WRCPW1 (1 << BK01TCR_V_B01WRCPW1) 3341 #define BK01TCR_V_MA01WRDLY 2 3342 #define BK01TCR_M_MA01WRDLY (1 << BK01TCR_V_MA01WRDLY) 3343 #define BK01TCR_V_B01RDCPW 3 3344 #define BK01TCR_M_B01RDCPW (0x3 << BK01TCR_V_B01RDCPW) 3345 #define BK01TCR_V_B01RDCPW0 3 3346 #define BK01TCR_M_B01RDCPW0 (1 << BK01TCR_V_B01RDCPW0) 3347 #define BK01TCR_V_B01RDCPW1 4 3348 #define BK01TCR_M_B01RDCPW1 (1 << BK01TCR_V_B01RDCPW1) 3349 #define BK01TCR_V_MA01RDDLY 5 3350 #define BK01TCR_M_MA01RDDLY (1 << BK01TCR_V_MA01RDDLY) 3351 #define BK01TCR_V_B01CPRE 6 3352 #define BK01TCR_M_B01CPRE (1 << BK01TCR_V_B01CPRE) 3353 #define BK01TCR_V_B01RTMA 7 3354 #define BK01TCR_M_B01RTMA (1 << BK01TCR_V_B01RTMA) 3355 #define BK01TCR_V_B01MATC 8 3356 #define BK01TCR_M_B01MATC (1 << BK01TCR_V_B01MATC) 3357 #define BK01TCR_V_B01RPRE 9 3358 #define BK01TCR_M_B01RPRE (0x7 << BK01TCR_V_B01RPRE) 3359 #define BK01TCR_V_B01RPRE0 9 3360 #define BK01TCR_M_B01RPRE0 (1 << BK01TCR_V_B01RPRE0) 3361 #define BK01TCR_V_B01RPRE1 10 3362 #define BK01TCR_M_B01RPRE1 (1 << BK01TCR_V_B01RPRE1) 3363 #define BK01TCR_V_B01RPRE2 11 3364 #define BK01TCR_M_B01RPRE2 (1 << BK01TCR_V_B01RPRE2) 3365 #define BK01TCR_V_B01ILAVDT 12 3366 #define BK01TCR_M_B01ILAVDT (1 << BK01TCR_V_B01ILAVDT) 3367 #define BK01TCR_V_BNK01_ITL 13 3368 #define BK01TCR_M_BNK01_ITL (1 << BK01TCR_V_BNK01_ITL) 3369 3370 /* 3371 ** Bank 0/1 Write CAS Cycle Time 3372 */ 3373 #define B01WRCPW_1T BK01TCR_M_B01WRCPW0 3374 #define B01WRCPW_2T BK01TCR_M_B01WRCPW1 3375 #define B01WRCPW_3T (BK01TCR_M_B01WRCPW0 | BK01TCR_M_B01WRCPW1) 3376 3377 /* 3378 ** Bank 0/1 Read CAS Cycle Time 3379 */ 3380 #define B01RDCPW_1T 0x000 3381 #define B01RDCPW_2T BK01TCR_M_B01WRCPW0 3382 #define B01RDCPW_3T BK01TCR_M_B01WRCPW1 3383 #define B01RDCPW_4T (BK01TCR_M_B01WRCPW0 | BK01TCR_M_B01WRCPW1) 3384 3385 /* 3386 ** Bank 0/1 RAS Precharge Time 3387 */ 3388 #define B01RPRE_1PT5T BK01TCR_M_B01RPRE1 3389 #define B01RPRE_2T (BK01TCR_M_B01RPRE0 | BK01TCR_M_B01RPRE1) 3390 #define B01RPRE_2PT5T BK01TCR_M_B01RPRE2 3391 #define B01RPRE_3T (BK01TCR_M_B01RPRE0 | BK01TCR_M_B01RPRE2) 3392 #define B01RPRE_3PT5T (BK01TCR_M_B01RPRE1 | BK01TCR_M_B01RPRE2) 3393 #define B01RPRE_4T (BK01TCR_M_B01RPRE0 | BK01TCR_M_B01RPRE1 | BK01TCR_M_B01RPRE2) 3394 3395 /* 3396 ** 3397 ** Bank 2 Control Register (BK2CR) - Index 0x205 3398 ** 3399 ** Loc Size Name Function 3400 ** ----- ---- ---- --------------------------------- 3401 ** <0> 8 B2A Bank 2 Starting Address 3402 ** <8> 1 B2S0 Bank 2 DRAM Size 0 3403 ** <9> 1 B2S1 Bank 2 DRAM Size 1 3404 ** <10> 1 B2S2 Bank 2 DRAM Size 2 3405 ** <11> 1 BANKEN2 Bank 2 Enable 3406 ** <12> 1 ENMDEN2N Enable MDEN# for Bank 2 3407 ** <13> 1 COLADR20 Number of Column Address Bits for Bank 2 0 3408 ** <14> 1 COLADR21 Number of Column Address Bits for Bank 2 1 3409 ** <15> 1 COLADR22 Number of Column Address Bits for Bank 2 2 3410 ** 3411 */ 3412 #define DRAMCR_BK2CR_REG 0x205 3413 #define DRAMCR_BK2CR_INIT 0x0000 3414 #define BK2CR_V_B2A 0 3415 #define BK2CR_M_B2A (0xFF << BK2CR_V_B2A) 3416 #define BK2CR_V_B2S 8 3417 #define BK2CR_M_B2S (0x7 << BK2CR_V_B2S) 3418 #define BK2CR_V_B2S0 8 3419 #define BK2CR_M_B2S0 (1 << BK2CR_V_B2S0) 3420 #define BK2CR_V_B2S1 9 3421 #define BK2CR_M_B2S1 (1 << BK2CR_V_B2S1) 3422 #define BK2CR_V_B2S2 10 3423 #define BK2CR_M_B2S2 (1 << BK2CR_V_B2S2) 3424 #define BK2CR_V_BANKEN2 11 3425 #define BK2CR_M_BANKEN2 (1 << BK2CR_V_BANKEN2) 3426 #define BK2CR_V_ENMDEN2N 12 3427 #define BK2CR_M_ENMDEN2N (1 << BK2CR_V_ENMDEN2N) 3428 #define BK2CR_V_COLADR2 13 3429 #define BK2CR_M_COLADR2 (0xE << BK2CR_V_COLADR2) 3430 #define BK2CR_V_COLADR20 13 3431 #define BK2CR_M_COLADR20 (1 << BK2CR_V_COLADR20) 3432 #define BK2CR_V_COLADR21 14 3433 #define BK2CR_M_COLADR21 (1 << BK2CR_V_COLADR21) 3434 #define BK2CR_V_COLADR22 15 3435 #define BK2CR_M_COLADR22 (1 << BK2CR_V_COLADR22) 3436 3437 /* 3438 ** Bank 2 DRAM Size 3439 */ 3440 #define B2S_256KB 0x000 3441 #define B2S_512KB BK2CR_M_B2S0 3442 #define B2S_1MB BK2CR_M_B2S1 3443 #define B2S_2MB (BK2CR_M_B2S0 | BK2CR_M_B2S1) 3444 #define B2S_4MB BK2CR_M_B2S2 3445 #define B2S_16MB (BK2CR_M_B2S1 | BK2CR_M_B2S2) 3446 3447 /* 3448 ** Bank 2 Column Address Bits 3449 */ 3450 #define COLADR2_8 0x000 3451 #define COLADR2_9 BK2CR_M_COLADR20 3452 #define COLADR2_10 BK2CR_M_COLADR21 3453 #define COLADR2_11 (BK2CR_M_COLADR20 | BK2CR_M_COLADR21) 3454 #define COLADR2_12 BK2CR_M_COLADR22 3455 3456 /* 3457 ** 3458 ** Bank 3 Control Register (BK3CR) - Index 0x206 3459 ** 3460 ** Loc Size Name Function 3461 ** ----- ---- ---- --------------------------------- 3462 ** <0> 8 B3A Bank 3 Starting Address 3463 ** <8> 1 B3S0 Bank 3 DRAM Size 0 3464 ** <9> 1 B3S1 Bank 3 DRAM Size 1 3465 ** <10> 1 B3S2 Bank 3 DRAM Size 2 3466 ** <11> 1 BANKEN3 Bank 3 Enable 3467 ** <12> 1 ENMDEN3N Enable MDEN# for Bank 3 3468 ** <13> 1 COLADR30 Number of Column Address Bits for Bank 3 0 3469 ** <14> 1 COLADR31 Number of Column Address Bits for Bank 3 1 3470 ** <15> 1 COLADR32 Number of Column Address Bits for Bank 3 2 3471 ** 3472 */ 3473 #define DRAMCR_BK3CR_REG 0x206 3474 #define DRAMCR_BK3CR_INIT 0x0000 3475 #define BK3CR_V_B3A 0 3476 #define BK3CR_M_B3A (0xFF << BK3CR_V_B3A) 3477 #define BK3CR_V_B3S 8 3478 #define BK3CR_M_B3S (0x7 << BK3CR_V_B3S) 3479 #define BK3CR_V_B3S0 8 3480 #define BK3CR_M_B3S0 (1 << BK3CR_V_B3S0) 3481 #define BK3CR_V_B3S1 9 3482 #define BK3CR_M_B3S1 (1 << BK3CR_V_B3S1) 3483 #define BK3CR_V_B3S2 10 3484 #define BK3CR_M_B3S2 (1 << BK3CR_V_B3S2) 3485 #define BK3CR_V_BANKEN3 11 3486 #define BK3CR_M_BANKEN3 (1 << BK3CR_V_BANKEN3) 3487 #define BK3CR_V_ENMDEN3N 12 3488 #define BK3CR_M_ENMDEN3N (1 << BK3CR_V_ENMDEN3N) 3489 #define BK3CR_V_COLADR3 13 3490 #define BK3CR_M_COLADR3 (0xE << BK3CR_V_COLADR3) 3491 #define BK3CR_V_COLADR30 13 3492 #define BK3CR_M_COLADR30 (1 << BK3CR_V_COLADR30) 3493 #define BK3CR_V_COLADR31 14 3494 #define BK3CR_M_COLADR31 (1 << BK3CR_V_COLADR31) 3495 #define BK3CR_V_COLADR32 15 3496 #define BK3CR_M_COLADR32 (1 << BK3CR_V_COLADR32) 3497 3498 /* 3499 ** Bank 3 DRAM Size 3500 */ 3501 #define B3S_256KB 0x000 3502 #define B3S_512KB BK3CR_M_B3S0 3503 #define B3S_1MB BK3CR_M_B3S1 3504 #define B3S_2MB (BK3CR_M_B3S0 | BK3CR_M_B3S1) 3505 #define B3S_4MB BK3CR_M_B3S2 3506 #define B3S_16MB (BK3CR_M_B3S1 | BK3CR_M_B3S2) 3507 3508 /* 3509 ** Bank 3 Column Address Bits 3510 */ 3511 #define COLADR3_8 0x000 3512 #define COLADR3_9 BK3CR_M_COLADR30 3513 #define COLADR3_10 BK3CR_M_COLADR31 3514 #define COLADR3_11 (BK3CR_M_COLADR30 | BK3CR_M_COLADR31) 3515 #define COLADR3_12 BK3CR_M_COLADR32 3516 3517 /* 3518 ** 3519 ** Bank 2/3 Timing Control Register (BK23TCR) - Index 0x207 3520 ** 3521 ** Loc Size Name Function 3522 ** ----- ---- ---- --------------------------------- 3523 ** <0> 1 B23WRCPW0 Bank 2/3 Write CAS Cycle Time 0 3524 ** <1> 1 B23WRCPW1 Bank 2/3 Write CAS Cycle Time 1 3525 ** <2> 1 MA23WRDLY Bank 2/3 Write MA Delay 3526 ** <3> 1 B23RDCPW0 Bank 2/3 Read CAS Cycle Time 0 3527 ** <4> 1 B23RDCPW1 Bank 2/3 Read CAS Cycle Time 1 3528 ** <5> 1 MA23RDDLY Bank 2/3 Read MA Delay 3529 ** <6> 1 B23CPRE Bank 2/3 CAS Precharge 3530 ** <7> 1 B23RTMA Bank 2/3 RAS to CAS Delay 3531 ** <8> 1 B23MATC Bank 2/3 MA to CAS Delay 3532 ** <9> 1 B23RPRE0 Bank 2/3 RAS Precharge Time 0 3533 ** <10> 1 B23RPRE1 Bank 2/3 RAS Precharge Time 1 3534 ** <11> 1 B23RPRE2 Bank 2/3 RAS Precharge Time 2 3535 ** <13> 1 BNK23_ITL Bank 2/3 Interleave Enable 3536 ** 3537 ** <12><14:15> Reserved 3538 */ 3539 #define DRAMCR_BK23TCR_REG 0x207 3540 #define DRAMCR_BK23TCR_INIT ( BK23TCR_M_B23WRCPW | BK23TCR_M_MA23WRDLY | \ 3541 BK23TCR_M_B23RDCPW | BK23TCR_M_MA23RDDLY | \ 3542 BK23TCR_M_B23CPRE | BK23TCR_M_B23RTMA | \ 3543 BK23TCR_M_B23MATC | BK23TCR_M_B23RPRE ) 3544 #define BK23TCR_V_B23WRCPW 0 3545 #define BK23TCR_M_B23WRCPW (0x3 << BK23TCR_V_B23WRCPW) 3546 #define BK23TCR_V_B23WRCPW0 0 3547 #define BK23TCR_M_B23WRCPW0 (1 << BK23TCR_V_B23WRCPW0) 3548 #define BK23TCR_V_B23WRCPW1 1 3549 #define BK23TCR_M_B23WRCPW1 (1 << BK23TCR_V_B23WRCPW1) 3550 #define BK23TCR_V_MA23WRDLY 2 3551 #define BK23TCR_M_MA23WRDLY (1 << BK23TCR_V_MA23WRDLY) 3552 #define BK23TCR_V_B23RDCPW 3 3553 #define BK23TCR_M_B23RDCPW (0x3 << BK23TCR_V_B23RDCPW) 3554 #define BK23TCR_V_B23RDCPW0 3 3555 #define BK23TCR_M_B23RDCPW0 (1 << BK23TCR_V_B23RDCPW0) 3556 #define BK23TCR_V_B23RDCPW1 4 3557 #define BK23TCR_M_B23RDCPW1 (1 << BK23TCR_V_B23RDCPW1) 3558 #define BK23TCR_V_MA23RDDLY 5 3559 #define BK23TCR_M_MA23RDDLY (1 << BK23TCR_V_MA23RDDLY) 3560 #define BK23TCR_V_B23CPRE 6 3561 #define BK23TCR_M_B23CPRE (1 << BK23TCR_V_B23CPRE) 3562 #define BK23TCR_V_B23RTMA 7 3563 #define BK23TCR_M_B23RTMA (1 << BK23TCR_V_B23RTMA) 3564 #define BK23TCR_V_B23MATC 8 3565 #define BK23TCR_M_B23MATC (1 << BK23TCR_V_B23MATC) 3566 #define BK23TCR_V_B23RPRE 9 3567 #define BK23TCR_M_B23RPRE (0x7 << BK23TCR_V_B23RPRE) 3568 #define BK23TCR_V_B23RPRE0 9 3569 #define BK23TCR_M_B23RPRE0 (1 << BK23TCR_V_B23RPRE0) 3570 #define BK23TCR_V_B23RPRE1 10 3571 #define BK23TCR_M_B23RPRE1 (1 << BK23TCR_V_B23RPRE1) 3572 #define BK23TCR_V_B23RPRE2 11 3573 #define BK23TCR_M_B23RPRE2 (1 << BK23TCR_V_B23RPRE2) 3574 #define BK23TCR_V_BNK23_ITL 13 3575 #define BK23TCR_M_BNK23_ITL (1 << BK23TCR_V_BNK23_ITL) 3576 3577 /* 3578 ** Bank 2/3 Write CAS Cycle Time 3579 */ 3580 #define B23WRCPW_1T BK23TCR_M_B23WRCPW0 3581 #define B23WRCPW_2T BK23TCR_M_B23WRCPW1 3582 #define B23WRCPW_3T (BK23TCR_M_B23WRCPW0 | BK23TCR_M_B23WRCPW1) 3583 3584 /* 3585 ** Bank 2/3 Read CAS Cycle Time 3586 */ 3587 #define B23RDCPW_1T 0x000 3588 #define B23RDCPW_2T BK23TCR_M_B23RDCPW0 3589 #define B23RDCPW_3T BK23TCR_M_B23RDCPW1 3590 #define B23RDCPW_4T (BK23TCR_M_B23RDCPW0 | BK23TCR_M_B23RDCPW1) 3591 3592 /* 3593 ** Bank 2/3 RAS Precharge Time 3594 */ 3595 #define B23RPRE_1PT5T BK23TCR_M_B23RPRE1 3596 #define B23RPRE_2T (BK23TCR_M_B23RPRE0 | BK23TCR_M_B23RPRE1) 3597 #define B23RPRE_2PT5T BK23TCR_M_B23RPRE2 3598 #define B23RPRE_3T (BK23TCR_M_B23RPRE0 | BK23TCR_M_B23RPRE2) 3599 #define B23RPRE_3PT5T (BK23TCR_M_B23RPRE1 | BK23TCR_M_B23RPRE2) 3600 #define B23RPRE_4T (BK23TCR_M_B23RPRE0 | BK23TCR_M_B23RPRE1 | BK23TCR_M_B23RPRE2) 3601 3602 /* 3603 ** 3604 ** Bank 4 Control Register (BK4CR) - Index 0x208 3605 ** 3606 ** Loc Size Name Function 3607 ** ----- ---- ---- --------------------------------- 3608 ** <0> 8 B4A Bank 4 Starting Address 3609 ** <8> 1 B4S0 Bank 4 DRAM Size 0 3610 ** <9> 1 B4S1 Bank 4 DRAM Size 1 3611 ** <10> 1 B4S2 Bank 4 DRAM Size 2 3612 ** <11> 1 BANKEN4 Bank 4 Enable 3613 ** <12> 1 ENMDEN4N Enable MDEN# for Bank 4 3614 ** <13> 1 COLADR40 Number of Column Address Bits for Bank 4 0 3615 ** <14> 1 COLADR41 Number of Column Address Bits for Bank 4 1 3616 ** <15> 1 COLADR42 Number of Column Address Bits for Bank 4 2 3617 ** 3618 */ 3619 #define DRAMCR_BK4CR_REG 0x208 3620 #define DRAMCR_BK4CR_INIT 0x0000 3621 #define BK4CR_V_B4A 0 3622 #define BK4CR_M_B4A (0xFF << BK4CR_V_B4A) 3623 #define BK4CR_V_B4S 8 3624 #define BK4CR_M_B4S (0x7 << BK4CR_V_B4S) 3625 #define BK4CR_V_B4S0 8 3626 #define BK4CR_M_B4S0 (1 << BK4CR_V_B4S0) 3627 #define BK4CR_V_B4S1 9 3628 #define BK4CR_M_B4S1 (1 << BK4CR_V_B4S1) 3629 #define BK4CR_V_B4S2 10 3630 #define BK4CR_M_B4S2 (1 << BK4CR_V_B4S2) 3631 #define BK4CR_V_BANKEN4 11 3632 #define BK4CR_M_BANKEN4 (1 << BK4CR_V_BANKEN4) 3633 #define BK4CR_V_ENMDEN4N 12 3634 #define BK4CR_M_ENMDEN4N (1 << BK4CR_V_ENMDEN4N) 3635 #define BK4CR_V_COLADR4 13 3636 #define BK4CR_M_COLADR4 (0xE << BK4CR_V_COLADR4) 3637 #define BK4CR_V_COLADR40 13 3638 #define BK4CR_M_COLADR40 (1 << BK4CR_V_COLADR40) 3639 #define BK4CR_V_COLADR41 14 3640 #define BK4CR_M_COLADR41 (1 << BK4CR_V_COLADR41) 3641 #define BK4CR_V_COLADR42 15 3642 #define BK4CR_M_COLADR42 (1 << BK4CR_V_COLADR42) 3643 3644 /* 3645 ** Bank 4 DRAM Size 3646 */ 3647 #define B4S_256KB 0x000 3648 #define B4S_512KB BK4CR_M_B4S0 3649 #define B4S_1MB BK4CR_M_B4S1 3650 #define B4S_2MB (BK4CR_M_B4S0 | BK4CR_M_B4S1) 3651 #define B4S_4MB BK4CR_M_B4S2 3652 #define B4S_16MB (BK4CR_M_B4S1 | BK4CR_M_B4S2) 3653 3654 /* 3655 ** Bank 4 Column Address Bits 3656 */ 3657 #define COLADR4_8 0x000 3658 #define COLADR4_9 BK4CR_M_COLADR40 3659 #define COLADR4_10 BK4CR_M_COLADR41 3660 #define COLADR4_11 (BK4CR_M_COLADR40 | BK4CR_M_COLADR41) 3661 #define COLADR4_12 BK4CR_M_COLADR42 3662 3663 /* 3664 ** 3665 ** Bank 5 Control Register (BK5CR) - Index 0x209 3666 ** 3667 ** Loc Size Name Function 3668 ** ----- ---- ---- --------------------------------- 3669 ** <0> 8 B5A Bank 5 Starting Address 3670 ** <8> 1 B5S0 Bank 5 DRAM Size 0 3671 ** <9> 1 B5S1 Bank 5 DRAM Size 1 3672 ** <10> 1 B5S2 Bank 5 DRAM Size 2 3673 ** <11> 1 BANKEN5 Bank 5 Enable 3674 ** <12> 1 ENMDEN5N Enable MDEN# for Bank 5 3675 ** <13> 1 COLADR50 Number of Column Address Bits for Bank 5 0 3676 ** <14> 1 COLADR51 Number of Column Address Bits for Bank 5 1 3677 ** <15> 1 COLADR52 Number of Column Address Bits for Bank 5 2 3678 ** 3679 */ 3680 #define DRAMCR_BK5CR_REG 0x209 3681 #define DRAMCR_BK5CR_INIT 0x0000 3682 #define BK5CR_V_B5A 0 3683 #define BK5CR_M_B5A (0xFF << BK5CR_V_B5A) 3684 #define BK5CR_V_B5S 8 3685 #define BK5CR_M_B5S (0x7 << BK5CR_V_B5S) 3686 #define BK5CR_V_B5S0 8 3687 #define BK5CR_M_B5S0 (1 << BK5CR_V_B5S0) 3688 #define BK5CR_V_B5S1 9 3689 #define BK5CR_M_B5S1 (1 << BK5CR_V_B5S1) 3690 #define BK5CR_V_B5S2 10 3691 #define BK5CR_M_B5S2 (1 << BK5CR_V_B5S2) 3692 #define BK5CR_V_BANKEN5 11 3693 #define BK5CR_M_BANKEN5 (1 << BK5CR_V_BANKEN5) 3694 #define BK5CR_V_ENMDEN5N 12 3695 #define BK5CR_M_ENMDEN5N (1 << BK5CR_V_ENMDEN5N) 3696 #define BK5CR_V_COLADR5 13 3697 #define BK5CR_M_COLADR5 (0xE << BK5CR_V_COLADR5) 3698 #define BK5CR_V_COLADR50 13 3699 #define BK5CR_M_COLADR50 (1 << BK5CR_V_COLADR50) 3700 #define BK5CR_V_COLADR51 14 3701 #define BK5CR_M_COLADR51 (1 << BK5CR_V_COLADR51) 3702 #define BK5CR_V_COLADR52 15 3703 #define BK5CR_M_COLADR52 (1 << BK5CR_V_COLADR52) 3704 3705 /* 3706 ** Bank 5 DRAM Size 3707 */ 3708 #define B5S_256KB 0x000 3709 #define B5S_512KB BK5CR_M_B5S0 3710 #define B5S_1MB BK5CR_M_B5S1 3711 #define B5S_2MB (BK5CR_M_B5S0 | BK5CR_M_B5S1) 3712 #define B5S_4MB BK5CR_M_B5S2 3713 #define B5S_16MB (BK5CR_M_B5S1 | BK5CR_M_B5S2) 3714 3715 /* 3716 ** Bank 5 Column Address Bits 3717 */ 3718 #define COLADR5_8 0x000 3719 #define COLADR5_9 BK5CR_M_COLADR50 3720 #define COLADR5_10 BK5CR_M_COLADR51 3721 #define COLADR5_11 (BK5CR_M_COLADR50 | BK5CR_M_COLADR51) 3722 #define COLADR5_12 BK5CR_M_COLADR52 3723 3724 /* 3725 ** 3726 ** Bank 4/5 Timing Control Register (BK45TCR) - Index 0x20A 3727 ** 3728 ** Loc Size Name Function 3729 ** ----- ---- ---- --------------------------------- 3730 ** <0> 1 B45WRCPW0 Bank 4/5 Write CAS Cycle Time 0 3731 ** <1> 1 B45WRCPW1 Bank 4/5 Write CAS Cycle Time 1 3732 ** <2> 1 MA45WRDLY Bank 4/5 Write MA Delay 3733 ** <3> 1 B45RDCPW0 Bank 4/5 Read CAS Cycle Time 0 3734 ** <4> 1 B45RDCPW1 Bank 4/5 Read CAS Cycle Time 1 3735 ** <5> 1 MA45RDDLY Bank 4/5 Read MA Delay 3736 ** <6> 1 B45CPRE Bank 4/5 CAS Precharge 3737 ** <7> 1 B45RTMA Bank 4/5 RAS to CAS Delay 3738 ** <8> 1 B45MATC Bank 4/5 MA to CAS Delay 3739 ** <9> 1 B45RPRE0 Bank 4/5 RAS Precharge Time 0 3740 ** <10> 1 B45RPRE1 Bank 4/5 RAS Precharge Time 1 3741 ** <11> 1 B45RPRE2 Bank 4/5 RAS Precharge Time 2 3742 ** <13> 1 BNK45_ITL Bank 4/5 Interleave Enable 3743 ** 3744 ** <12><14:15> Reserved 3745 */ 3746 #define DRAMCR_BK45TCR_REG 0x20A 3747 #define DRAMCR_BK45TCR_INIT ( BK45TCR_M_B45WRCPW | BK45TCR_M_MA45WRDLY | \ 3748 BK45TCR_M_B45RDCPW | BK45TCR_M_MA45RDDLY | \ 3749 BK45TCR_M_B45CPRE | BK45TCR_M_B45RTMA | \ 3750 BK45TCR_M_B45MATC | BK45TCR_M_B45RPRE ) 3751 #define BK45TCR_V_B45WRCPW 0 3752 #define BK45TCR_M_B45WRCPW (0x3 << BK45TCR_V_B45WRCPW) 3753 #define BK45TCR_V_B45WRCPW0 0 3754 #define BK45TCR_M_B45WRCPW0 (1 << BK45TCR_V_B45WRCPW0) 3755 #define BK45TCR_V_B45WRCPW1 1 3756 #define BK45TCR_M_B45WRCPW1 (1 << BK45TCR_V_B45WRCPW1) 3757 #define BK45TCR_V_MA45WRDLY 2 3758 #define BK45TCR_M_MA45WRDLY (1 << BK45TCR_V_MA45WRDLY) 3759 #define BK45TCR_V_B45RDCPW 3 3760 #define BK45TCR_M_B45RDCPW (0x3 << BK45TCR_V_B45RDCPW) 3761 #define BK45TCR_V_B45RDCPW0 3 3762 #define BK45TCR_M_B45RDCPW0 (1 << BK45TCR_V_B45RDCPW0) 3763 #define BK45TCR_V_B45RDCPW1 4 3764 #define BK45TCR_M_B45RDCPW1 (1 << BK45TCR_V_B45RDCPW1) 3765 #define BK45TCR_V_MA45RDDLY 5 3766 #define BK45TCR_M_MA45RDDLY (1 << BK45TCR_V_MA45RDDLY) 3767 #define BK45TCR_V_B45CPRE 6 3768 #define BK45TCR_M_B45CPRE (1 << BK45TCR_V_B45CPRE) 3769 #define BK45TCR_V_B45RTMA 7 3770 #define BK45TCR_M_B45RTMA (1 << BK45TCR_V_B45RTMA) 3771 #define BK45TCR_V_B45MATC 8 3772 #define BK45TCR_M_B45MATC (1 << BK45TCR_V_B45MATC) 3773 #define BK45TCR_V_B45RPRE 9 3774 #define BK45TCR_M_B45RPRE (0x7 << BK45TCR_V_B45RPRE) 3775 #define BK45TCR_V_B45RPRE0 9 3776 #define BK45TCR_M_B45RPRE0 (1 << BK45TCR_V_B45RPRE0) 3777 #define BK45TCR_V_B45RPRE1 10 3778 #define BK45TCR_M_B45RPRE1 (1 << BK45TCR_V_B45RPRE1) 3779 #define BK45TCR_V_B45RPRE2 11 3780 #define BK45TCR_M_B45RPRE2 (1 << BK45TCR_V_B45RPRE2) 3781 #define BK45TCR_V_BNK45_ITL 13 3782 #define BK45TCR_M_BNK45_ITL (1 << BK45TCR_V_BNK45_ITL) 3783 3784 /* 3785 ** Bank 4/5 Write CAS Cycle Time 3786 */ 3787 #define B45WRCPW_1T BK45TCR_M_B45WRCPW0 3788 #define B45WRCPW_2T BK45TCR_M_B45WRCPW1 3789 #define B45WRCPW_3T (BK45TCR_M_B45WRCPW0 | BK45TCR_M_B45WRCPW1) 3790 3791 /* 3792 ** Bank 4/5 Read CAS Cycle Time 3793 */ 3794 #define B45RDCPW_1T 0x000 3795 #define B45RDCPW_2T BK45TCR_M_B45RDCPW0 3796 #define B45RDCPW_3T BK45TCR_M_B45RDCPW1 3797 #define B45RDCPW_4T (BK45TCR_M_B45RDCPW0 | BK45TCR_M_B45RDCPW1) 3798 3799 /* 3800 ** Bank 4/5 RAS Precharge Time 3801 */ 3802 #define B45RPRE_1PT5T BK45TCR_M_B45RPRE1 3803 #define B45RPRE_2T (BK45TCR_M_B45RPRE0 | BK45TCR_M_B45RPRE1) 3804 #define B45RPRE_2PT5T BK45TCR_M_B45RPRE2 3805 #define B45RPRE_3T (BK45TCR_M_B45RPRE0 | BK45TCR_M_B45RPRE2) 3806 #define B45RPRE_3PT5T (BK45TCR_M_B45RPRE1 | BK45TCR_M_B45RPRE2) 3807 #define B45RPRE_4T (BK45TCR_M_B45RPRE0 | BK45TCR_M_B45RPRE1 | BK45TCR_M_B45RPRE2) 3808 3809 /* 3810 ** 3811 ** DRAM Configuration Register 1 (DRAMCR1) - Index 0x20B 3812 ** 3813 ** Loc Size Name Function 3814 ** ----- ---- ---- --------------------------------- 3815 ** <0> 1 SIXRASEN Six RAS# Control Line Enable 3816 ** <3> 1 BRSTWREN Burst WRite Enable 3817 ** <4> 1 PS0 DRAM Page Size 0 3818 ** <5> 1 PS1 DRAM Page Size 1 3819 ** <6> 1 PS2 DRAM Page Size 2 3820 ** <7> 1 FSTPHDEC Fast Page Hit Decode 3821 ** <9> 1 RONLYRF DRAM Refresh Scheme 3822 ** <10> 1 RFRPRE0 RAS Precharge Time for Refresh Cycles 0 3823 ** <11> 1 RFRPRE1 RAS Precharge Time for Refresh Cycles 1 3824 ** <12> 1 RFRPW0 RAS Pulse Width for Refresh Cycles 0 3825 ** <13> 1 RFRPW1 RAS Pulse Width for Refresh Cycles 1 3826 ** <14> 1 XWITDOFFR Extra Wait State for Lead-off Read Cycles 3827 ** <15> 1 XWITDOFFW Extra Wait State for Lead-off Write Cycles 3828 ** 3829 ** <1:2><8> Reserved 3830 */ 3831 #define DRAMCR_DRAMCR1_REG 0x20B 3832 #define DRAMCR_DRAMCR1_INIT ( DRAMCR1_M_XWITDOFFR | DRAMCR1_M_XWITDOFFW ) 3833 #define DRAMCR1_V_SIXRASEN 0 3834 #define DRAMCR1_M_SIXRASEN (1 << DRAMCR1_V_SIXRASEN) 3835 #define DRAMCR1_V_BRSTWREN 3 3836 #define DRAMCR1_M_BRSTWREN (1 << DRAMCR1_V_BRSTWREN) 3837 #define DRAMCR1_V_PS 4 3838 #define DRAMCR1_M_PS (0x7 << DRAMCR1_V_PS) 3839 #define DRAMCR1_V_PS0 4 3840 #define DRAMCR1_M_PS0 (1 << DRAMCR1_V_PS0) 3841 #define DRAMCR1_V_PS1 5 3842 #define DRAMCR1_M_PS1 (1 << DRAMCR1_V_PS1) 3843 #define DRAMCR1_V_PS2 6 3844 #define DRAMCR1_M_PS2 (1 << DRAMCR1_V_PS2) 3845 #define DRAMCR1_V_FSTPHDEC 7 3846 #define DRAMCR1_M_FSTPHDEC (1 << DRAMCR1_V_FSTPHDEC) 3847 #define DRAMCR1_V_RONLYRF 9 3848 #define DRAMCR1_M_RONLYRF (1 << DRAMCR1_V_RONLYRF) 3849 #define DRAMCR1_V_RFRPRE 10 3850 #define DRAMCR1_M_RFRPRE (0x3 << DRAMCR1_V_RFRPRE) 3851 #define DRAMCR1_V_RFRPRE0 10 3852 #define DRAMCR1_M_RFRPRE0 (1 << DRAMCR1_V_RFRPRE0) 3853 #define DRAMCR1_V_RFRPRE1 11 3854 #define DRAMCR1_M_RFRPRE1 (1 << DRAMCR1_V_RFRPRE1) 3855 #define DRAMCR1_V_RFRPW 12 3856 #define DRAMCR1_M_RFRPW (0x3 << DRAMCR1_V_RFRPW) 3857 #define DRAMCR1_V_RFRPW0 12 3858 #define DRAMCR1_M_RFRPW0 (1 << DRAMCR1_V_RFRPW0) 3859 #define DRAMCR1_V_RFRPW1 13 3860 #define DRAMCR1_M_RFRPW1 (1 << DRAMCR1_V_RFRPW1) 3861 #define DRAMCR1_V_XWITDOFFR 14 3862 #define DRAMCR1_M_XWITDOFFR (1 << DRAMCR1_V_XWITDOFFR) 3863 #define DRAMCR1_V_XWITDOFFW 15 3864 #define DRAMCR1_M_XWITDOFFW (1 << DRAMCR1_V_XWITDOFFW) 3865 3866 /* 3867 ** DRAM Page Size 3868 */ 3869 #define PS_1KB 0x000 3870 #define PS_2KB DRAMCR1_M_PS0 3871 #define PS_4KB DRAMCR1_M_PS1 3872 #define PS_8KB (DRAMCR1_M_PS0 | DRAMCR1_M_PS1) 3873 #define PS_16KB DRAMCR1_M_PS2 3874 #define PS_32KB (DRAMCR1_M_PS0 | DRAMCR1_M_PS2) 3875 3876 /* 3877 ** RAS Precharge Time for Refresh Cycles 3878 */ 3879 #define RFRPRE_5T 0x000 3880 #define RFRPRE_4T DRAMCR1_M_RFRPRE0 3881 #define RFRPRE_3T DRAMCR1_M_RFRPRE1 3882 #define RFRPRE_2T (DRAMCR1_M_RFRPRE0 | DRAMCR1_M_RFRPRE1) 3883 3884 /* 3885 ** RAS Pulse Width for Refresh Cycles 3886 */ 3887 #define RFRPW_5T 0x000 3888 #define RFRPW_4T DRAMCR1_M_RFRPW0 3889 #define RFRPW_3T DRAMCR1_M_RFRPW1 3890 #define RFRPW_2T (DRAMCR1_M_RFRPW0 | DRAMCR1_M_RFRPW1) 3891 3892 /* 3893 ** 3894 ** DRAM Configuration Register 2 (DRAMCR2) - Index 0x20C 3895 ** 3896 ** Loc Size Name Function 3897 ** ----- ---- ---- --------------------------------- 3898 ** <9> 1 ENPARADRL Enable Parity Error Address Latch 3899 ** <10> 1 ENPARCK0 Enable Parity Check for Bank 0 3900 ** <11> 1 ENPARCK1 Enable Parity Check for Bank 1 3901 ** <12> 1 ENPARCK2 Enable Parity Check for Bank 2 3902 ** <13> 1 ENPARCK3 Enable Parity Check for Bank 3 3903 ** <14> 1 ENPARCK4 Enable Parity Check for Bank 4 3904 ** <15> 1 ENPARCK5 Enable Parity Check for Bank 5 3905 ** 3906 ** <0:8> Reserved 3907 */ 3908 #define DRAMCR_DRAMCR2_REG 0x20C 3909 #define DRAMCR_DRAMCR2_INIT 0x0000 3910 #define DRAMCR2_V_ENPARADRL 9 3911 #define DRAMCR2_M_ENPARADRL (1 << DRAMCR2_V_ENPARADRL) 3912 #define DRAMCR2_V_ENPARCK0 10 3913 #define DRAMCR2_M_ENPARCK0 (1 << DRAMCR2_V_ENPARCK0) 3914 #define DRAMCR2_V_ENPARCK1 11 3915 #define DRAMCR2_M_ENPARCK1 (1 << DRAMCR2_V_ENPARCK1) 3916 #define DRAMCR2_V_ENPARCK2 12 3917 #define DRAMCR2_M_ENPARCK2 (1 << DRAMCR2_V_ENPARCK2) 3918 #define DRAMCR2_V_ENPARCK3 13 3919 #define DRAMCR2_M_ENPARCK3 (1 << DRAMCR2_V_ENPARCK3) 3920 #define DRAMCR2_V_ENPARCK4 14 3921 #define DRAMCR2_M_ENPARCK4 (1 << DRAMCR2_V_ENPARCK4) 3922 #define DRAMCR2_V_ENPARCK5 15 3923 #define DRAMCR2_M_ENPARCK5 (1 << DRAMCR2_V_ENPARCK5) 3924 3925 /* 3926 ** 3927 ** DRAM Configuration Register 3 (DRAMCR3) - Index 0x20D 3928 ** 3929 ** Loc Size Name Function 3930 ** ----- ---- ---- --------------------------------- 3931 ** <0> 1 RAS0DRV0 Driving Strength of RAS0# Output 0 3932 ** <1> 1 RAS0DRV1 Driving Strength of RAS0# Output 1 3933 ** <2> 1 RAS0DRV2 Driving Strength of RAS0# Output 2 3934 ** <3> 1 RAS0DRV3 Driving Strength of RAS0# Output 3 3935 ** <4> 1 RAS1DRV0 Driving Strength of RAS1# Output 0 3936 ** <5> 1 RAS1DRV1 Driving Strength of RAS1# Output 1 3937 ** <6> 1 RAS1DRV2 Driving Strength of RAS1# Output 2 3938 ** <7> 1 RAS1DRV3 Driving Strength of RAS1# Output 3 3939 ** <8> 1 RAS2DRV0 Driving Strength of RAS2# Output 0 3940 ** <9> 1 RAS2DRV1 Driving Strength of RAS2# Output 1 3941 ** <10> 1 RAS2DRV2 Driving Strength of RAS2# Output 2 3942 ** <11> 1 RAS2DRV3 Driving Strength of RAS2# Output 3 3943 ** <12> 1 RAS3DRV0 Driving Strength of RAS3# Output 0 3944 ** <13> 1 RAS3DRV1 Driving Strength of RAS3# Output 1 3945 ** <14> 1 RAS3DRV2 Driving Strength of RAS3# Output 2 3946 ** <15> 1 RAS3DRV3 Driving Strength of RAS3# Output 3 3947 ** 3948 */ 3949 #define DRAMCR_DRAMCR3_REG 0x20D 3950 #define DRAMCR_DRAMCR3_INIT ( DRAMCR3_M_RAS0DRV0 | DRAMCR3_M_RAS0DRV1 | \ 3951 DRAMCR3_M_RAS0DRV2 | DRAMCR3_M_RAS1DRV0 | \ 3952 DRAMCR3_M_RAS1DRV1 | DRAMCR3_M_RAS1DRV2 | \ 3953 DRAMCR3_M_RAS2DRV0 | DRAMCR3_M_RAS2DRV1 | \ 3954 DRAMCR3_M_RAS2DRV2 | DRAMCR3_M_RAS3DRV0 | \ 3955 DRAMCR3_M_RAS3DRV1 | DRAMCR3_M_RAS3DRV2 ) 3956 #define DRAMCR3_V_RAS0DRV 0 3957 #define DRAMCR3_M_RAS0DRV (0xF << DRAMCR3_V_RAS0DRV) 3958 #define DRAMCR3_V_RAS0DRV0 0 3959 #define DRAMCR3_M_RAS0DRV0 (1 << DRAMCR3_V_RAS0DRV0) 3960 #define DRAMCR3_V_RAS0DRV1 1 3961 #define DRAMCR3_M_RAS0DRV1 (1 << DRAMCR3_V_RAS0DRV1) 3962 #define DRAMCR3_V_RAS0DRV2 2 3963 #define DRAMCR3_M_RAS0DRV2 (1 << DRAMCR3_V_RAS0DRV2) 3964 #define DRAMCR3_V_RAS0DRV3 3 3965 #define DRAMCR3_M_RAS0DRV3 (1 << DRAMCR3_V_RAS0DRV3) 3966 #define DRAMCR3_V_RAS1DRV 4 3967 #define DRAMCR3_M_RAS1DRV (0xF << DRAMCR3_V_RAS1DRV) 3968 #define DRAMCR3_V_RAS1DRV0 4 3969 #define DRAMCR3_M_RAS1DRV0 (1 << DRAMCR3_V_RAS1DRV0) 3970 #define DRAMCR3_V_RAS1DRV1 5 3971 #define DRAMCR3_M_RAS1DRV1 (1 << DRAMCR3_V_RAS1DRV1) 3972 #define DRAMCR3_V_RAS1DRV2 6 3973 #define DRAMCR3_M_RAS1DRV2 (1 << DRAMCR3_V_RAS1DRV2) 3974 #define DRAMCR3_V_RAS1DRV3 7 3975 #define DRAMCR3_M_RAS1DRV3 (1 << DRAMCR3_V_RAS1DRV3) 3976 #define DRAMCR3_V_RAS2DRV 8 3977 #define DRAMCR3_M_RAS2DRV (0xF << DRAMCR3_V_RAS2DRV) 3978 #define DRAMCR3_V_RAS2DRV0 8 3979 #define DRAMCR3_M_RAS2DRV0 (1 << DRAMCR3_V_RAS2DRV0) 3980 #define DRAMCR3_V_RAS2DRV1 9 3981 #define DRAMCR3_M_RAS2DRV1 (1 << DRAMCR3_V_RAS2DRV1) 3982 #define DRAMCR3_V_RAS2DRV2 10 3983 #define DRAMCR3_M_RAS2DRV2 (1 << DRAMCR3_V_RAS2DRV2) 3984 #define DRAMCR3_V_RAS2DRV3 11 3985 #define DRAMCR3_M_RAS2DRV3 (1 << DRAMCR3_V_RAS2DRV3) 3986 #define DRAMCR3_V_RAS3DRV 12 3987 #define DRAMCR3_M_RAS3DRV (0xF << DRAMCR3_V_RAS3DRV) 3988 #define DRAMCR3_V_RAS3DRV0 12 3989 #define DRAMCR3_M_RAS3DRV0 (1 << DRAMCR3_V_RAS3DRV0) 3990 #define DRAMCR3_V_RAS3DRV1 13 3991 #define DRAMCR3_M_RAS3DRV1 (1 << DRAMCR3_V_RAS3DRV1) 3992 #define DRAMCR3_V_RAS3DRV2 14 3993 #define DRAMCR3_M_RAS3DRV2 (1 << DRAMCR3_V_RAS3DRV2) 3994 #define DRAMCR3_V_RAS3DRV3 15 3995 #define DRAMCR3_M_RAS3DRV3 (1 << DRAMCR3_V_RAS3DRV3) 3996 3997 /* 3998 ** Driving Strength of RAS0# Output (mA) 3999 */ 4000 #define RAS0DRV_4MA DRAMCR3_M_RAS0DRV0 4001 #define RAS0DRV_8MA (DRAMCR3_M_RAS0DRV0 | DRAMCR3_M_RAS0DRV1) 4002 #define RAS0DRV_12MA (DRAMCR3_M_RAS0DRV0 | DRAMCR3_M_RAS0DRV1 | DRAMCR3_M_RAS0DRV2 4003 4004 /* 4005 ** Driving Strength of RAS1# Output (mA) 4006 */ 4007 #define RAS1DRV_4MA DRAMCR3_M_RAS1DRV0 4008 #define RAS1DRV_8MA (DRAMCR3_M_RAS1DRV0 | DRAMCR3_M_RAS1DRV1) 4009 #define RAS1DRV_12MA (DRAMCR3_M_RAS1DRV0 | DRAMCR3_M_RAS1DRV1 | DRAMCR3_M_RAS1DRV2 4010 4011 /* 4012 ** Driving Strength of RAS2# Output (mA) 4013 */ 4014 #define RAS2DRV_4MA DRAMCR3_M_RAS2DRV0 4015 #define RAS2DRV_8MA (DRAMCR3_M_RAS2DRV0 | DRAMCR3_M_RAS2DRV1) 4016 #define RAS2DRV_12MA (DRAMCR3_M_RAS2DRV0 | DRAMCR3_M_RAS2DRV1 | DRAMCR3_M_RAS2DRV2 4017 4018 /* 4019 ** Driving Strength of RAS3# Output (mA) 4020 */ 4021 #define RAS3DRV_4MA DRAMCR3_M_RAS3DRV0 4022 #define RAS3DRV_8MA (DRAMCR3_M_RAS3DRV0 | DRAMCR3_M_RAS3DRV1) 4023 #define RAS3DRV_12MA (DRAMCR3_M_RAS3DRV0 | DRAMCR3_M_RAS3DRV1 | DRAMCR3_M_RAS3DRV2 4024 4025 /* 4026 ** 4027 ** DRAM Configuration Register 4 (DRAMCR4) - Index 0x20E 4028 ** 4029 ** Loc Size Name Function 4030 ** ----- ---- ---- --------------------------------- 4031 ** <0> 1 MADRV0 Driving Strength of MA Output 0 4032 ** <1> 1 MADRV1 Driving Strength of MA Output 1 4033 ** <2> 1 MADRV2 Driving Strength of MA Output 2 4034 ** <3> 1 MADRV3 Driving Strength of MA Output 3 4035 ** <4> 1 CASADRV0 Driving Strength of CASA Output 0 4036 ** <5> 1 CASADRV1 Driving Strength of CASA Output 1 4037 ** <6> 1 CASADRV2 Driving Strength of CASA Output 2 4038 ** <7> 1 CASADRV3 Driving Strength of CASA Output 3 4039 ** <8> 1 CASBDRV0 Driving Strength of CASB Output 0 4040 ** <9> 1 CASBDRV1 Driving Strength of CASB Output 1 4041 ** <10> 1 CASBDRV2 Driving Strength of CASB Output 2 4042 ** <11> 1 CASBDRV3 Driving Strength of CASB Output 3 4043 ** 4044 */ 4045 #define DRAMCR_DRAMCR4_REG 0x20E 4046 #define DRAMCR_DRAMCR4_INIT ( DRAMCR4_M_MADRV0 | DRAMCR4_M_MADRV1 | \ 4047 DRAMCR4_M_MADRV2 | DRAMCR4_M_CASADRV0 | \ 4048 DRAMCR4_M_CASADRV1 | DRAMCR4_M_CASADRV2 | \ 4049 DRAMCR4_M_CASBDRV0 | DRAMCR4_M_CASBDRV1 | \ 4050 DRAMCR4_M_CASBDRV2 ) 4051 #define DRAMCR4_V_MADRV 0 4052 #define DRAMCR4_M_MADRV (0xF << DRAMCR4_V_MADRV) 4053 #define DRAMCR4_V_MADRV0 0 4054 #define DRAMCR4_M_MADRV0 (1 << DRAMCR4_V_MADRV0) 4055 #define DRAMCR4_V_MADRV1 1 4056 #define DRAMCR4_M_MADRV1 (1 << DRAMCR4_V_MADRV1) 4057 #define DRAMCR4_V_MADRV2 2 4058 #define DRAMCR4_M_MADRV2 (1 << DRAMCR4_V_MADRV2) 4059 #define DRAMCR4_V_MADRV3 3 4060 #define DRAMCR4_M_MADRV3 (1 << DRAMCR4_V_MADRV3) 4061 #define DRAMCR4_V_CASADRV 4 4062 #define DRAMCR4_M_CASADRV (0xF << DRAMCR4_V_CASADRV) 4063 #define DRAMCR4_V_CASADRV0 4 4064 #define DRAMCR4_M_CASADRV0 (1 << DRAMCR4_V_CASADRV0) 4065 #define DRAMCR4_V_CASADRV1 5 4066 #define DRAMCR4_M_CASADRV1 (1 << DRAMCR4_V_CASADRV1) 4067 #define DRAMCR4_V_CASADRV2 6 4068 #define DRAMCR4_M_CASADRV2 (1 << DRAMCR4_V_CASADRV2) 4069 #define DRAMCR4_V_CASADRV3 7 4070 #define DRAMCR4_M_CASADRV3 (1 << DRAMCR4_V_CASADRV3) 4071 #define DRAMCR4_V_CASBDRV 8 4072 #define DRAMCR4_M_CASBDRV (0xF << DRAMCR4_V_CASBDRV) 4073 #define DRAMCR4_V_CASBDRV0 8 4074 #define DRAMCR4_M_CASBDRV0 (1 << DRAMCR4_V_CASBDRV0) 4075 #define DRAMCR4_V_CASBDRV1 9 4076 #define DRAMCR4_M_CASBDRV1 (1 << DRAMCR4_V_CASBDRV1) 4077 #define DRAMCR4_V_CASBDRV2 10 4078 #define DRAMCR4_M_CASBDRV2 (1 << DRAMCR4_V_CASBDRV2) 4079 #define DRAMCR4_V_CASBDRV3 11 4080 #define DRAMCR4_M_CASBDRV3 (1 << DRAMCR4_V_CASBDRV3) 4081 4082 /* 4083 ** Driving Strength of MA Output (mA) 4084 */ 4085 #define MADRV_4MA DRAMCR2_M_MADRV0 4086 #define MADRV_8MA (DRAMCR2_M_MADRV0 | DRAMCR2_M_MADRV1) 4087 #define MADRV_12MA (DRAMCR2_M_MADRV0 | DRAMCR2_M_MADRV1 | DRAMCR2_M_MADRV2 4088 4089 /* 4090 ** Driving Strength of CASA Output (mA) 4091 */ 4092 #define CASADRV_4MA DRAMCR2_M_CASADRV0 4093 #define CASADRV_8MA (DRAMCR2_M_CASADRV0 | DRAMCR2_M_CASADRV1) 4094 #define CASADRV_12MA (DRAMCR2_M_CASADRV0 | DRAMCR2_M_CASADRV1 | DRAMCR2_M_CASADRV2 4095 4096 /* 4097 ** Driving Strength of CASB Output (mA) 4098 */ 4099 #define CASBDRV_4MA DRAMCR2_M_CASBDRV0 4100 #define CASBDRV_8MA (DRAMCR2_M_CASBDRV0 | DRAMCR2_M_CASBDRV1) 4101 #define CASBDRV_12MA (DRAMCR2_M_CASBDRV0 | DRAMCR2_M_CASBDRV1 | DRAMCR2_M_CASBDRV2 4102 4103 /* 4104 ** 4105 ** DRAM Configuration Register 5 (DRAMCR5) - Index 0x20F 4106 ** 4107 ** Loc Size Name Function 4108 ** ----- ---- ---- --------------------------------- 4109 ** <1> 1 FLASHENB Flash Enable 4110 ** <10> 1 ENC0ROMCS Enable ROMCS# for C0000H-C7FFFH Region 4111 ** <11> 1 ENC8ROMCS Enable ROMCS# for C8000H-CFFFFH Region 4112 ** <12> 1 END0ROMCS Enable ROMCS# for D0000H-D7FFFH Region 4113 ** <13> 1 END8ROMCS Enable ROMCS# for D8000H-DFFFFH Region 4114 ** <14> 1 ENE0ROMCS Enable ROMCS# for E0000H-E7FFFH Region 4115 ** <15> 1 ENE8ROMCS Enable ROMCS# for E8000H-EFFFFH Region 4116 ** 4117 ** <0><2:9> Reserved 4118 */ 4119 #define DRAMCR_DRAMCR5_REG 0x20F 4120 #define DRAMCR_DRAMCR5_INIT 0x0000 4121 #define DRAMCR5_V_FLASHENB 0 4122 #define DRAMCR5_M_FLASHENB (1 << DRAMCR5_V_FLASHENB) 4123 #define DRAMCR5_V_ENC0ROMCS 10 4124 #define DRAMCR5_M_ENC0ROMCS (1 << DRAMCR5_V_ENC0ROMCS) 4125 #define DRAMCR5_V_ENC8ROMCS 11 4126 #define DRAMCR5_M_ENC8ROMCS (1 << DRAMCR5_V_ENC8ROMCS) 4127 #define DRAMCR5_V_END0ROMCS 12 4128 #define DRAMCR5_M_END0ROMCS (1 << DRAMCR5_V_ENC0ROMCS) 4129 #define DRAMCR5_V_END8ROMCS 13 4130 #define DRAMCR5_M_END8ROMCS (1 << DRAMCR5_V_ENC8ROMCS) 4131 #define DRAMCR5_V_ENE0ROMCS 14 4132 #define DRAMCR5_M_ENE0ROMCS (1 << DRAMCR5_V_ENC0ROMCS) 4133 #define DRAMCR5_V_ENE8ROMCS 15 4134 #define DRAMCR5_M_ENE8ROMCS (1 << DRAMCR5_V_ENC8ROMCS) 4135 4136 /* 4137 ** Cache Controller Registers 4138 ** 4139 */ 4140 4141 /* 4142 ** 4143 ** Cache Control Register 1 (CCR1) - Index 0x400 4144 ** 4145 ** Loc Size Name Function 4146 ** ----- ---- ---- --------------------------------- 4147 ** <0> 1 L2CST0 Level 2 Cache Status 0 4148 ** <1> 1 L2CST1 Level 2 Cache Status 1 4149 ** <2> 1 L2CST2 Level 2 Cache Status 2 4150 ** <3> 1 L2CST3 Level 2 Cache Status 3 4151 ** <4> 1 CSIZE0 Level 2 Cache Data 0 4152 ** <5> 1 CSIZE1 Level 2 Cache Data 1 4153 ** <6> 1 CSIZE2 Level 2 Cache Data 2 4154 ** <7> 1 CSIZE3 Level 2 Cache Data 3 4155 ** <8> 1 L1WB Enable Level 1 Write Back Support 4156 ** <9> 1 WPL2KEN L2 Cache Write Protect 4157 ** 4158 ** <10:15> Reserved 4159 */ 4160 #define CCR_CCR1_REG 0x400 4161 #define CCR1_V_L2CST 0 4162 #define CCR1_M_L2CST (0xF << CCR1_V_L2CST) 4163 #define CCR1_V_L2CST0 0 4164 #define CCR1_M_L2CST0 (1 << CCR1_V_L2CST0) 4165 #define CCR1_V_L2CST1 1 4166 #define CCR1_M_L2CST1 (1 << CCR1_V_L2CST1) 4167 #define CCR1_V_L2CST2 2 4168 #define CCR1_M_L2CST2 (1 << CCR1_V_L2CST2) 4169 #define CCR1_V_L2CST3 3 4170 #define CCR1_M_L2CST3 (1 << CCR1_V_L2CST3) 4171 #define CCR1_V_CSIZE 4 4172 #define CCR1_M_CSIZE (0xF << CCR1_V_CSIZE) 4173 #define CCR1_V_CSIZE0 4 4174 #define CCR1_M_CSIZE0 (1 << CCR1_V_CSIZE0) 4175 #define CCR1_V_CSIZE1 5 4176 #define CCR1_M_CSIZE1 (1 << CCR1_V_CSIZE1) 4177 #define CCR1_V_CSIZE2 6 4178 #define CCR1_M_CSIZE2 (1 << CCR1_V_CSIZE2) 4179 #define CCR1_V_CSIZE3 7 4180 #define CCR1_M_CSIZE3 (1 << CCR1_V_CSIZE3) 4181 #define CCR1_V_L1WB 8 4182 #define CCR1_M_L1WB (1 << CCR1_V_L1WB) 4183 #define CCR1_V_WPL2KEN 9 4184 #define CCR1_M_WPL2KEN (1 << CCR1_V_WPL2KEN) 4185 4186 /* 4187 ** Level 2 Cache Status 4188 */ 4189 #define L2CST_STNDBY 0x0000 4190 #define L2CST_INIT CCR1_M_L2CST0 4191 #define L2CST_WRTHRU CCR1_M_L2CST1 4192 #define L2CST_WRBACK (CCR1_M_L2CST0 | CCR1_M_L2CST1) 4193 #define L2CST_FLUSH CCR1_M_L2CST2 4194 #define L2CST_WRTHRUDR (CCR1_M_L2CST0 | CCR1_M_L2CST2) 4195 #define L2CST_WRBACKDR (CCR1_M_L2CST1 | CCR1_M_L2CST2) 4196 4197 /* 4198 ** Level 2 Cache Size 4199 */ 4200 #define CSIZE_64KB_2BNK CCR1_M_CSIZE0 4201 #define CSIZE_128KB_1BNK CCR1_M_CSIZE1 4202 #define CSIZE_256KB_2BNK (CCR1_M_CSIZE0 | CCR1_M_CSIZE1) 4203 #define CSIZE_512KB_1BNK CCR1_M_CSIZE2 4204 #define CSIZE_1MB_2BNK (CCR1_M_CSIZE0 | CCR1_M_CSIZE2) 4205 #define CSIZE_256KB_1BNK (CCR1_M_CSIZE0 | CCR1_M_CSIZE1 | CCR1_M_CSIZE3) 4206 4207 /* 4208 ** 4209 ** Cache Control Register 2 (CCR2) - Index 0x401 4210 ** 4211 ** Loc Size Name Function 4212 ** ----- ---- ---- --------------------------------- 4213 ** <0> 1 TWIDTH Width of L2 Cache TAG Data 4214 ** <1> 1 DTYEN Configuration of L2 Cache TAG Field 4215 ** <2> 1 DRTWEN Configuration of L2 Cache TAG Write 4216 ** <7> 1 EHITEN External Comparator is Used 4217 ** 4218 ** <3:6><8:15> Reserved 4219 */ 4220 #define CCR_CCR2_REG 0x401 4221 #define CCR2_V_TWIDTH 0 4222 #define CCR2_M_TWIDTH (1 << CCR2_V_TWIDTH) 4223 #define CCR2_V_DTYEN 1 4224 #define CCR2_M_DTYEN (1 << CCR2_V_DTYEN) 4225 #define CCR2_V_DRTWEN 2 4226 #define CCR2_M_DRTWEN (1 << CCR2_V_DRTWEN) 4227 #define CCR2_V_EHITEN 7 4228 #define CCR2_M_EHITEN (1 << CCR2_V_EHITEN) 4229 4230 /* 4231 ** 4232 ** Cache Control Register 3 (CCR3) - Index 0x402 4233 ** 4234 ** Loc Size Name Function 4235 ** ----- ---- ---- --------------------------------- 4236 ** <0> 1 RDL0 CPU Cache Read Lead-off Cycles 0 4237 ** <1> 1 RDL1 CPU Cache Read Lead-off Cycles 1 4238 ** <2> 1 RDB2T CPU Cache Read Burst Cycles 4239 ** <3> 1 WRL0 CPU Cache Write Lead-off Cycles 0 4240 ** <4> 1 WRL1 CPU Cache Write Lead-off Cycles 1 4241 ** <5> 1 WRB2T CPU Cache Write Burst Cycles 4242 ** <6> 1 WRTEG0 Cache Write Enable Trailing Edge Timing 0 4243 ** <7> 1 WRTEG1 Cache Write Enable Trailing Edge Timing 1 4244 ** <8> 1 RDTEG0 Cache Write Enable Trailing Edge Timing 0 4245 ** <9> 1 RDTEG1 Cache Write Enable Trailing Edge Timing 1 4246 ** 4247 ** <10:15> Reserved 4248 */ 4249 #define CCR_CCR3_REG 0x402 4250 #define CCR3_V_RDL 0 4251 #define CCR3_M_RDL (0x3 << CCR3_V_RDL) 4252 #define CCR3_V_RDL0 0 4253 #define CCR3_M_RDL0 (1 << CCR3_V_RDL0) 4254 #define CCR3_V_RDL1 2 4255 #define CCR3_M_RDL1 (1 << CCR3_V_RDL1) 4256 #define CCR3_V_RDB2T 3 4257 #define CCR3_M_RDB2T (1 << CCR3_V_RDB2T) 4258 #define CCR3_V_WRL 3 4259 #define CCR3_M_WRL (0x3 << CCR3_V_WRL) 4260 #define CCR3_V_WRL0 3 4261 #define CCR3_M_WRL0 (1 << CCR3_V_WRL0) 4262 #define CCR3_V_WRL1 4 4263 #define CCR3_M_WRL1 (1 << CCR3_V_WRL1) 4264 #define CCR3_V_WRB2T 5 4265 #define CCR3_M_WRB2T (1 << CCR3_V_WRB2T) 4266 #define CCR3_V_WRTEG 6 4267 #define CCR3_M_WRTEG (0x3 << CCR3_V_WRTEG) 4268 #define CCR3_V_WRTEG0 6 4269 #define CCR3_M_WRTEG0 (1 << CCR3_V_WRTEG0) 4270 #define CCR3_V_WRTEG1 7 4271 #define CCR3_M_WRTEG1 (1 << CCR3_V_WRTEG1) 4272 #define CCR3_V_RDTEG 8 4273 #define CCR3_M_RDTEG (0x3 << CCR3_V_RDTEG) 4274 #define CCR3_V_RDTEG0 8 4275 #define CCR3_M_RDTEG0 (1 << CCR3_V_RDTEG0) 4276 #define CCR3_V_RDTEG1 9 4277 #define CCR3_M_RDTEG1 (1 << CCR3_V_RDTEG1) 4278 4279 /* 4280 ** CPU Cache Read Lead-off Cycles 4281 */ 4282 #define RDL_2T 0x000 4283 #define RDL_3T CCR3_M_RDL0 4284 #define RDL_4T CCR3_M_RDL1 4285 4286 /* 4287 ** CPU Cache Write Lead-off Cycles 4288 */ 4289 #define WRL_2T 0x000 4290 #define WRL_3T CCR3_M_WRL0 4291 #define WRL_4T CCR3_M_WRL1 4292 4293 /* 4294 ** Cache Write Enable Trailing Edge Timing for Write Hit Cycles 4295 */ 4296 #define WRTEG_SYNCH 0x000 4297 #define WRTEG_EARLY CCR3_M_WRTEG0 4298 4299 /* 4300 ** Cache Write Enable Trailing Edge Timing for Line Fill Cycles 4301 */ 4302 #define RDTEG_SYNCH 0x000 4303 #define RDTEG_EARLY CCR3_M_RDTEG0 4304 4305 /* 4306 ** 4307 ** Cache Control Register 4 (CCR4) - Index 0x403 4308 ** 4309 ** Loc Size Name Function 4310 ** ----- ---- ---- --------------------------------- 4311 ** <1> 1 TAGCK0 TAG RAM Timing Checking Point 0 4312 ** <2> 1 TAGCK1 TAG RAM Timing Checking Point 1 4313 ** <3> 1 DRTWETR0 Dirty Bit Write Timing Point 0 4314 ** <4> 1 DRTWETR1 Dirty Bit Write Timing Point 1 4315 ** 4316 ** <0><5:15> Reserved 4317 */ 4318 #define CCR_CCR4_REG 0x403 4319 #define CCR4_V_TAGCK 0 4320 #define CCR4_M_TAGCK (0x3 << CCR4_V_TAGCK) 4321 #define CCR4_V_TAGCK0 0 4322 #define CCR4_M_TAGCK0 (1 << CCR4_V_TAGCK0) 4323 #define CCR4_V_TAGCK1 1 4324 #define CCR4_M_TAGCK1 (1 << CCR4_V_TAGCK1) 4325 #define CCR4_V_DRTWETR 0 4326 #define CCR4_M_DRTWETR (0x3 << CCR4_V_DRTWETR) 4327 #define CCR4_V_DRTWETR0 0 4328 #define CCR4_M_DRTWETR0 (1 << CCR4_V_DRTWETR0) 4329 #define CCR4_V_DRTWETR1 1 4330 #define CCR4_M_DRTWETR1 (1 << CCR4_V_DRTWETR1) 4331 4332 /* 4333 ** TAG RAM Timing Checking Point 4334 */ 4335 #define TAGCK_ENDT1 0x000 4336 #define TAGCK_MIDT2_EARLY CCR4_M_TAGCK0 4337 #define TAGCK_MIDT2_NORM CCR4_M_TAGCK1 4338 #define TAGCK_ENDT2 (CCR4_M_TAGCK0 | CCR4_M_TAGCK1) 4339 4340 /* 4341 ** Dirty Bit Write Enable Trailing Edge Timing Point 4342 */ 4343 #define DRTWETR_EARLYEST CCR4_M_DRTWETR0 4344 #define DRTWETR_EARLYER CCR4_M_DRTWETR1 4345 #define DRTWETR_SYNCH (CCR4_M_DRTWETR0 | CCR4_M_DRTWETR1) 4346 4347 /* 4348 ** 4349 ** Global Control Register 1 (GCR1) - Index 0x700 4350 ** 4351 ** Loc Size Name Function 4352 ** ----- ---- ---- --------------------------------- 4353 ** <0> 1 CPUHITMWS CPU HITM# Sampling Wait State Selection 4354 ** 4355 ** <2:15> Reserved 4356 */ 4357 #define CCR_GCR1_REG 0x700 4358 #define CCR_GCR1_INIT 0x0000 4359 #define GCR1_V_CPUHITMWS 0 4360 #define GCR1_M_CPUHITMWS (1 << GCR1_V_CPUHITMWS) 4361 4362 /**************************************************** 4363 ** SEQUOIA-2 ** 4364 *****************************************************/ 4365 4366 /* 4367 ** 4368 ** AT Miscellaneous Control Register 1 (ATMCR1) - Index 0x300 4369 ** 4370 ** Loc Size Name Function 4371 ** ----- ---- ---- --------------------------------- 4372 ** <0> 1 SYSDIV0 SYSCLK Divisor Select 0 4373 ** <1> 1 SYSDIV1 SYSCLK Divisor Select 1 4374 ** <2> 1 SYSDIV2 SYSCLK Divisor Select 2 4375 ** <4> 1 IDERDYDLY0 Turbo IDE Cycle Ready Delay Select 0 4376 ** <5> 1 IDERDYDLY1 Turbo IDE Cycle Ready Delay Select 1 4377 ** <6> 1 B2BD0 Back-to-Back I/O Delay Select 0 4378 ** <7> 1 B2BD1 Back-to-Back I/O Delay Select 1 4379 ** <9> 1 PARITYEN Global Parity Enable 4380 ** <10> 1 ATREFDIS AT Bus Refresh Disable 4381 ** <11> 1 HIDREFEN Hidden AT Refresh Enable 4382 ** 4383 ** <3><8><12:15> Reserved 4384 */ 4385 #define SEQ2_ATMCR_REG 0x300 4386 #define SEQ2_ATMCR_INIT ( SYSDIV_4 | IDERDYDLY_2FS1XCLK | B2BD_3 | \ 4387 ATMCR1_M_ATREFDIS | ATMCR1_M_HIDREFEN ) 4388 #define ATMCR1_V_SYSDIV 0 4389 #define ATMCR1_M_SYSDIV (0x7 << ATMCR1_V_SYSDIV) 4390 #define ATMCR1_V_SYSDIV0 0 4391 #define ATMCR1_M_SYSDIV0 (1 << ATMCR1_V_SYSDIV0) 4392 #define ATMCR1_V_SYSDIV1 1 4393 #define ATMCR1_M_SYSDIV1 (1 << ATMCR1_V_SYSDIV1) 4394 #define ATMCR1_V_SYSDIV2 2 4395 #define ATMCR1_M_SYSDIV2 (1 << ATMCR1_V_SYSDIV2) 4396 #define ATMCR1_V_IDERDYDLY 4 4397 #define ATMCR1_M_IDERDYDLY (0x3 << ATMCR1_V_IDERDYDLY) 4398 #define ATMCR1_V_IDERDYDLY0 4 4399 #define ATMCR1_M_IDERDYDLY0 (1 << ATMCR1_V_IDERDYDLY0) 4400 #define ATMCR1_V_IDERDYDLY1 5 4401 #define ATMCR1_M_IDERDYDLY1 (1 << ATMCR1_V_IDERDYDLY1) 4402 #define ATMCR1_V_B2BD 6 4403 #define ATMCR1_M_B2BD (0x3 << ATMCR1_V_B2BD) 4404 #define ATMCR1_V_B2BD0 6 4405 #define ATMCR1_M_B2BD0 (1 << ATMCR1_V_B2BD0) 4406 #define ATMCR1_V_B2BD1 7 4407 #define ATMCR1_M_B2BD1 (1 << ATMCR1_V_B2BD1) 4408 #define ATMCR1_V_PARITYEN 9 4409 #define ATMCR1_M_PARITYEN (1 << ATMCR1_V_PARITYEN) 4410 #define ATMCR1_V_ATREFDIS 10 4411 #define ATMCR1_M_ATREFDIS (1 << ATMCR1_V_ATREFDIS) 4412 #define ATMCR1_V_HIDREFEN 11 4413 #define ATMCR1_M_HIDREFEN (1 << ATMCR1_V_HIDREFEN) 4414 4415 /* 4416 ** SYSCLK Divisor Select 4417 */ 4418 #define SYSDIV_3 ATMCR1_M_SYSDIV0 4419 #define SYSDIV_4 ATMCR1_M_SYSDIV1 4420 #define SYSDIV_5 (ATMCR1_M_SYSDIV0 | ATMCR1_M_SYSDIV1) 4421 #define SYSDIV_6 ATMCR1_M_SYSDIV2 4422 4423 /* 4424 ** Turbo IDE Cycle Ready Delay Select 4425 */ 4426 #define IDERDYDLY_NONE 0x000 4427 #define IDERDYDLY_1FS1XCLK ATMCR1_M_IDERDYDLY0 4428 #define IDERDYDLY_2FS1XCLK ATMCR1_M_IDERDYDLY1 4429 4430 /* 4431 ** Back-to-Back Delay Select 4432 */ 4433 #define B2BD_0 0x000 4434 #define B2BD_1 ATMCR1_M_B2BD0 4435 #define B2BD_2 ATMCR1_M_B2BD1 4436 #define B2BD_3 (ATMCR1_M_B2BD0 | ATMCR1_M_B2BD1) 4437 4438 /* 4439 ** 4440 ** AT Miscellaneous Control Register 2 (ATMCR2) - Index 0x301 4441 ** 4442 ** Loc Size Name Function 4443 ** ----- ---- ---- --------------------------------- 4444 ** <0> 1 IDECMDW0 Turbo IDE Command Width Select 0 4445 ** <1> 1 IDECMDW1 Turbo IDE Command Width Select 1 4446 ** <2> 1 IDECMDW2 Turbo IDE Command Width Select 2 4447 ** <3> 1 IDEB2BDLY0 Turbo IDE Back-to-Back Cycle Delay Select 0 4448 ** <4> 1 IDEB2BDLY1 Turbo IDE Back-to-Back Cycle Delay Select 1 4449 ** <5> 1 IDEB2BDLY2 Turbo IDE Back-to-Back Cycle Delay Select 2 4450 ** <6> 1 GIDENABLE Global IDE Enable 4451 ** <11> 1 EXTATADD Extended AT Address 4452 ** <12> 1 DLYLOCAL Delay Sampling Point for LOCAL# 4453 ** <14> 1 BSEREN BSER Enable 4454 ** <15> 1 DMACLKDIS DMA Modular Clock Disable 4455 ** 4456 ** <7:10><13> Reserved 4457 */ 4458 #define SEQ2_ATMCR2_REG 0x301 4459 #define SEQ2_ATMCR2_INIT ( ATMCR2_M_IDECMDW | ATMCR2_M_IDEB2BDLY | \ 4460 ATMCR2_M_IDEB2BDLY1 | ATMCR2_M_IDEB2BDLY2 | \ 4461 ATMCR2_M_GIDENABLE | ATMCR2_M_EXTATADD | \ 4462 ATMCR2_M_DLYLOCAL | ATMCR2_M_BSEREN ) 4463 #define ATMCR2_V_IDECMDW 0 4464 #define ATMCR2_M_IDECMDW (0x7 << ATMCR2_V_IDECMDW) 4465 #define ATMCR2_V_IDECMDW0 0 4466 #define ATMCR2_M_IDECMDW0 (1 << ATMCR2_V_IDECMDW0) 4467 #define ATMCR2_V_IDECMDW1 1 4468 #define ATMCR2_M_IDECMDW1 (1 << ATMCR2_V_IDECMDW1) 4469 #define ATMCR2_V_IDECMDW2 2 4470 #define ATMCR2_M_IDECMDW2 (1 << ATMCR2_V_IDECMDW2) 4471 #define ATMCR2_V_IDEB2BDLY 3 4472 #define ATMCR2_M_IDEB2BDLY (0x7 << ATMCR2_V_IDEB2BDLY) 4473 #define ATMCR2_V_IDEB2BDLY0 3 4474 #define ATMCR2_M_IDEB2BDLY0 (1 << ATMCR2_V_IDEB2BDLY0) 4475 #define ATMCR2_V_IDEB2BDLY1 4 4476 #define ATMCR2_M_IDEB2BDLY1 (1 << ATMCR2_V_IDEB2BDLY1) 4477 #define ATMCR2_V_IDEB2BDLY2 5 4478 #define ATMCR2_M_IDEB2BDLY2 (1 << ATMCR2_V_IDEB2BDLY2) 4479 #define ATMCR2_V_GIDENABLE 6 4480 #define ATMCR2_M_GIDENABLE (1 << ATMCR2_V_GIDENABLE) 4481 #define ATMCR2_V_EXTATADD 11 4482 #define ATMCR2_M_EXTATADD (1 << ATMCR2_V_EXTATADD) 4483 #define ATMCR2_V_DLYLOCAL 12 4484 #define ATMCR2_M_DLYLOCAL (1 << ATMCR2_V_DLYLOCAL) 4485 #define ATMCR2_V_BSEREN 14 4486 #define ATMCR2_M_BSEREN (1 << ATMCR2_V_BSEREN) 4487 #define ATMCR2_V_DMACLKDIS 15 4488 #define ATMCR2_M_DMACLKDIS (1 << ATMCR2_V_DMACLKDIS) 4489 4490 /* 4491 ** Turbo IDE Command Width Select 4492 */ 4493 #define IDECMDW_2FS1XCLK 0x000 4494 #define IDECMDW_3FS1XCLK ATMCR2_M_IDECMDW0 4495 #define IDECMDW_4FS1XCLK ATMCR2_M_IDECMDW1 4496 #define IDECMDW_5FS1XCLK (ATMCR2_M_IDECMDW0 | ATMCR2_M_IDECMDW1) 4497 #define IDECMDW_6FS1XCLK ATMCR2_M_IDECMDW2 4498 #define IDECMDW_7FS1XCLK (ATMCR2_M_IDECMDW0 | ATMCR2_M_IDECMDW2) 4499 #define IDECMDW_8FS1XCLK (ATMCR2_M_IDECMDW1 | ATMCR2_M_IDECMDW2) 4500 #define IDECMDW_9FS1XCLK (ATMCR2_M_IDECMDW0 | ATMCR2_M_IDECMDW1 | ATMCR2_M_IDECMDW2) 4501 4502 /* 4503 ** Turbo IDE Back=to-Back Cycle Delay Select 4504 */ 4505 #define IDEB2BDLY_2FS1XCLK 0x000 4506 #define IDEB2BDLY_3FS1XCLK ATMCR2_M_IDEB2BDLY0 4507 #define IDEB2BDLY_4FS1XCLK ATMCR2_M_IDEB2BDLY1 4508 #define IDEB2BDLY_5FS1XCLK (ATMCR2_M_IDEB2BDLY0 | ATMCR2_M_IDEB2BDLY1) 4509 #define IDEB2BDLY_6FS1XCLK ATMCR2_M_IDEB2BDLY2 4510 #define IDEB2BDLY_7FS1XCLK (ATMCR2_M_IDEB2BDLY0 | ATMCR2_M_IDEB2BDLY2) 4511 #define IDEB2BDLY_8FS1XCLK (ATMCR2_M_IDEB2BDLY1 | ATMCR2_M_IDEB2BDLY2) 4512 #define IDEB2BDLY_9FS1XCLK (ATMCR2_M_IDEB2BDLY0 | ATMCR2_M_IDEB2BDLY1 | ATMCR2_M_IDEB2BDLY2) 4513 4514 /* 4515 ** 4516 ** SEQUOIA-2 Pin Select Register (SEQ2PSR) - Index 0x302 4517 ** 4518 ** Loc Size Name Function 4519 ** ----- ---- ---- --------------------------------- 4520 ** <0> 1 DPBUSEN DP Bus Enable 4521 ** <1> 1 GPIOPINEN General Purpose I/O [7:4] Pin Enable 4522 ** <4> 1 IDEPINEN IDE Pin Enable 4523 ** <5> 1 LOCALPINEN Additional LOCAL Pin Enable 4524 ** <8> 1 ATREFADDEN AT Refresh Address Enable 4525 ** <14> 1 IDECMDEN IDE Command Enable 4526 ** <15> 1 SQ2TYPESEL SEQUOIA-2 Type Select 4527 ** 4528 ** <2:3><6:7><9:13> Reserved 4529 */ 4530 #define SEQ2_SEQ2PSR_REG 0x302 4531 #define SEQ2_SEQ2PSR_INIT ( SEQ2PSR_M_DPBUSEN | SEQ2PSR_M_LOCALPINEN ) 4532 #define SEQ2PSR_V_DPBUSEN 0 4533 #define SEQ2PSR_M_DPBUSEN (1 << SEQ2PSR_V_DPBUSEN) 4534 #define SEQ2PSR_V_GPIOPINEN 1 4535 #define SEQ2PSR_M_GPIOPINEN (1 << SEQ2PSR_V_GPIOPINEN) 4536 #define SEQ2PSR_V_IDEPINEN 4 4537 #define SEQ2PSR_M_IDEPINEN (1 << SEQ2PSR_V_IDEPINEN) 4538 #define SEQ2PSR_V_LOCALPINEN 5 4539 #define SEQ2PSR_M_LOCALPINEN (1 << SEQ2PSR_V_LOCALPINEN) 4540 #define SEQ2PSR_V_ATREFADDEN 8 4541 #define SEQ2PSR_M_ATREFADDEN (1 << SEQ2PSR_V_ATREFADDEN) 4542 #define SEQ2PSR_V_IDECMDEN 14 4543 #define SEQ2PSR_M_IDECMDEN (1 << SEQ2PSR_V_IDECMDEN) 4544 #define SEQ2PSR_V_SQ2TYPESEL 15 4545 #define SEQ2PSR_M_SQ2TYPESEL (1 << SEQ2PSR_V_SQ2TYPESEL) 4546 4547 /* 4548 ** 4549 ** Modular Clock Control Register (MCLKCR) - Index 0x303 4550 ** 4551 ** Loc Size Name Function 4552 ** ----- ---- ---- --------------------------------- 4553 ** <0> 1 ATMODCLKEN AT Modular Clock Enable 4554 ** <3> 1 SYNCTMREN Synchronous Timer Enable 4555 ** <4> 1 TMRCLKDIS Timer Clock Disable 4556 ** <5> 1 SYSCLKDIS ISA SYSCLK Disable 4557 ** 4558 ** <1:2><6:15> Reserved 4559 */ 4560 #define SEQ2_MCLKCR_REG 0x303 4561 #define SEQ2_MCLKCR_INIT 0x0000 4562 #define MCLKCR_V_ATMODCLKEN 0 4563 #define MCLKCR_M_ATMODCLKEN (1 << MCLKCR_V_ATMODCLKEN) 4564 #define MCLKCR_V_SYNCTMREN 3 4565 #define MCLKCR_M_SYNCTMREN (1 << MCLKCR_V_SYNCTMREN) 4566 #define MCLKCR_V_TMRCLKDIS 4 4567 #define MCLKCR_M_TMRCLKDIS (1 << MCLKCR_V_TMRCLKDIS) 4568 #define MCLKCR_V_SYSCLKDIS 5 4569 #define MCLKCR_M_SYSCLKDIS (1 << MCLKCR_V_SYSCLKDIS) 4570 4571 /* 4572 ** 4573 ** Optional GPIO Control Register (OGPIOCR) - Index 0x304 4574 ** 4575 ** Loc Size Name Function 4576 ** ----- ---- ---- --------------------------------- 4577 ** <0:7> 8 Reserved 4578 ** <8> 4 GPIODATA General Purpose I/O Data [4:7] 4579 ** <12> 4 GPIODIR General Purpose I/O Direction [4:7] 4580 ** 4581 */ 4582 #define SEQ2_OGPIOCR_REG 0x304 4583 #define SEQ2_OGPIOCR_INIT OGPIOCR_M_GPIODIR 4584 #define OOGPIOCR_V_GPIODATA 8 4585 #define OGPIOCR_M_GPIODATA (0xF << OGPIOCR_V_GPIODATA) 4586 #define OGPIOCR_V_GPIODATA4 8 4587 #define OGPIOCR_M_GPIODATA4 (1 << OGPIOCR_V_GPIODATA4) 4588 #define OGPIOCR_V_GPIODATA5 9 4589 #define OGPIOCR_M_GPIODATA5 (1 << OGPIOCR_V_GPIODATA5) 4590 #define OGPIOCR_V_GPIODATA6 10 4591 #define OGPIOCR_M_GPIODATA6 (1 << OGPIOCR_V_GPIODATA6) 4592 #define OGPIOCR_V_GPIODATA7 11 4593 #define OGPIOCR_M_GPIODATA7 (1 << OGPIOCR_V_GPIODATA7) 4594 #define OGPIOCR_V_GPIODIR 12 4595 #define OGPIOCR_M_GPIODIR (0xF << OGPIOCR_V_GPIODIR) 4596 #define OGPIOCR_V_GPIODIR4 12 4597 #define OGPIOCR_M_GPIODIR4 (1 << OGPIOCR_V_GPIODIR4) 4598 #define OGPIOCR_V_GPIODIR5 13 4599 #define OGPIOCR_M_GPIODIR5 (1 << OGPIOCR_V_GPIODIR5) 4600 #define OGPIOCR_V_GPIODIR6 14 4601 #define OGPIOCR_M_GPIODIR6 (1 << OGPIOCR_V_GPIODIR6) 4602 #define OGPIOCR_V_GPIODIR7 15 4603 #define OGPIOCR_M_GPIODIR7 (1 << OGPIOCR_V_GPIODIR7) 4604 4605 /* 4606 ** 4607 ** SEQUOIA-2 ID Register (SEQ2IDR) - Index 0x310 4608 ** 4609 ** Loc Size Name Function 4610 ** ----- ---- ---- --------------------------------- 4611 ** <0> 4 S2ID SEQUOIA-2 Revision ID Number 4612 ** 4613 ** <1:15> Reserved 4614 */ 4615 #define SEQ2_SEQ2IDR_REG 0x310 4616 #define SEQ2IDR_V_S2ID 0 4617 #define SEQ2IDR_M_S2ID (0xF << SEQ2IDR_V_S2ID) 4618 4619 /* 4620 ** 4621 ** Miscellaneous DMA Control Register 1 (MDMACR1) - Index 0x330 4622 ** 4623 ** Loc Size Name Function 4624 ** ----- ---- ---- --------------------------------- 4625 ** <8> 1 ENCDDMA Encoded DMA Acknowledges 4626 ** 4627 ** <0:7><9:15> Reserved 4628 */ 4629 #define SEQ2_MDMACR1_REG 0x330 4630 #define SEQ2_MDMACR1_INIT 0x0000 4631 #define MDMACR1_V_ENCDDMA 8 4632 #define MDMACR1_M_ENCDDMA (1 << MDMACR1_V_ENCDDMA) 4633 4634 /* 4635 ** 4636 ** Miscellaneous DMA Control Register 2 (MDMACR2) - Index 0x331 4637 ** 4638 ** Loc Size Name Function 4639 ** ----- ---- ---- --------------------------------- 4640 ** <0> 1 SEL3DMA Select 3 DMA 4641 ** <4> 1 DMA0CHSEL0 DMA Channel 0 Select 0 4642 ** <5> 1 DMA0CHSEL1 DMA Channel 0 Select 1 4643 ** <6> 1 DMA0CHSEL2 DMA Channel 0 Select 2 4644 ** <8> 1 DMA1CHSEL0 DMA Channel 1 Select 0 4645 ** <9> 1 DMA1CHSEL1 DMA Channel 1 Select 1 4646 ** <10> 1 DMA1CHSEL2 DMA Channel 1 Select 2 4647 ** <12> 1 DMA2CHSEL0 DMA Channel 2 Select 0 4648 ** <13> 1 DMA2CHSEL1 DMA Channel 2 Select 1 4649 ** <14> 1 DMA2CHSEL2 DMA Channel 2 Select 2 4650 ** 4651 ** <1:3><7><11><15> Reserved 4652 */ 4653 #define SEQ2_MDMACR2_REG 0x331 4654 #define SEQ2_MDMACR2_INIT 0x0000 4655 #define MDMACR2_V_SEL3DMA 0 4656 #define MDMACR2_M_SEL3DMA (1 << MDMACR2_V_SEL3DMA) 4657 #define MDMACR2_V_DMA0CHSEL 4 4658 #define MDMACR2_M_DMA0CHSEL (0x7 << MDMACR2_V_DMA0CHSEL) 4659 #define MDMACR2_V_DMA0CHSEL0 4 4660 #define MDMACR2_M_DMA0CHSEL0 (1 << MDMACR2_V_DMA0CHSEL0) 4661 #define MDMACR2_V_DMA0CHSEL1 5 4662 #define MDMACR2_M_DMA0CHSEL1 (1 << MDMACR2_V_DMA0CHSEL1) 4663 #define MDMACR2_V_DMA0CHSEL2 6 4664 #define MDMACR2_M_DMA0CHSEL2 (1 << MDMACR2_V_DMA0CHSEL2) 4665 #define MDMACR2_V_DMA1CHSEL 7 4666 #define MDMACR2_M_DMA1CHSEL (0x7 << MDMACR2_V_DMA1CHSEL) 4667 #define MDMACR2_V_DMA1CHSEL0 7 4668 #define MDMACR2_M_DMA1CHSEL0 (1 << MDMACR2_V_DMA1CHSEL0) 4669 #define MDMACR2_V_DMA1CHSEL1 8 4670 #define MDMACR2_M_DMA1CHSEL1 (1 << MDMACR2_V_DMA1CHSEL1) 4671 #define MDMACR2_V_DMA1CHSEL2 9 4672 #define MDMACR2_M_DMA1CHSEL2 (1 << MDMACR2_V_DMA1CHSEL2) 4673 #define MDMACR2_V_DMA2CHSEL 12 4674 #define MDMACR2_M_DMA2CHSEL (0x7 << MDMACR2_V_DMA2CHSEL) 4675 #define MDMACR2_V_DMA2CHSEL0 12 4676 #define MDMACR2_M_DMA2CHSEL0 (1 << MDMACR2_V_DMA2CHSEL0) 4677 #define MDMACR2_V_DMA2CHSEL1 13 4678 #define MDMACR2_M_DMA2CHSEL1 (1 << MDMACR2_V_DMA2CHSEL1) 4679 #define MDMACR2_V_DMA2CHSEL2 14 4680 #define MDMACR2_M_DMA2CHSEL2 (1 << MDMACR2_V_DMA2CHSEL2) 4681 4682 /* 4683 ** DMA Channel 0 Select 4684 */ 4685 #define DMA0CHSEL_0 0x000 4686 #define DMA0CHSEL_1 MDMACR2_M_DMA0CHSEL0 4687 #define DMA0CHSEL_2 MDMACR2_M_DMA0CHSEL1 4688 #define DMA0CHSEL_3 (MDMACR2_M_DMA0CHSEL0 | MDMACR2_M_DMA0CHSEL1) 4689 #define DMA0CHSEL_5 (MDMACR2_M_DMA0CHSEL0 | MDMACR2_M_DMA0CHSEL2) 4690 #define DMA0CHSEL_6 (MDMACR2_M_DMA0CHSEL1 | MDMACR2_M_DMA0CHSEL2) 4691 #define DMA0CHSEL_7 (MDMACR2_M_DMA0CHSEL0 | MDMACR2_M_DMA0CHSEL1 | MDMACR2_M_DMA0CHSEL1) 4692 4693 /* 4694 ** DMA Channel 1 Select 4695 */ 4696 #define DMA1CHSEL_0 0x000 4697 #define DMA1CHSEL_1 MDMACR2_M_DMA1CHSEL0 4698 #define DMA1CHSEL_2 MDMACR2_M_DMA1CHSEL1 4699 #define DMA1CHSEL_3 (MDMACR2_M_DMA1CHSEL0 | MDMACR2_M_DMA1CHSEL1) 4700 #define DMA1CHSEL_5 (MDMACR2_M_DMA1CHSEL0 | MDMACR2_M_DMA1CHSEL2) 4701 #define DMA1CHSEL_6 (MDMACR2_M_DMA1CHSEL1 | MDMACR2_M_DMA1CHSEL2) 4702 #define DMA1CHSEL_7 (MDMACR2_M_DMA1CHSEL0 | MDMACR2_M_DMA1CHSEL1 | MDMACR2_M_DMA1CHSEL1) 4703 4704 /* 4705 ** DMA Channel 2 Select 4706 */ 4707 #define DMA2CHSEL_0 0x000 4708 #define DMA2CHSEL_1 MDMACR2_M_DMA2CHSEL0 4709 #define DMA2CHSEL_2 MDMACR2_M_DMA2CHSEL1 4710 #define DMA2CHSEL_3 (MDMACR2_M_DMA2CHSEL0 | MDMACR2_M_DMA2CHSEL1) 4711 #define DMA2CHSEL_5 (MDMACR2_M_DMA2CHSEL0 | MDMACR2_M_DMA2CHSEL2) 4712 #define DMA2CHSEL_6 (MDMACR2_M_DMA2CHSEL1 | MDMACR2_M_DMA2CHSEL2) 4713 #define DMA2CHSEL_7 (MDMACR2_M_DMA2CHSEL0 | MDMACR2_M_DMA2CHSEL1 | MDMACR2_M_DMA2CHSEL1) 4714 4715 /* 4716 ** 4717 ** Burst Bus Interrupt Control Register (BBICR) - Index 0x340 4718 ** 4719 ** Loc Size Name Function 4720 ** ----- ---- ---- --------------------------------- 4721 ** <0> 1 ENBINT Enable Burst Bus Interrupt 4722 ** <1> 1 BINTLOCKCLR Burst Interrupt Interlock Clear 4723 ** <2> 1 BINTLOCKDIS Burst Interrupt Interlock Disable 4724 ** 4725 ** <3:15> Reserved 4726 */ 4727 #define SEQ2_BBICR_REG 0x340 4728 #define SEQ2_BBICR_INIT 0x0000 4729 #define BBICR_V_ENBINT 0 4730 #define BBICR_M_ENBINT (1 << BBICR_V_ENBINT) 4731 #define BBICR_V_BINTLOCKCLR 1 4732 #define BBICR_M_BINTLOCKCLR (1 << BBICR_V_BINTLOCKCLR) 4733 #define BBICR_V_BINTLOCKDIS 2 4734 #define BBICR_M_BINTLOCKDIS (1 << BBICR_V_BINTLOCKDIS) 4735 4736 /* 4737 ** 4738 ** Primary Activities IRQ Mask Register (PAIMR) - Index 0x350 4739 ** 4740 ** Loc Size Name Function 4741 ** ----- ---- ---- --------------------------------- 4742 ** <1> 1 PAMSKIRQ1 IRQ1 Primary Activity Mask Enable 4743 ** <3> 1 PAMSKIRQ3 IRQ3 Primary Activity Mask Enable 4744 ** <4> 1 PAMSKIRQ4 IRQ4 Primary Activity Mask Enable 4745 ** <5> 1 PAMSKIRQ5 IRQ5 Primary Activity Mask Enable 4746 ** <6> 1 PAMSKIRQ6 IRQ6 Primary Activity Mask Enable 4747 ** <7> 1 PAMSKIRQ7 IRQ7 Primary Activity Mask Enable 4748 ** <8> 1 PAMSKIRQ8 IRQ8 Primary Activity Mask Enable 4749 ** <9> 1 PAMSKIRQ9 IRQ9 Primary Activity Mask Enable 4750 ** <10> 1 PAMSKIRQ10 IRQ10 Primary Activity Mask Enable 4751 ** <11> 1 PAMSKIRQ11 IRQ11 Primary Activity Mask Enable 4752 ** <12> 1 PAMSKIRQ12 IRQ12 Primary Activity Mask Enable 4753 ** <13> 1 PAMSKIRQ13 IRQ13 Primary Activity Mask Enable 4754 ** <14> 1 PAMSKIRQ14 IRQ14 Primary Activity Mask Enable 4755 ** <15> 1 PAMSKIRQ15 IRQ15 Primary Activity Mask Enable 4756 ** 4757 ** <0><2> Reserved 4758 */ 4759 #define SEQ2_PAIMR_REG 0x350 4760 #define SEQ2_PAIMR_INIT ( PAIMR_M_PAMSKIRQ1 | PAIMR_M_PAMSKIRQ3 | \ 4761 PAIMR_M_PAMSKIRQ4 | PAIMR_M_PAMSKIRQ5 | \ 4762 PAIMR_M_PAMSKIRQ6 | PAIMR_M_PAMSKIRQ7 | \ 4763 PAIMR_M_PAMSKIRQ8 | PAIMR_M_PAMSKIRQ9 | \ 4764 PAIMR_M_PAMSKIRQ10 | PAIMR_M_PAMSKIRQ11 | \ 4765 PAIMR_M_PAMSKIRQ12 | PAIMR_M_PAMSKIRQ13 | \ 4766 PAIMR_M_PAMSKIRQ14 ) 4767 #define PAIMR_V_PAMSKIRQ1 1 4768 #define PAIMR_M_PAMSKIRQ1 (1 << PAIMR_V_PAMSKIRQ1) 4769 #define PAIMR_V_PAMSKIRQ3 3 4770 #define PAIMR_M_PAMSKIRQ3 (1 << PAIMR_V_PAMSKIRQ3) 4771 #define PAIMR_V_PAMSKIRQ4 4 4772 #define PAIMR_M_PAMSKIRQ4 (1 << PAIMR_V_PAMSKIRQ4) 4773 #define PAIMR_V_PAMSKIRQ5 5 4774 #define PAIMR_M_PAMSKIRQ5 (1 << PAIMR_V_PAMSKIRQ5) 4775 #define PAIMR_V_PAMSKIRQ6 6 4776 #define PAIMR_M_PAMSKIRQ6 (1 << PAIMR_V_PAMSKIRQ6) 4777 #define PAIMR_V_PAMSKIRQ7 7 4778 #define PAIMR_M_PAMSKIRQ7 (1 << PAIMR_V_PAMSKIRQ7) 4779 #define PAIMR_V_PAMSKIRQ8 8 4780 #define PAIMR_M_PAMSKIRQ8 (1 << PAIMR_V_PAMSKIRQ8) 4781 #define PAIMR_V_PAMSKIRQ9 9 4782 #define PAIMR_M_PAMSKIRQ9 (1 << PAIMR_V_PAMSKIRQ9) 4783 #define PAIMR_V_PAMSKIRQ10 10 4784 #define PAIMR_M_PAMSKIRQ10 (1 << PAIMR_V_PAMSKIRQ10) 4785 #define PAIMR_V_PAMSKIRQ11 11 4786 #define PAIMR_M_PAMSKIRQ11 (1 << PAIMR_V_PAMSKIRQ11) 4787 #define PAIMR_V_PAMSKIRQ12 12 4788 #define PAIMR_M_PAMSKIRQ12 (1 << PAIMR_V_PAMSKIRQ12) 4789 #define PAIMR_V_PAMSKIRQ13 13 4790 #define PAIMR_M_PAMSKIRQ13 (1 << PAIMR_V_PAMSKIRQ13) 4791 #define PAIMR_V_PAMSKIRQ14 14 4792 #define PAIMR_M_PAMSKIRQ14 (1 << PAIMR_V_PAMSKIRQ14) 4793 #define PAIMR_V_PAMSKIRQ15 15 4794 #define PAIMR_M_PAMSKIRQ15 (1 << PAIMR_V_PAMSKIRQ15) 4795 4796 /* 4797 ** 4798 ** PMI Trigger Source IRQ Active Register (PTSIAR) - Index 0x351 4799 ** 4800 ** Loc Size Name Function 4801 ** ----- ---- ---- --------------------------------- 4802 ** <0> 1 PMIDETBACTV PMI Trigger Source DeTurbo Switch Active 4803 ** <1> 1 PMIIRQ1ACTV PMI Trigger Source IRQ1 Active 4804 ** <3> 1 PMIIRQ3ACTV PMI Trigger Source IRQ3 Active 4805 ** <4> 1 PMIIRQ4ACTV PMI Trigger Source IRQ4 Active 4806 ** <5> 1 PMIIRQ5ACTV PMI Trigger Source IRQ5 Active 4807 ** <6> 1 PMIIRQ6ACTV PMI Trigger Source IRQ6 Active 4808 ** <7> 1 PMIIRQ7ACTV PMI Trigger Source IRQ7 Active 4809 ** <8> 1 PMIIRQ8ACTV PMI Trigger Source IRQ8 Active 4810 ** <9> 1 PMIIRQ9ACTV PMI Trigger Source IRQ9 Active 4811 ** <10> 1 PMIIRQ10ACTV PMI Trigger Source IRQ10 Active 4812 ** <11> 1 PMIIRQ11ACTV PMI Trigger Source IRQ11 Active 4813 ** <12> 1 PMIIRQ12ACTV PMI Trigger Source IRQ12 Active 4814 ** <13> 1 PMIIRQ13ACTV PMI Trigger Source IRQ13 Active 4815 ** <14> 1 PMIIRQ14ACTV PMI Trigger Source IRQ14 Active 4816 ** <15> 1 PMIIRQ15ACTV PMI Trigger Source IRQ15 Active 4817 ** 4818 ** <2> Reserved 4819 */ 4820 #define SEQ2_PTSIAR_REG 0x351 4821 #define SEQ2_PTSIAR_INIT 0x0000 4822 #define PTSIAR_V_PMIDETBACTV 0 4823 #define PTSIAR_M_PMIDETBACTV (1 << PTSIAR_V_PMIDETBACTV) 4824 #define PTSIAR_V_PMIIRQ1ACTV 1 4825 #define PTSIAR_M_PMIIRQ1ACTV (1 << PTSIAR_V_PMIIRQ1ACTV) 4826 #define PTSIAR_V_PMIIRQ3ACTV 3 4827 #define PTSIAR_M_PMIIRQ3ACTV (1 << PTSIAR_V_PMIIRQ3ACTV) 4828 #define PTSIAR_V_PMIIRQ4ACTV 4 4829 #define PTSIAR_M_PMIIRQ4ACTV (1 << PTSIAR_V_PMIIRQ4ACTV) 4830 #define PTSIAR_V_PMIIRQ5ACTV 5 4831 #define PTSIAR_M_PMIIRQ5ACTV (1 << PTSIAR_V_PMIIRQ5ACTV) 4832 #define PTSIAR_V_PMIIRQ6ACTV 6 4833 #define PTSIAR_M_PMIIRQ6ACTV (1 << PTSIAR_V_PMIIRQ6ACTV) 4834 #define PTSIAR_V_PMIIRQ7ACTV 7 4835 #define PTSIAR_M_PMIIRQ7ACTV (1 << PTSIAR_V_PMIIRQ7ACTV) 4836 #define PTSIAR_V_PMIIRQ8ACTV 8 4837 #define PTSIAR_M_PMIIRQ8ACTV (1 << PTSIAR_V_PMIIRQ8ACTV) 4838 #define PTSIAR_V_PMIIRQ9ACTV 9 4839 #define PTSIAR_M_PMIIRQ9ACTV (1 << PTSIAR_V_PMIIRQ9ACTV) 4840 #define PTSIAR_V_PMIIRQ10ACTV 10 4841 #define PTSIAR_M_PMIIRQ10ACTV (1 << PTSIAR_V_PMIIRQ10ACTV) 4842 #define PTSIAR_V_PMIIRQ11ACTV 11 4843 #define PTSIAR_M_PMIIRQ11ACTV (1 << PTSIAR_V_PMIIRQ11ACTV) 4844 #define PTSIAR_V_PMIIRQ12ACTV 12 4845 #define PTSIAR_M_PMIIRQ12ACTV (1 << PTSIAR_V_PMIIRQ12ACTV) 4846 #define PTSIAR_V_PMIIRQ13ACTV 13 4847 #define PTSIAR_M_PMIIRQ13ACTV (1 << PTSIAR_V_PMIIRQ13ACTV) 4848 #define PTSIAR_V_PMIIRQ14ACTV 14 4849 #define PTSIAR_M_PMIIRQ14ACTV (1 << PTSIAR_V_PMIIRQ14ACTV) 4850 #define PTSIAR_V_PMIIRQ15ACTV 15 4851 #define PTSIAR_M_PMIIRQ15ACTV (1 << PTSIAR_V_PMIIRQ15ACTV) 4852 4853 /* 4854 ** 4855 ** PMI Trigger Source IRQ Mask Register (PTSIMR) - Index 0x352 4856 ** 4857 ** Loc Size Name Function 4858 ** ----- ---- ---- --------------------------------- 4859 ** <0> 1 IMSKDETURBO DeTurbo Switch Triggering PMI Mask Enable 4860 ** <1> 1 IMSKIRQ1 IRQ1 Triggering PMI Mask Enable 4861 ** <3> 1 IMSKIRQ3 IRQ3 Triggering PMI Mask Enable 4862 ** <4> 1 IMSKIRQ4 IRQ4 Triggering PMI Mask Enable 4863 ** <5> 1 IMSKIRQ5 IRQ5 Triggering PMI Mask Enable 4864 ** <6> 1 IMSKIRQ6 IRQ6 Triggering PMI Mask Enable 4865 ** <7> 1 IMSKIRQ7 IRQ7 Triggering PMI Mask Enable 4866 ** <8> 1 IMSKIRQ8 IRQ8 Triggering PMI Mask Enable 4867 ** <9> 1 IMSKIRQ9 IRQ9 Triggering PMI Mask Enable 4868 ** <10> 1 IMSKIRQ10 IRQ10 Triggering PMI Mask Enable 4869 ** <11> 1 IMSKIRQ11 IRQ11 Triggering PMI Mask Enable 4870 ** <12> 1 IMSKIRQ12 IRQ12 Triggering PMI Mask Enable 4871 ** <13> 1 IMSKIRQ13 IRQ13 Triggering PMI Mask Enable 4872 ** <14> 1 IMSKIRQ14 IRQ14 Triggering PMI Mask Enable 4873 ** <15> 1 IMSKIRQ15 IRQ15 Triggering PMI Mask Enable 4874 ** 4875 ** <2> Reserved 4876 */ 4877 #define SEQ2_PTSIMR_REG 0x352 4878 #define SEQ2_PTSIMR_INIT ( PTSIMR_M_IMSKDETURBO | PTSIMR_M_IMSKIRQ1 | \ 4879 PTSIMR_M_IMSKIRQ3 | PTSIMR_M_IMSKIRQ4 | \ 4880 PTSIMR_M_IMSKIRQ5 | PTSIMR_M_IMSKIRQ6 | \ 4881 PTSIMR_M_IMSKIRQ7 | PTSIMR_M_IMSKIRQ8 | \ 4882 PTSIMR_M_IMSKIRQ9 | PTSIMR_M_IMSKIRQ10 | \ 4883 PTSIMR_M_IMSKIRQ11 | PTSIMR_M_IMSKIRQ12 | \ 4884 PTSIMR_M_IMSKIRQ13 | PTSIMR_M_IMSKIRQ14 | \ 4885 PTSIMR_M_IMSKIRQ15 ) 4886 #define PTSIMR_V_IMSKDETURBO 0 4887 #define PTSIMR_M_IMSKDETURBO (1 << PTSIMR_V_IMSKDETURBO) 4888 #define PTSIMR_V_IMSKIRQ1 1 4889 #define PTSIMR_M_IMSKIRQ1 (1 << PTSIMR_V_IMSKIRQ1) 4890 #define PTSIMR_V_IMSKIRQ3 3 4891 #define PTSIMR_M_IMSKIRQ3 (1 << PTSIMR_V_IMSKIRQ3) 4892 #define PTSIMR_V_IMSKIRQ4 4 4893 #define PTSIMR_M_IMSKIRQ4 (1 << PTSIMR_V_IMSKIRQ4) 4894 #define PTSIMR_V_IMSKIRQ5 5 4895 #define PTSIMR_M_IMSKIRQ5 (1 << PTSIMR_V_IMSKIRQ5) 4896 #define PTSIMR_V_IMSKIRQ6 6 4897 #define PTSIMR_M_IMSKIRQ6 (1 << PTSIMR_V_IMSKIRQ6) 4898 #define PTSIMR_V_IMSKIRQ7 7 4899 #define PTSIMR_M_IMSKIRQ7 (1 << PTSIMR_V_IMSKIRQ7) 4900 #define PTSIMR_V_IMSKIRQ8 8 4901 #define PTSIMR_M_IMSKIRQ8 (1 << PTSIMR_V_IMSKIRQ8) 4902 #define PTSIMR_V_IMSKIRQ9 9 4903 #define PTSIMR_M_IMSKIRQ9 (1 << PTSIMR_V_IMSKIRQ9) 4904 #define PTSIMR_V_IMSKIRQ10 10 4905 #define PTSIMR_M_IMSKIRQ10 (1 << PTSIMR_V_IMSKIRQ10) 4906 #define PTSIMR_V_IMSKIRQ11 11 4907 #define PTSIMR_M_IMSKIRQ11 (1 << PTSIMR_V_IMSKIRQ11) 4908 #define PTSIMR_V_IMSKIRQ12 12 4909 #define PTSIMR_M_IMSKIRQ12 (1 << PTSIMR_V_IMSKIRQ12) 4910 #define PTSIMR_V_IMSKIRQ13 13 4911 #define PTSIMR_M_IMSKIRQ13 (1 << PTSIMR_V_IMSKIRQ13) 4912 #define PTSIMR_V_IMSKIRQ14 14 4913 #define PTSIMR_M_IMSKIRQ14 (1 << PTSIMR_V_IMSKIRQ14) 4914 #define PTSIMR_V_IMSKIRQ15 15 4915 #define PTSIMR_M_IMSKIRQ15 (1 << PTSIMR_V_IMSKIRQ15) 4916 4917 /* 4918 ** 4919 ** IRQ Secondary Activity Enable Register (ISAER) - Index 0x353 4920 ** 4921 ** Loc Size Name Function 4922 ** ----- ---- ---- --------------------------------- 4923 ** <0> 1 SAMSKIRQ Secondary Activity Mask for IRQs 4924 ** 4925 ** <1:15> Reserved 4926 */ 4927 #define SEQ2_ISAER_REG 0x353 4928 #define SEQ2_ISAER_INIT ISAER_M_SAMSKIRQ 4929 #define ISAER_V_SAMSKIRQ 0 4930 #define ISAER_M_SAMSKIRQ (1 << ISAER_V_SAMSKIRQ) 4931 4932 /* 4933 ** Shadow Read Registers 4934 ** 4935 */ 4936 4937 #define SR_M_DATAMSK 0xF 4938 4939 /* 4940 ** 8254 Counter Registers 4941 */ 4942 #define SRR_54CTR0_REG1 0x500 4943 #define SRR_54CTR0_REG2 0x501 4944 #define SRR_54CTR0_REG3 0x506 4945 #define SRR_54CTR1_REG1 0x502 4946 #define SRR_54CTR1_REG2 0x503 4947 #define SRR_54CTR1_REG3 0x507 4948 #define SRR_54CTR2_REG1 0x504 4949 #define SRR_54CTR2_REG2 0x505 4950 #define SRR_54CTR2_REG3 0x508 4951 4952 /* 4953 ** 8237 DMA Controller Registers 4954 */ 4955 #define SRR_37CTRL0_REG1 0x510 4956 #define SRR_37CTRL0_REG2 0x511 4957 #define SRR_37CTRL0_REG3 0x512 4958 #define SRR_37CTRL1_REG4 0x513 4959 #define SRR_37CTRL1_REG5 0x514 4960 #define SRR_37CTRL1_REG6 0x515 4961 #define SRR_37CTRL2_REG7 0x516 4962 #define SRR_37CTRL2_REG8 0x517 4963 4964 /* 4965 ** 8259 Interrupt Controller Registers 4966 */ 4967 #define SRR_59CTRL0_REG1 0x520 4968 #define SRR_59CTRL0_REG2 0x521 4969 #define SRR_59CTRL0_REG3 0x522 4970 #define SRR_59CTRL1_REG4 0x523 4971 #define SRR_59CTRL1_REG5 0x524 4972 #define SRR_59CTRL1_REG6 0x525 4973 #define SRR_59CTRL2_REG7 0x526 4974 #define SRR_59CTRL2_REG8 0x527 4975 #define SRR_59CTRL2_REG9 0x528 4976 #define SRR_59CTRL2_REG10 0x529 4977 #define SRR_59CTRL2_REG11 0x52A 4978 #define SRR_59CTRL2_REG12 0x52B 4979 4980 /* 4981 ** IBM-AT Standard Registers 4982 ** 4983 */ 4984 4985 /* 4986 ** 4987 ** Register 1 (REG1) - Access Address 0x061 4988 ** 4989 ** Loc Size Name Function 4990 ** ----- ---- ---- --------------------------------- 4991 ** <0> 1 TMR2EN Timer 2 Enable 4992 ** <1> 1 SPKREN Speaker Enable 4993 ** <2> 1 PARDIS Parity Disable 4994 ** <3> 1 IOCHKDIS I/O Channel Check Disable 4995 ** <4> 1 REFRTGL Refresh Toggle 4996 ** <5> 1 TMR2OUT Timer 2 Output 4997 ** <6> 1 IOCKERR I/O Channel Check Error 4998 ** <7> 1 PARERR Parity Error 4999 ** 5000 */ 5001 #define ATSR_REG1_REG 0x061 5002 #define ATSR_REG1_INIT REG1_M_PARDIS 5003 #define REG1_V_TMR2EN 0 5004 #define REG1_M_TMR2EN (1 << REG1_V_TMR2EN) 5005 #define REG1_V_SPKREN 1 5006 #define REG1_M_SPKREN (1 << REG1_V_SPKREN) 5007 #define REG1_V_PARDIS 2 5008 #define REG1_M_PARDIS (1 << REG1_V_PARDIS) 5009 #define REG1_V_IOCHKDIS 3 5010 #define REG1_M_IOCHKDIS (1 << REG1_V_IOCHKDIS) 5011 #define REG1_V_REFRTGL 4 5012 #define REG1_M_REFRTGL (1 << REG1_V_REFRTGL) 5013 #define REG1_V_TMR2OUT 5 5014 #define REG1_M_TMR2OUT (1 << REG1_V_TMR2OUT) 5015 #define REG1_V_IOCKERR 6 5016 #define REG1_M_IOCKERR (1 << REG1_V_IOCKERR) 5017 #define REG1_V_PARERR 7 5018 #define REG1_M_PARERR (1 << REG1_V_PARERR) 5019 5020 /* 5021 ** 5022 ** Register 2 (REG2) - Access Address 0x070 5023 ** 5024 ** Loc Size Name Function 5025 ** ----- ---- ---- --------------------------------- 5026 ** <0> 6 RTCINDX Real Timer Clock Index 5027 ** <7> 1 NMIDIS NMI Mask Disable 5028 ** 5029 */ 5030 #define ATSR_REG2_REG 0x070 5031 #define ATSR_REG2_INIT REG2_M_NMIDIS 5032 #define REG2_V_RTCINDX 0 5033 #define REG2_M_RTCINDX (0x7F << REG2_V_RTCINDX) 5034 #define REG2_V_NMIDIS 7 5035 #define REG2_M_NMIDIS (1 << REG2_V_NMIDIS) 5036 5037 /* 5038 ** 5039 ** Register 3 (REG3) - Access Address 0x092 5040 ** 5041 ** Loc Size Name Function 5042 ** ----- ---- ---- --------------------------------- 5043 ** <0> 1 FSTRST Alternate Fast CPU Reset 5044 ** <1> 1 FGATEA20 Fast GATEA20 5045 ** <3> 1 SCLOCK1 Security Lock 1 5046 ** 5047 ** <2><4:7> Reserved 5048 */ 5049 #define ATSR_REG3_REG 0x092 5050 #define ATSR_REG3_INIT 0x0000 5051 #define REG3_V_FSTRST 0 5052 #define REG3_M_FSTRST (1 << REG3_V_FSTRST) 5053 #define REG3_V_FGATEA20 1 5054 #define REG3_M_FGATEA20 (1 << REG3_V_FGATEA20) 5055 #define REG3_V_SCLOCK1 3 5056 #define REG3_M_SCLOCK1 (1 << REG3_V_SCLOCK1) 5057 5058 5059 5060 5061 5062 5063 #ifndef __LANGUAGE_ASM__ 5064 #ifndef _LOCORE 5065 5066 void sequoiaInit(void); 5067 void sequoiaLock(void); 5068 void sequoiaUnlock(void); 5069 bool sequoiaIsLocked(void); /* for DIAGNOSTIC checks only */ 5070 void sequoiaWrite(int reg,u_int16_t value); 5071 void sequoiaRead(int reg,u_int16_t * value_ptr); 5072 5073 /* x console functions */ 5074 void consXTvOn(void); 5075 void consXTvOff(void); 5076 5077 5078 /* smart card reader functions */ 5079 int scrGetDetect(void); 5080 void scrSetPower(int value); 5081 void scrSetClock(int value); 5082 void scrSetReset(int value); 5083 void scrSetDataHighZ(void); 5084 void scrSetData(int value); 5085 int scrGetData(void); 5086 5087 5088 /* just used to debug scr - remove when done - ejg */ 5089 void scrToggleTestPin(void); 5090 5091 5092 /* biled functions */ 5093 void ledNetActive(void); 5094 void ledNetBlock(void); 5095 void ledNetUnblock(void); 5096 void ledPanic(void); 5097 5098 5099 /* function to get the hw rev */ 5100 int hwGetRev(void); 5101 5102 /* debug led functions */ 5103 #define LED_DEBUG_STATE_0 0 5104 #define LED_DEBUG_STATE_1 1 5105 #define LED_DEBUG_STATE_2 2 5106 #define LED_DEBUG_STATE_3 3 5107 5108 #define LED_DEBUG_YELLOW_OFF 4 5109 #define LED_DEBUG_YELLOW_ON 5 5110 5111 #define LED_DEBUG_GREEN_OFF 6 5112 #define LED_DEBUG_GREEN_ON 7 5113 5114 5115 void ledSetDebug(int command); 5116 5117 #endif /* _LOCORE */ 5118 #endif /* __LANGUAGE_ASM__ */ 5119 5120 #endif /* SEQUOIAH */ 5121
Indexes created Sun Sep 21 16:09:51 GMT 2025